LXR linux/arch/arm/mach-u300/timer.c

   1/*
   2 *
   3 * arch/arm/mach-u300/timer.c
   4 *
   5 *
   6 * Copyright (C) 2007-2009 ST-Ericsson AB
   7 * License terms: GNU General Public License (GPL) version 2
   8 * Timer COH 901 328, runs the OS timer interrupt.
   9 * Author: Linus Walleij <linus.walleij@stericsson.com>
  10 */
  11#include <linux/interrupt.h>
  12#include <linux/sched.h>
  13#include <linux/time.h>
  14#include <linux/timex.h>
  15#include <linux/clockchips.h>
  16#include <linux/clocksource.h>
  17#include <linux/types.h>
  18#include <linux/io.h>
  19#include <linux/clk.h>
  20#include <linux/err.h>
  21
  22#include <mach/hardware.h>
  23
  24/* Generic stuff */
  25#include <asm/sched_clock.h>
  26#include <asm/mach/map.h>
  27#include <asm/mach/time.h>
  28#include <asm/mach/irq.h>
  29
  30/* Be able to sleep for atleast 4 seconds (usually more) */
  31#define APPTIMER_MIN_RANGE 4
  32
  33/*
  34 * APP side special timer registers
  35 * This timer contains four timers which can fire an interrupt each.
  36 * OS (operating system) timer @ 32768 Hz
  37 * DD (device driver) timer @ 1 kHz
  38 * GP1 (general purpose 1) timer @ 1MHz
  39 * GP2 (general purpose 2) timer @ 1MHz
  40 */
  41
  42/* Reset OS Timer 32bit (-/W) */
  43#define U300_TIMER_APP_ROST                                     (0x0000)
  44#define U300_TIMER_APP_ROST_TIMER_RESET                         (0x00000000)
  45/* Enable OS Timer 32bit (-/W) */
  46#define U300_TIMER_APP_EOST                                     (0x0004)
  47#define U300_TIMER_APP_EOST_TIMER_ENABLE                        (0x00000000)
  48/* Disable OS Timer 32bit (-/W) */
  49#define U300_TIMER_APP_DOST                                     (0x0008)
  50#define U300_TIMER_APP_DOST_TIMER_DISABLE                       (0x00000000)
  51/* OS Timer Mode Register 32bit (-/W) */
  52#define U300_TIMER_APP_SOSTM                                    (0x000c)
  53#define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS                    (0x00000000)
  54#define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT                      (0x00000001)
  55/* OS Timer Status Register 32bit (R/-) */
  56#define U300_TIMER_APP_OSTS                                     (0x0010)
  57#define U300_TIMER_APP_OSTS_TIMER_STATE_MASK                    (0x0000000F)
  58#define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE                    (0x00000001)
  59#define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE                  (0x00000002)
  60#define U300_TIMER_APP_OSTS_ENABLE_IND                          (0x00000010)
  61#define U300_TIMER_APP_OSTS_MODE_MASK                           (0x00000020)
  62#define U300_TIMER_APP_OSTS_MODE_CONTINUOUS                     (0x00000000)
  63#define U300_TIMER_APP_OSTS_MODE_ONE_SHOT                       (0x00000020)
  64#define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND                     (0x00000040)
  65#define U300_TIMER_APP_OSTS_IRQ_PENDING_IND                     (0x00000080)
  66/* OS Timer Current Count Register 32bit (R/-) */
  67#define U300_TIMER_APP_OSTCC                                    (0x0014)
  68/* OS Timer Terminal Count Register 32bit (R/W) */
  69#define U300_TIMER_APP_OSTTC                                    (0x0018)
  70/* OS Timer Interrupt Enable Register 32bit (-/W) */
  71#define U300_TIMER_APP_OSTIE                                    (0x001c)
  72#define U300_TIMER_APP_OSTIE_IRQ_DISABLE                        (0x00000000)
  73#define U300_TIMER_APP_OSTIE_IRQ_ENABLE                         (0x00000001)
  74/* OS Timer Interrupt Acknowledge Register 32bit (-/W) */
  75#define U300_TIMER_APP_OSTIA                                    (0x0020)
  76#define U300_TIMER_APP_OSTIA_IRQ_ACK                            (0x00000080)
  77
  78/* Reset DD Timer 32bit (-/W) */
  79#define U300_TIMER_APP_RDDT                                     (0x0040)
  80#define U300_TIMER_APP_RDDT_TIMER_RESET                         (0x00000000)
  81/* Enable DD Timer 32bit (-/W) */
  82#define U300_TIMER_APP_EDDT                                     (0x0044)
  83#define U300_TIMER_APP_EDDT_TIMER_ENABLE                        (0x00000000)
  84/* Disable DD Timer 32bit (-/W) */
  85#define U300_TIMER_APP_DDDT                                     (0x0048)
  86#define U300_TIMER_APP_DDDT_TIMER_DISABLE                       (0x00000000)
  87/* DD Timer Mode Register 32bit (-/W) */
  88#define U300_TIMER_APP_SDDTM                                    (0x004c)
  89#define U300_TIMER_APP_SDDTM_MODE_CONTINUOUS                    (0x00000000)
  90#define U300_TIMER_APP_SDDTM_MODE_ONE_SHOT                      (0x00000001)
  91/* DD Timer Status Register 32bit (R/-) */
  92#define U300_TIMER_APP_DDTS                                     (0x0050)
  93#define U300_TIMER_APP_DDTS_TIMER_STATE_MASK                    (0x0000000F)
  94#define U300_TIMER_APP_DDTS_TIMER_STATE_IDLE                    (0x00000001)
  95#define U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE                  (0x00000002)
  96#define U300_TIMER_APP_DDTS_ENABLE_IND                          (0x00000010)
  97#define U300_TIMER_APP_DDTS_MODE_MASK                           (0x00000020)
  98#define U300_TIMER_APP_DDTS_MODE_CONTINUOUS                     (0x00000000)
  99#define U300_TIMER_APP_DDTS_MODE_ONE_SHOT                       (0x00000020)
 100#define U300_TIMER_APP_DDTS_IRQ_ENABLED_IND                     (0x00000040)
 101#define U300_TIMER_APP_DDTS_IRQ_PENDING_IND                     (0x00000080)
 102/* DD Timer Current Count Register 32bit (R/-) */
 103#define U300_TIMER_APP_DDTCC                                    (0x0054)
 104/* DD Timer Terminal Count Register 32bit (R/W) */
 105#define U300_TIMER_APP_DDTTC                                    (0x0058)
 106/* DD Timer Interrupt Enable Register 32bit (-/W) */
 107#define U300_TIMER_APP_DDTIE                                    (0x005c)
 108#define U300_TIMER_APP_DDTIE_IRQ_DISABLE                        (0x00000000)
 109#define U300_TIMER_APP_DDTIE_IRQ_ENABLE                         (0x00000001)
 110/* DD Timer Interrupt Acknowledge Register 32bit (-/W) */
 111#define U300_TIMER_APP_DDTIA                                    (0x0060)
 112#define U300_TIMER_APP_DDTIA_IRQ_ACK                            (0x00000080)
 113
 114/* Reset GP1 Timer 32bit (-/W) */
 115#define U300_TIMER_APP_RGPT1                                    (0x0080)
 116#define U300_TIMER_APP_RGPT1_TIMER_RESET                        (0x00000000)
 117/* Enable GP1 Timer 32bit (-/W) */
 118#define U300_TIMER_APP_EGPT1                                    (0x0084)
 119#define U300_TIMER_APP_EGPT1_TIMER_ENABLE                       (0x00000000)
 120/* Disable GP1 Timer 32bit (-/W) */
 121#define U300_TIMER_APP_DGPT1                                    (0x0088)
 122#define U300_TIMER_APP_DGPT1_TIMER_DISABLE                      (0x00000000)
 123/* GP1 Timer Mode Register 32bit (-/W) */
 124#define U300_TIMER_APP_SGPT1M                                   (0x008c)
 125#define U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS                   (0x00000000)
 126#define U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT                     (0x00000001)
 127/* GP1 Timer Status Register 32bit (R/-) */
 128#define U300_TIMER_APP_GPT1S                                    (0x0090)
 129#define U300_TIMER_APP_GPT1S_TIMER_STATE_MASK                   (0x0000000F)
 130#define U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE                   (0x00000001)
 131#define U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE                 (0x00000002)
 132#define U300_TIMER_APP_GPT1S_ENABLE_IND                         (0x00000010)
 133#define U300_TIMER_APP_GPT1S_MODE_MASK                          (0x00000020)
 134#define U300_TIMER_APP_GPT1S_MODE_CONTINUOUS                    (0x00000000)
 135#define U300_TIMER_APP_GPT1S_MODE_ONE_SHOT                      (0x00000020)
 136#define U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND                    (0x00000040)
 137#define U300_TIMER_APP_GPT1S_IRQ_PENDING_IND                    (0x00000080)
 138/* GP1 Timer Current Count Register 32bit (R/-) */
 139#define U300_TIMER_APP_GPT1CC                                   (0x0094)
 140/* GP1 Timer Terminal Count Register 32bit (R/W) */
 141#define U300_TIMER_APP_GPT1TC                                   (0x0098)
 142/* GP1 Timer Interrupt Enable Register 32bit (-/W) */
 143#define U300_TIMER_APP_GPT1IE                                   (0x009c)
 144#define U300_TIMER_APP_GPT1IE_IRQ_DISABLE                       (0x00000000)
 145#define U300_TIMER_APP_GPT1IE_IRQ_ENABLE                        (0x00000001)
 146/* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */
 147#define U300_TIMER_APP_GPT1IA                                   (0x00a0)
 148#define U300_TIMER_APP_GPT1IA_IRQ_ACK                           (0x00000080)
 149
 150/* Reset GP2 Timer 32bit (-/W) */
 151#define U300_TIMER_APP_RGPT2                                    (0x00c0)
 152#define U300_TIMER_APP_RGPT2_TIMER_RESET                        (0x00000000)
 153/* Enable GP2 Timer 32bit (-/W) */
 154#define U300_TIMER_APP_EGPT2                                    (0x00c4)
 155#define U300_TIMER_APP_EGPT2_TIMER_ENABLE                       (0x00000000)
 156/* Disable GP2 Timer 32bit (-/W) */
 157#define U300_TIMER_APP_DGPT2                                    (0x00c8)
 158#define U300_TIMER_APP_DGPT2_TIMER_DISABLE                      (0x00000000)
 159/* GP2 Timer Mode Register 32bit (-/W) */
 160#define U300_TIMER_APP_SGPT2M                                   (0x00cc)
 161#define U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS                   (0x00000000)
 162#define U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT                     (0x00000001)
 163/* GP2 Timer Status Register 32bit (R/-) */
 164#define U300_TIMER_APP_GPT2S                                    (0x00d0)
 165#define U300_TIMER_APP_GPT2S_TIMER_STATE_MASK                   (0x0000000F)
 166#define U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE                   (0x00000001)
 167#define U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE                 (0x00000002)
 168#define U300_TIMER_APP_GPT2S_ENABLE_IND                         (0x00000010)
 169#define U300_TIMER_APP_GPT2S_MODE_MASK                          (0x00000020)
 170#define U300_TIMER_APP_GPT2S_MODE_CONTINUOUS                    (0x00000000)
 171#define U300_TIMER_APP_GPT2S_MODE_ONE_SHOT                      (0x00000020)
 172#define U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND                    (0x00000040)
 173#define U300_TIMER_APP_GPT2S_IRQ_PENDING_IND                    (0x00000080)
 174/* GP2 Timer Current Count Register 32bit (R/-) */
 175#define U300_TIMER_APP_GPT2CC                                   (0x00d4)
 176/* GP2 Timer Terminal Count Register 32bit (R/W) */
 177#define U300_TIMER_APP_GPT2TC                                   (0x00d8)
 178/* GP2 Timer Interrupt Enable Register 32bit (-/W) */
 179#define U300_TIMER_APP_GPT2IE                                   (0x00dc)
 180#define U300_TIMER_APP_GPT2IE_IRQ_DISABLE                       (0x00000000)
 181#define U300_TIMER_APP_GPT2IE_IRQ_ENABLE                        (0x00000001)
 182/* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */
 183#define U300_TIMER_APP_GPT2IA                                   (0x00e0)
 184#define U300_TIMER_APP_GPT2IA_IRQ_ACK                           (0x00000080)
 185
 186/* Clock request control register - all four timers */
 187#define U300_TIMER_APP_CRC                                      (0x100)
 188#define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE                 (0x00000001)
 189
 190#define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
 191#define US_PER_TICK ((1000000 + (HZ/2)) / HZ)
 192
 193/*
 194 * The u300_set_mode() function is always called first, if we
 195 * have oneshot timer active, the oneshot scheduling function
 196 * u300_set_next_event() is called immediately after.
 197 */
 198static void u300_set_mode(enum clock_event_mode mode,
 199                          struct clock_event_device *evt)
 200{
 201        switch (mode) {
 202        case CLOCK_EVT_MODE_PERIODIC:
 203                /* Disable interrupts on GPT1 */
 204                writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 205                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 206                /* Disable GP1 while we're reprogramming it. */
 207                writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 208                       U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
 209                /*
 210                 * Set the periodic mode to a certain number of ticks per
 211                 * jiffy.
 212                 */
 213                writel(TICKS_PER_JIFFY,
 214                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
 215                /*
 216                 * Set continuous mode, so the timer keeps triggering
 217                 * interrupts.
 218                 */
 219                writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
 220                       U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
 221                /* Enable timer interrupts */
 222                writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
 223                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 224                /* Then enable the OS timer again */
 225                writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
 226                       U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
 227                break;
 228        case CLOCK_EVT_MODE_ONESHOT:
 229                /* Just break; here? */
 230                /*
 231                 * The actual event will be programmed by the next event hook,
 232                 * so we just set a dummy value somewhere at the end of the
 233                 * universe here.
 234                 */
 235                /* Disable interrupts on GPT1 */
 236                writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 237                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 238                /* Disable GP1 while we're reprogramming it. */
 239                writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 240                       U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
 241                /*
 242                 * Expire far in the future, u300_set_next_event() will be
 243                 * called soon...
 244                 */
 245                writel(0xFFFFFFFF, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
 246                /* We run one shot per tick here! */
 247                writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
 248                       U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
 249                /* Enable interrupts for this timer */
 250                writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
 251                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 252                /* Enable timer */
 253                writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
 254                       U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
 255                break;
 256        case CLOCK_EVT_MODE_UNUSED:
 257        case CLOCK_EVT_MODE_SHUTDOWN:
 258                /* Disable interrupts on GP1 */
 259                writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 260                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 261                /* Disable GP1 */
 262                writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 263                       U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
 264                break;
 265        case CLOCK_EVT_MODE_RESUME:
 266                /* Ignore this call */
 267                break;
 268        }
 269}
 270
 271/*
 272 * The app timer in one shot mode obviously has to be reprogrammed
 273 * in EXACTLY this sequence to work properly. Do NOT try to e.g. replace
 274 * the interrupt disable + timer disable commands with a reset command,
 275 * it will fail miserably. Apparently (and I found this the hard way)
 276 * the timer is very sensitive to the instruction order, though you don't
 277 * get that impression from the data sheet.
 278 */
 279static int u300_set_next_event(unsigned long cycles,
 280                               struct clock_event_device *evt)
 281
 282{
 283        /* Disable interrupts on GPT1 */
 284        writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 285               U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 286        /* Disable GP1 while we're reprogramming it. */
 287        writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 288               U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
 289        /* Reset the General Purpose timer 1. */
 290        writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
 291               U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
 292        /* IRQ in n * cycles */
 293        writel(cycles, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
 294        /*
 295         * We run one shot per tick here! (This is necessary to reconfigure,
 296         * the timer will tilt if you don't!)
 297         */
 298        writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
 299               U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
 300        /* Enable timer interrupts */
 301        writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
 302               U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 303        /* Then enable the OS timer again */
 304        writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
 305               U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
 306        return 0;
 307}
 308
 309
 310/* Use general purpose timer 1 as clock event */
 311static struct clock_event_device clockevent_u300_1mhz = {
 312        .name           = "GPT1",
 313        .rating         = 300, /* Reasonably fast and accurate clock event */
 314        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 315        .set_next_event = u300_set_next_event,
 316        .set_mode       = u300_set_mode,
 317};
 318
 319/* Clock event timer interrupt handler */
 320static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
 321{
 322        struct clock_event_device *evt = &clockevent_u300_1mhz;
 323        /* ACK/Clear timer IRQ for the APP GPT1 Timer */
 324        writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
 325                U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IA);
 326        evt->event_handler(evt);
 327        return IRQ_HANDLED;
 328}
 329
 330static struct irqaction u300_timer_irq = {
 331        .name           = "U300 Timer Tick",
 332        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 333        .handler        = u300_timer_interrupt,
 334};
 335
 336/* Use general purpose timer 2 as clock source */
 337static cycle_t u300_get_cycles(struct clocksource *cs)
 338{
 339        return (cycles_t) readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
 340}
 341
 342static struct clocksource clocksource_u300_1mhz = {
 343        .name           = "GPT2",
 344        .rating         = 300, /* Reasonably fast and accurate clock source */
 345        .read           = u300_get_cycles,
 346        .mask           = CLOCKSOURCE_MASK(32), /* 32 bits */
 347        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 348};
 349
 350/*
 351 * Override the global weak sched_clock symbol with this
 352 * local implementation which uses the clocksource to get some
 353 * better resolution when scheduling the kernel. We accept that
 354 * this wraps around for now, since it is just a relative time
 355 * stamp. (Inspired by OMAP implementation.)
 356 */
 357static DEFINE_CLOCK_DATA(cd);
 358
 359unsigned long long notrace sched_clock(void)
 360{
 361        u32 cyc = readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
 362        return cyc_to_sched_clock(&cd, cyc, (u32)~0);
 363}
 364
 365static void notrace u300_update_sched_clock(void)
 366{
 367        u32 cyc = readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
 368        update_sched_clock(&cd, cyc, (u32)~0);
 369}
 370
 371
 372/*
 373 * This sets up the system timers, clock source and clock event.
 374 */
 375static void __init u300_timer_init(void)
 376{
 377        struct clk *clk;
 378        unsigned long rate;
 379
 380        /* Clock the interrupt controller */
 381        clk = clk_get_sys("apptimer", NULL);
 382        BUG_ON(IS_ERR(clk));
 383        clk_enable(clk);
 384        rate = clk_get_rate(clk);
 385
 386        init_sched_clock(&cd, u300_update_sched_clock, 32, rate);
 387
 388        /*
 389         * Disable the "OS" and "DD" timers - these are designed for Symbian!
 390         * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
 391         */
 392        writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
 393                U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC);
 394        writel(U300_TIMER_APP_ROST_TIMER_RESET,
 395                U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST);
 396        writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
 397                U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST);
 398        writel(U300_TIMER_APP_RDDT_TIMER_RESET,
 399                U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT);
 400        writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
 401                U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT);
 402
 403        /* Reset the General Purpose timer 1. */
 404        writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
 405                U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
 406
 407        /* Set up the IRQ handler */
 408        setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq);
 409
 410        /* Reset the General Purpose timer 2 */
 411        writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
 412                U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2);
 413        /* Set this timer to run around forever */
 414        writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC);
 415        /* Set continuous mode so it wraps around */
 416        writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
 417               U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M);
 418        /* Disable timer interrupts */
 419        writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
 420                U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE);
 421        /* Then enable the GP2 timer to use as a free running us counter */
 422        writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
 423                U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2);
 424
 425        if (clocksource_register_hz(&clocksource_u300_1mhz, rate))
 426                printk(KERN_ERR "timer: failed to initialize clock "
 427                       "source %s\n", clocksource_u300_1mhz.name);
 428
 429        clockevents_calc_mult_shift(&clockevent_u300_1mhz,
 430                                    rate, APPTIMER_MIN_RANGE);
 431        /* 32bit counter, so 32bits delta is max */
 432        clockevent_u300_1mhz.max_delta_ns =
 433                clockevent_delta2ns(0xffffffff, &clockevent_u300_1mhz);
 434        /* This timer is slow enough to set for 1 cycle == 1 MHz */
 435        clockevent_u300_1mhz.min_delta_ns =
 436                clockevent_delta2ns(1, &clockevent_u300_1mhz);
 437        clockevent_u300_1mhz.cpumask = cpumask_of(0);
 438        clockevents_register_device(&clockevent_u300_1mhz);
 439        /*
 440         * TODO: init and register the rest of the timers too, they can be
 441         * used by hrtimers!
 442         */
 443}
 444
 445/*
 446 * Very simple system timer that only register the clock event and
 447 * clock source.
 448 */
 449struct sys_timer u300_timer = {
 450        .init           = u300_timer_init,
 451};
 452