LXR linux/arch/arm/mm/alignment.c

   1/*
   2 *  linux/arch/arm/mm/alignment.c
   3 *
   4 *  Copyright (C) 1995  Linus Torvalds
   5 *  Modifications for ARM processor (c) 1995-2001 Russell King
   6 *  Thumb alignment fault fixups (c) 2004 MontaVista Software, Inc.
   7 *  - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
   8 *    Copyright (C) 1996, Cygnus Software Technologies Ltd.
   9 *
  10 * This program is free software; you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License version 2 as
  12 * published by the Free Software Foundation.
  13 */
  14#include <linux/moduleparam.h>
  15#include <linux/compiler.h>
  16#include <linux/kernel.h>
  17#include <linux/errno.h>
  18#include <linux/string.h>
  19#include <linux/proc_fs.h>
  20#include <linux/seq_file.h>
  21#include <linux/init.h>
  22#include <linux/sched.h>
  23#include <linux/uaccess.h>
  24
  25#include <asm/unaligned.h>
  26
  27#include "fault.h"
  28
  29/*
  30 * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
  31 * /proc/sys/debug/alignment, modified and integrated into
  32 * Linux 2.1 by Russell King
  33 *
  34 * Speed optimisations and better fault handling by Russell King.
  35 *
  36 * *** NOTE ***
  37 * This code is not portable to processors with late data abort handling.
  38 */
  39#define CODING_BITS(i)  (i & 0x0e000000)
  40
  41#define LDST_I_BIT(i)   (i & (1 << 26))         /* Immediate constant   */
  42#define LDST_P_BIT(i)   (i & (1 << 24))         /* Preindex             */
  43#define LDST_U_BIT(i)   (i & (1 << 23))         /* Add offset           */
  44#define LDST_W_BIT(i)   (i & (1 << 21))         /* Writeback            */
  45#define LDST_L_BIT(i)   (i & (1 << 20))         /* Load                 */
  46
  47#define LDST_P_EQ_U(i)  ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
  48
  49#define LDSTHD_I_BIT(i) (i & (1 << 22))         /* double/half-word immed */
  50#define LDM_S_BIT(i)    (i & (1 << 22))         /* write CPSR from SPSR */
  51
  52#define RN_BITS(i)      ((i >> 16) & 15)        /* Rn                   */
  53#define RD_BITS(i)      ((i >> 12) & 15)        /* Rd                   */
  54#define RM_BITS(i)      (i & 15)                /* Rm                   */
  55
  56#define REGMASK_BITS(i) (i & 0xffff)
  57#define OFFSET_BITS(i)  (i & 0x0fff)
  58
  59#define IS_SHIFT(i)     (i & 0x0ff0)
  60#define SHIFT_BITS(i)   ((i >> 7) & 0x1f)
  61#define SHIFT_TYPE(i)   (i & 0x60)
  62#define SHIFT_LSL       0x00
  63#define SHIFT_LSR       0x20
  64#define SHIFT_ASR       0x40
  65#define SHIFT_RORRRX    0x60
  66
  67#define BAD_INSTR       0xdeadc0de
  68
  69/* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
  70#define IS_T32(hi16) \
  71        (((hi16) & 0xe000) == 0xe000 && ((hi16) & 0x1800))
  72
  73static unsigned long ai_user;
  74static unsigned long ai_sys;
  75static unsigned long ai_skipped;
  76static unsigned long ai_half;
  77static unsigned long ai_word;
  78static unsigned long ai_dword;
  79static unsigned long ai_multi;
  80static int ai_usermode;
  81
  82core_param(alignment, ai_usermode, int, 0600);
  83
  84#define UM_WARN         (1 << 0)
  85#define UM_FIXUP        (1 << 1)
  86#define UM_SIGNAL       (1 << 2)
  87
  88#ifdef CONFIG_PROC_FS
  89static const char *usermode_action[] = {
  90        "ignored",
  91        "warn",
  92        "fixup",
  93        "fixup+warn",
  94        "signal",
  95        "signal+warn"
  96};
  97
  98static int alignment_proc_show(struct seq_file *m, void *v)
  99{
 100        seq_printf(m, "User:\t\t%lu\n", ai_user);
 101        seq_printf(m, "System:\t\t%lu\n", ai_sys);
 102        seq_printf(m, "Skipped:\t%lu\n", ai_skipped);
 103        seq_printf(m, "Half:\t\t%lu\n", ai_half);
 104        seq_printf(m, "Word:\t\t%lu\n", ai_word);
 105        if (cpu_architecture() >= CPU_ARCH_ARMv5TE)
 106                seq_printf(m, "DWord:\t\t%lu\n", ai_dword);
 107        seq_printf(m, "Multi:\t\t%lu\n", ai_multi);
 108        seq_printf(m, "User faults:\t%i (%s)\n", ai_usermode,
 109                        usermode_action[ai_usermode]);
 110
 111        return 0;
 112}
 113
 114static int alignment_proc_open(struct inode *inode, struct file *file)
 115{
 116        return single_open(file, alignment_proc_show, NULL);
 117}
 118
 119static ssize_t alignment_proc_write(struct file *file, const char __user *buffer,
 120                                    size_t count, loff_t *pos)
 121{
 122        char mode;
 123
 124        if (count > 0) {
 125                if (get_user(mode, buffer))
 126                        return -EFAULT;
 127                if (mode >= '0' && mode <= '5')
 128                        ai_usermode = mode - '0';
 129        }
 130        return count;
 131}
 132
 133static const struct file_operations alignment_proc_fops = {
 134        .open           = alignment_proc_open,
 135        .read           = seq_read,
 136        .llseek         = seq_lseek,
 137        .release        = single_release,
 138        .write          = alignment_proc_write,
 139};
 140#endif /* CONFIG_PROC_FS */
 141
 142union offset_union {
 143        unsigned long un;
 144          signed long sn;
 145};
 146
 147#define TYPE_ERROR      0
 148#define TYPE_FAULT      1
 149#define TYPE_LDST       2
 150#define TYPE_DONE       3
 151
 152#ifdef __ARMEB__
 153#define BE              1
 154#define FIRST_BYTE_16   "mov    %1, %1, ror #8\n"
 155#define FIRST_BYTE_32   "mov    %1, %1, ror #24\n"
 156#define NEXT_BYTE       "ror #24"
 157#else
 158#define BE              0
 159#define FIRST_BYTE_16
 160#define FIRST_BYTE_32
 161#define NEXT_BYTE       "lsr #8"
 162#endif
 163
 164#define __get8_unaligned_check(ins,val,addr,err)        \
 165        __asm__(                                        \
 166 ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
 167 THUMB( "1:     "ins"   %1, [%2]\n"     )               \
 168 THUMB( "       add     %2, %2, #1\n"   )               \
 169        "2:\n"                                          \
 170        "       .pushsection .fixup,\"ax\"\n"           \
 171        "       .align  2\n"                            \
 172        "3:     mov     %0, #1\n"                       \
 173        "       b       2b\n"                           \
 174        "       .popsection\n"                          \
 175        "       .pushsection __ex_table,\"a\"\n"        \
 176        "       .align  3\n"                            \
 177        "       .long   1b, 3b\n"                       \
 178        "       .popsection\n"                          \
 179        : "=r" (err), "=&r" (val), "=r" (addr)          \
 180        : "0" (err), "2" (addr))
 181
 182#define __get16_unaligned_check(ins,val,addr)                   \
 183        do {                                                    \
 184                unsigned int err = 0, v, a = addr;              \
 185                __get8_unaligned_check(ins,v,a,err);            \
 186                val =  v << ((BE) ? 8 : 0);                     \
 187                __get8_unaligned_check(ins,v,a,err);            \
 188                val |= v << ((BE) ? 0 : 8);                     \
 189                if (err)                                        \
 190                        goto fault;                             \
 191        } while (0)
 192
 193#define get16_unaligned_check(val,addr) \
 194        __get16_unaligned_check("ldrb",val,addr)
 195
 196#define get16t_unaligned_check(val,addr) \
 197        __get16_unaligned_check("ldrbt",val,addr)
 198
 199#define __get32_unaligned_check(ins,val,addr)                   \
 200        do {                                                    \
 201                unsigned int err = 0, v, a = addr;              \
 202                __get8_unaligned_check(ins,v,a,err);            \
 203                val =  v << ((BE) ? 24 :  0);                   \
 204                __get8_unaligned_check(ins,v,a,err);            \
 205                val |= v << ((BE) ? 16 :  8);                   \
 206                __get8_unaligned_check(ins,v,a,err);            \
 207                val |= v << ((BE) ?  8 : 16);                   \
 208                __get8_unaligned_check(ins,v,a,err);            \
 209                val |= v << ((BE) ?  0 : 24);                   \
 210                if (err)                                        \
 211                        goto fault;                             \
 212        } while (0)
 213
 214#define get32_unaligned_check(val,addr) \
 215        __get32_unaligned_check("ldrb",val,addr)
 216
 217#define get32t_unaligned_check(val,addr) \
 218        __get32_unaligned_check("ldrbt",val,addr)
 219
 220#define __put16_unaligned_check(ins,val,addr)                   \
 221        do {                                                    \
 222                unsigned int err = 0, v = val, a = addr;        \
 223                __asm__( FIRST_BYTE_16                          \
 224         ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
 225         THUMB( "1:     "ins"   %1, [%2]\n"     )               \
 226         THUMB( "       add     %2, %2, #1\n"   )               \
 227                "       mov     %1, %1, "NEXT_BYTE"\n"          \
 228                "2:     "ins"   %1, [%2]\n"                     \
 229                "3:\n"                                          \
 230                "       .pushsection .fixup,\"ax\"\n"           \
 231                "       .align  2\n"                            \
 232                "4:     mov     %0, #1\n"                       \
 233                "       b       3b\n"                           \
 234                "       .popsection\n"                          \
 235                "       .pushsection __ex_table,\"a\"\n"        \
 236                "       .align  3\n"                            \
 237                "       .long   1b, 4b\n"                       \
 238                "       .long   2b, 4b\n"                       \
 239                "       .popsection\n"                          \
 240                : "=r" (err), "=&r" (v), "=&r" (a)              \
 241                : "0" (err), "1" (v), "2" (a));                 \
 242                if (err)                                        \
 243                        goto fault;                             \
 244        } while (0)
 245
 246#define put16_unaligned_check(val,addr)  \
 247        __put16_unaligned_check("strb",val,addr)
 248
 249#define put16t_unaligned_check(val,addr) \
 250        __put16_unaligned_check("strbt",val,addr)
 251
 252#define __put32_unaligned_check(ins,val,addr)                   \
 253        do {                                                    \
 254                unsigned int err = 0, v = val, a = addr;        \
 255                __asm__( FIRST_BYTE_32                          \
 256         ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
 257         THUMB( "1:     "ins"   %1, [%2]\n"     )               \
 258         THUMB( "       add     %2, %2, #1\n"   )               \
 259                "       mov     %1, %1, "NEXT_BYTE"\n"          \
 260         ARM(   "2:     "ins"   %1, [%2], #1\n" )               \
 261         THUMB( "2:     "ins"   %1, [%2]\n"     )               \
 262         THUMB( "       add     %2, %2, #1\n"   )               \
 263                "       mov     %1, %1, "NEXT_BYTE"\n"          \
 264         ARM(   "3:     "ins"   %1, [%2], #1\n" )               \
 265         THUMB( "3:     "ins"   %1, [%2]\n"     )               \
 266         THUMB( "       add     %2, %2, #1\n"   )               \
 267                "       mov     %1, %1, "NEXT_BYTE"\n"          \
 268                "4:     "ins"   %1, [%2]\n"                     \
 269                "5:\n"                                          \
 270                "       .pushsection .fixup,\"ax\"\n"           \
 271                "       .align  2\n"                            \
 272                "6:     mov     %0, #1\n"                       \
 273                "       b       5b\n"                           \
 274                "       .popsection\n"                          \
 275                "       .pushsection __ex_table,\"a\"\n"        \
 276                "       .align  3\n"                            \
 277                "       .long   1b, 6b\n"                       \
 278                "       .long   2b, 6b\n"                       \
 279                "       .long   3b, 6b\n"                       \
 280                "       .long   4b, 6b\n"                       \
 281                "       .popsection\n"                          \
 282                : "=r" (err), "=&r" (v), "=&r" (a)              \
 283                : "0" (err), "1" (v), "2" (a));                 \
 284                if (err)                                        \
 285                        goto fault;                             \
 286        } while (0)
 287
 288#define put32_unaligned_check(val,addr) \
 289        __put32_unaligned_check("strb", val, addr)
 290
 291#define put32t_unaligned_check(val,addr) \
 292        __put32_unaligned_check("strbt", val, addr)
 293
 294static void
 295do_alignment_finish_ldst(unsigned long addr, unsigned long instr, struct pt_regs *regs, union offset_union offset)
 296{
 297        if (!LDST_U_BIT(instr))
 298                offset.un = -offset.un;
 299
 300        if (!LDST_P_BIT(instr))
 301                addr += offset.un;
 302
 303        if (!LDST_P_BIT(instr) || LDST_W_BIT(instr))
 304                regs->uregs[RN_BITS(instr)] = addr;
 305}
 306
 307static int
 308do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *regs)
 309{
 310        unsigned int rd = RD_BITS(instr);
 311
 312        ai_half += 1;
 313
 314        if (user_mode(regs))
 315                goto user;
 316
 317        if (LDST_L_BIT(instr)) {
 318                unsigned long val;
 319                get16_unaligned_check(val, addr);
 320
 321                /* signed half-word? */
 322                if (instr & 0x40)
 323                        val = (signed long)((signed short) val);
 324
 325                regs->uregs[rd] = val;
 326        } else
 327                put16_unaligned_check(regs->uregs[rd], addr);
 328
 329        return TYPE_LDST;
 330
 331 user:
 332        if (LDST_L_BIT(instr)) {
 333                unsigned long val;
 334                get16t_unaligned_check(val, addr);
 335
 336                /* signed half-word? */
 337                if (instr & 0x40)
 338                        val = (signed long)((signed short) val);
 339
 340                regs->uregs[rd] = val;
 341        } else
 342                put16t_unaligned_check(regs->uregs[rd], addr);
 343
 344        return TYPE_LDST;
 345
 346 fault:
 347        return TYPE_FAULT;
 348}
 349
 350static int
 351do_alignment_ldrdstrd(unsigned long addr, unsigned long instr,
 352                      struct pt_regs *regs)
 353{
 354        unsigned int rd = RD_BITS(instr);
 355        unsigned int rd2;
 356        int load;
 357
 358        if ((instr & 0xfe000000) == 0xe8000000) {
 359                /* ARMv7 Thumb-2 32-bit LDRD/STRD */
 360                rd2 = (instr >> 8) & 0xf;
 361                load = !!(LDST_L_BIT(instr));
 362        } else if (((rd & 1) == 1) || (rd == 14))
 363                goto bad;
 364        else {
 365                load = ((instr & 0xf0) == 0xd0);
 366                rd2 = rd + 1;
 367        }
 368
 369        ai_dword += 1;
 370
 371        if (user_mode(regs))
 372                goto user;
 373
 374        if (load) {
 375                unsigned long val;
 376                get32_unaligned_check(val, addr);
 377                regs->uregs[rd] = val;
 378                get32_unaligned_check(val, addr + 4);
 379                regs->uregs[rd2] = val;
 380        } else {
 381                put32_unaligned_check(regs->uregs[rd], addr);
 382                put32_unaligned_check(regs->uregs[rd2], addr + 4);
 383        }
 384
 385        return TYPE_LDST;
 386
 387 user:
 388        if (load) {
 389                unsigned long val;
 390                get32t_unaligned_check(val, addr);
 391                regs->uregs[rd] = val;
 392                get32t_unaligned_check(val, addr + 4);
 393                regs->uregs[rd2] = val;
 394        } else {
 395                put32t_unaligned_check(regs->uregs[rd], addr);
 396                put32t_unaligned_check(regs->uregs[rd2], addr + 4);
 397        }
 398
 399        return TYPE_LDST;
 400 bad:
 401        return TYPE_ERROR;
 402 fault:
 403        return TYPE_FAULT;
 404}
 405
 406static int
 407do_alignment_ldrstr(unsigned long addr, unsigned long instr, struct pt_regs *regs)
 408{
 409        unsigned int rd = RD_BITS(instr);
 410
 411        ai_word += 1;
 412
 413        if ((!LDST_P_BIT(instr) && LDST_W_BIT(instr)) || user_mode(regs))
 414                goto trans;
 415
 416        if (LDST_L_BIT(instr)) {
 417                unsigned int val;
 418                get32_unaligned_check(val, addr);
 419                regs->uregs[rd] = val;
 420        } else
 421                put32_unaligned_check(regs->uregs[rd], addr);
 422        return TYPE_LDST;
 423
 424 trans:
 425        if (LDST_L_BIT(instr)) {
 426                unsigned int val;
 427                get32t_unaligned_check(val, addr);
 428                regs->uregs[rd] = val;
 429        } else
 430                put32t_unaligned_check(regs->uregs[rd], addr);
 431        return TYPE_LDST;
 432
 433 fault:
 434        return TYPE_FAULT;
 435}
 436
 437/*
 438 * LDM/STM alignment handler.
 439 *
 440 * There are 4 variants of this instruction:
 441 *
 442 * B = rn pointer before instruction, A = rn pointer after instruction
 443 *              ------ increasing address ----->
 444 *              |    | r0 | r1 | ... | rx |    |
 445 * PU = 01             B                    A
 446 * PU = 11        B                    A
 447 * PU = 00        A                    B
 448 * PU = 10             A                    B
 449 */
 450static int
 451do_alignment_ldmstm(unsigned long addr, unsigned long instr, struct pt_regs *regs)
 452{
 453        unsigned int rd, rn, correction, nr_regs, regbits;
 454        unsigned long eaddr, newaddr;
 455
 456        if (LDM_S_BIT(instr))
 457                goto bad;
 458
 459        correction = 4; /* processor implementation defined */
 460        regs->ARM_pc += correction;
 461
 462        ai_multi += 1;
 463
 464        /* count the number of registers in the mask to be transferred */
 465        nr_regs = hweight16(REGMASK_BITS(instr)) * 4;
 466
 467        rn = RN_BITS(instr);
 468        newaddr = eaddr = regs->uregs[rn];
 469
 470        if (!LDST_U_BIT(instr))
 471                nr_regs = -nr_regs;
 472        newaddr += nr_regs;
 473        if (!LDST_U_BIT(instr))
 474                eaddr = newaddr;
 475
 476        if (LDST_P_EQ_U(instr)) /* U = P */
 477                eaddr += 4;
 478
 479        /*
 480         * For alignment faults on the ARM922T/ARM920T the MMU  makes
 481         * the FSR (and hence addr) equal to the updated base address
 482         * of the multiple access rather than the restored value.
 483         * Switch this message off if we've got a ARM92[02], otherwise
 484         * [ls]dm alignment faults are noisy!
 485         */
 486#if !(defined CONFIG_CPU_ARM922T)  && !(defined CONFIG_CPU_ARM920T)
 487        /*
 488         * This is a "hint" - we already have eaddr worked out by the
 489         * processor for us.
 490         */
 491        if (addr != eaddr) {
 492                printk(KERN_ERR "LDMSTM: PC = %08lx, instr = %08lx, "
 493                        "addr = %08lx, eaddr = %08lx\n",
 494                         instruction_pointer(regs), instr, addr, eaddr);
 495                show_regs(regs);
 496        }
 497#endif
 498
 499        if (user_mode(regs)) {
 500                for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
 501                     regbits >>= 1, rd += 1)
 502                        if (regbits & 1) {
 503                                if (LDST_L_BIT(instr)) {
 504                                        unsigned int val;
 505                                        get32t_unaligned_check(val, eaddr);
 506                                        regs->uregs[rd] = val;
 507                                } else
 508                                        put32t_unaligned_check(regs->uregs[rd], eaddr);
 509                                eaddr += 4;
 510                        }
 511        } else {
 512                for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
 513                     regbits >>= 1, rd += 1)
 514                        if (regbits & 1) {
 515                                if (LDST_L_BIT(instr)) {
 516                                        unsigned int val;
 517                                        get32_unaligned_check(val, eaddr);
 518                                        regs->uregs[rd] = val;
 519                                } else
 520                                        put32_unaligned_check(regs->uregs[rd], eaddr);
 521                                eaddr += 4;
 522                        }
 523        }
 524
 525        if (LDST_W_BIT(instr))
 526                regs->uregs[rn] = newaddr;
 527        if (!LDST_L_BIT(instr) || !(REGMASK_BITS(instr) & (1 << 15)))
 528                regs->ARM_pc -= correction;
 529        return TYPE_DONE;
 530
 531fault:
 532        regs->ARM_pc -= correction;
 533        return TYPE_FAULT;
 534
 535bad:
 536        printk(KERN_ERR "Alignment trap: not handling ldm with s-bit set\n");
 537        return TYPE_ERROR;
 538}
 539
 540/*
 541 * Convert Thumb ld/st instruction forms to equivalent ARM instructions so
 542 * we can reuse ARM userland alignment fault fixups for Thumb.
 543 *
 544 * This implementation was initially based on the algorithm found in
 545 * gdb/sim/arm/thumbemu.c. It is basically just a code reduction of same
 546 * to convert only Thumb ld/st instruction forms to equivalent ARM forms.
 547 *
 548 * NOTES:
 549 * 1. Comments below refer to ARM ARM DDI0100E Thumb Instruction sections.
 550 * 2. If for some reason we're passed an non-ld/st Thumb instruction to
 551 *    decode, we return 0xdeadc0de. This should never happen under normal
 552 *    circumstances but if it does, we've got other problems to deal with
 553 *    elsewhere and we obviously can't fix those problems here.
 554 */
 555
 556static unsigned long
 557thumb2arm(u16 tinstr)
 558{
 559        u32 L = (tinstr & (1<<11)) >> 11;
 560
 561        switch ((tinstr & 0xf800) >> 11) {
 562        /* 6.5.1 Format 1: */
 563        case 0x6000 >> 11:                              /* 7.1.52 STR(1) */
 564        case 0x6800 >> 11:                              /* 7.1.26 LDR(1) */
 565        case 0x7000 >> 11:                              /* 7.1.55 STRB(1) */
 566        case 0x7800 >> 11:                              /* 7.1.30 LDRB(1) */
 567                return 0xe5800000 |
 568                        ((tinstr & (1<<12)) << (22-12)) |       /* fixup */
 569                        (L<<20) |                               /* L==1? */
 570                        ((tinstr & (7<<0)) << (12-0)) |         /* Rd */
 571                        ((tinstr & (7<<3)) << (16-3)) |         /* Rn */
 572                        ((tinstr & (31<<6)) >>                  /* immed_5 */
 573                                (6 - ((tinstr & (1<<12)) ? 0 : 2)));
 574        case 0x8000 >> 11:                              /* 7.1.57 STRH(1) */
 575        case 0x8800 >> 11:                              /* 7.1.32 LDRH(1) */
 576                return 0xe1c000b0 |
 577                        (L<<20) |                               /* L==1? */
 578                        ((tinstr & (7<<0)) << (12-0)) |         /* Rd */
 579                        ((tinstr & (7<<3)) << (16-3)) |         /* Rn */
 580                        ((tinstr & (7<<6)) >> (6-1)) |   /* immed_5[2:0] */
 581                        ((tinstr & (3<<9)) >> (9-8));    /* immed_5[4:3] */
 582
 583        /* 6.5.1 Format 2: */
 584        case 0x5000 >> 11:
 585        case 0x5800 >> 11:
 586                {
 587                        static const u32 subset[8] = {
 588                                0xe7800000,             /* 7.1.53 STR(2) */
 589                                0xe18000b0,             /* 7.1.58 STRH(2) */
 590                                0xe7c00000,             /* 7.1.56 STRB(2) */
 591                                0xe19000d0,             /* 7.1.34 LDRSB */
 592                                0xe7900000,             /* 7.1.27 LDR(2) */
 593                                0xe19000b0,             /* 7.1.33 LDRH(2) */
 594                                0xe7d00000,             /* 7.1.31 LDRB(2) */
 595                                0xe19000f0              /* 7.1.35 LDRSH */
 596                        };
 597                        return subset[(tinstr & (7<<9)) >> 9] |
 598                            ((tinstr & (7<<0)) << (12-0)) |     /* Rd */
 599                            ((tinstr & (7<<3)) << (16-3)) |     /* Rn */
 600                            ((tinstr & (7<<6)) >> (6-0));       /* Rm */
 601                }
 602
 603        /* 6.5.1 Format 3: */
 604        case 0x4800 >> 11:                              /* 7.1.28 LDR(3) */
 605                /* NOTE: This case is not technically possible. We're
 606                 *       loading 32-bit memory data via PC relative
 607                 *       addressing mode. So we can and should eliminate
 608                 *       this case. But I'll leave it here for now.
 609                 */
 610                return 0xe59f0000 |
 611                    ((tinstr & (7<<8)) << (12-8)) |             /* Rd */
 612                    ((tinstr & 255) << (2-0));                  /* immed_8 */
 613
 614        /* 6.5.1 Format 4: */
 615        case 0x9000 >> 11:                              /* 7.1.54 STR(3) */
 616        case 0x9800 >> 11:                              /* 7.1.29 LDR(4) */
 617                return 0xe58d0000 |
 618                        (L<<20) |                               /* L==1? */
 619                        ((tinstr & (7<<8)) << (12-8)) |         /* Rd */
 620                        ((tinstr & 255) << 2);                  /* immed_8 */
 621
 622        /* 6.6.1 Format 1: */
 623        case 0xc000 >> 11:                              /* 7.1.51 STMIA */
 624        case 0xc800 >> 11:                              /* 7.1.25 LDMIA */
 625                {
 626                        u32 Rn = (tinstr & (7<<8)) >> 8;
 627                        u32 W = ((L<<Rn) & (tinstr&255)) ? 0 : 1<<21;
 628
 629                        return 0xe8800000 | W | (L<<20) | (Rn<<16) |
 630                                (tinstr&255);
 631                }
 632
 633        /* 6.6.1 Format 2: */
 634        case 0xb000 >> 11:                              /* 7.1.48 PUSH */
 635        case 0xb800 >> 11:                              /* 7.1.47 POP */
 636                if ((tinstr & (3 << 9)) == 0x0400) {
 637                        static const u32 subset[4] = {
 638                                0xe92d0000,     /* STMDB sp!,{registers} */
 639                                0xe92d4000,     /* STMDB sp!,{registers,lr} */
 640                                0xe8bd0000,     /* LDMIA sp!,{registers} */
 641                                0xe8bd8000      /* LDMIA sp!,{registers,pc} */
 642                        };
 643                        return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] |
 644                            (tinstr & 255);             /* register_list */
 645                }
 646                /* Else fall through for illegal instruction case */
 647
 648        default:
 649                return BAD_INSTR;
 650        }
 651}
 652
 653/*
 654 * Convert Thumb-2 32 bit LDM, STM, LDRD, STRD to equivalent instruction
 655 * handlable by ARM alignment handler, also find the corresponding handler,
 656 * so that we can reuse ARM userland alignment fault fixups for Thumb.
 657 *
 658 * @pinstr: original Thumb-2 instruction; returns new handlable instruction
 659 * @regs: register context.
 660 * @poffset: return offset from faulted addr for later writeback
 661 *
 662 * NOTES:
 663 * 1. Comments below refer to ARMv7 DDI0406A Thumb Instruction sections.
 664 * 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt)
 665 */
 666static void *
 667do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs,
 668                            union offset_union *poffset)
 669{
 670        unsigned long instr = *pinstr;
 671        u16 tinst1 = (instr >> 16) & 0xffff;
 672        u16 tinst2 = instr & 0xffff;
 673        poffset->un = 0;
 674
 675        switch (tinst1 & 0xffe0) {
 676        /* A6.3.5 Load/Store multiple */
 677        case 0xe880:            /* STM/STMIA/STMEA,LDM/LDMIA, PUSH/POP T2 */
 678        case 0xe8a0:            /* ...above writeback version */
 679        case 0xe900:            /* STMDB/STMFD, LDMDB/LDMEA */
 680        case 0xe920:            /* ...above writeback version */
 681                /* no need offset decision since handler calculates it */
 682                return do_alignment_ldmstm;
 683
 684        case 0xf840:            /* POP/PUSH T3 (single register) */
 685                if (RN_BITS(instr) == 13 && (tinst2 & 0x09ff) == 0x0904) {
 686                        u32 L = !!(LDST_L_BIT(instr));
 687                        const u32 subset[2] = {
 688                                0xe92d0000,     /* STMDB sp!,{registers} */
 689                                0xe8bd0000,     /* LDMIA sp!,{registers} */
 690                        };
 691                        *pinstr = subset[L] | (1<<RD_BITS(instr));
 692                        return do_alignment_ldmstm;
 693                }
 694                /* Else fall through for illegal instruction case */
 695                break;
 696
 697        /* A6.3.6 Load/store double, STRD/LDRD(immed, lit, reg) */
 698        case 0xe860:
 699        case 0xe960:
 700        case 0xe8e0:
 701        case 0xe9e0:
 702                poffset->un = (tinst2 & 0xff) << 2;
 703        case 0xe940:
 704        case 0xe9c0:
 705                return do_alignment_ldrdstrd;
 706
 707        /*
 708         * No need to handle load/store instructions up to word size
 709         * since ARMv6 and later CPUs can perform unaligned accesses.
 710         */
 711        default:
 712                break;
 713        }
 714        return NULL;
 715}
 716
 717static int
 718do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 719{
 720        union offset_union offset;
 721        unsigned long instr = 0, instrptr;
 722        int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs);
 723        unsigned int type;
 724        mm_segment_t fs;
 725        unsigned int fault;
 726        u16 tinstr = 0;
 727        int isize = 4;
 728        int thumb2_32b = 0;
 729
 730        instrptr = instruction_pointer(regs);
 731
 732        fs = get_fs();
 733        set_fs(KERNEL_DS);
 734        if (thumb_mode(regs)) {
 735                fault = __get_user(tinstr, (u16 *)(instrptr & ~1));
 736                if (!fault) {
 737                        if (cpu_architecture() >= CPU_ARCH_ARMv7 &&
 738                            IS_T32(tinstr)) {
 739                                /* Thumb-2 32-bit */
 740                                u16 tinst2 = 0;
 741                                fault = __get_user(tinst2, (u16 *)(instrptr+2));
 742                                instr = (tinstr << 16) | tinst2;
 743                                thumb2_32b = 1;
 744                        } else {
 745                                isize = 2;
 746                                instr = thumb2arm(tinstr);
 747                        }
 748                }
 749        } else
 750                fault = __get_user(instr, (u32 *)instrptr);
 751        set_fs(fs);
 752
 753        if (fault) {
 754                type = TYPE_FAULT;
 755                goto bad_or_fault;
 756        }
 757
 758        if (user_mode(regs))
 759                goto user;
 760
 761        ai_sys += 1;
 762
 763 fixup:
 764
 765        regs->ARM_pc += isize;
 766
 767        switch (CODING_BITS(instr)) {
 768        case 0x00000000:        /* 3.13.4 load/store instruction extensions */
 769                if (LDSTHD_I_BIT(instr))
 770                        offset.un = (instr & 0xf00) >> 4 | (instr & 15);
 771                else
 772                        offset.un = regs->uregs[RM_BITS(instr)];
 773
 774                if ((instr & 0x000000f0) == 0x000000b0 || /* LDRH, STRH */
 775                    (instr & 0x001000f0) == 0x001000f0)   /* LDRSH */
 776                        handler = do_alignment_ldrhstrh;
 777                else if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */
 778                         (instr & 0x001000f0) == 0x000000f0)   /* STRD */
 779                        handler = do_alignment_ldrdstrd;
 780                else if ((instr & 0x01f00ff0) == 0x01000090) /* SWP */
 781                        goto swp;
 782                else
 783                        goto bad;
 784                break;
 785
 786        case 0x04000000:        /* ldr or str immediate */
 787                offset.un = OFFSET_BITS(instr);
 788                handler = do_alignment_ldrstr;
 789                break;
 790
 791        case 0x06000000:        /* ldr or str register */
 792                offset.un = regs->uregs[RM_BITS(instr)];
 793
 794                if (IS_SHIFT(instr)) {
 795                        unsigned int shiftval = SHIFT_BITS(instr);
 796
 797                        switch(SHIFT_TYPE(instr)) {
 798                        case SHIFT_LSL:
 799                                offset.un <<= shiftval;
 800                                break;
 801
 802                        case SHIFT_LSR:
 803                                offset.un >>= shiftval;
 804                                break;
 805
 806                        case SHIFT_ASR:
 807                                offset.sn >>= shiftval;
 808                                break;
 809
 810                        case SHIFT_RORRRX:
 811                                if (shiftval == 0) {
 812                                        offset.un >>= 1;
 813                                        if (regs->ARM_cpsr & PSR_C_BIT)
 814                                                offset.un |= 1 << 31;
 815                                } else
 816                                        offset.un = offset.un >> shiftval |
 817                                                          offset.un << (32 - shiftval);
 818                                break;
 819                        }
 820                }
 821                handler = do_alignment_ldrstr;
 822                break;
 823
 824        case 0x08000000:        /* ldm or stm, or thumb-2 32bit instruction */
 825                if (thumb2_32b)
 826                        handler = do_alignment_t32_to_handler(&instr, regs, &offset);
 827                else
 828                        handler = do_alignment_ldmstm;
 829                break;
 830
 831        default:
 832                goto bad;
 833        }
 834
 835        if (!handler)
 836                goto bad;
 837        type = handler(addr, instr, regs);
 838
 839        if (type == TYPE_ERROR || type == TYPE_FAULT) {
 840                regs->ARM_pc -= isize;
 841                goto bad_or_fault;
 842        }
 843
 844        if (type == TYPE_LDST)
 845                do_alignment_finish_ldst(addr, instr, regs, offset);
 846
 847        return 0;
 848
 849 bad_or_fault:
 850        if (type == TYPE_ERROR)
 851                goto bad;
 852        /*
 853         * We got a fault - fix it up, or die.
 854         */
 855        do_bad_area(addr, fsr, regs);
 856        return 0;
 857
 858 swp:
 859        printk(KERN_ERR "Alignment trap: not handling swp instruction\n");
 860
 861 bad:
 862        /*
 863         * Oops, we didn't handle the instruction.
 864         */
 865        printk(KERN_ERR "Alignment trap: not handling instruction "
 866                "%0*lx at [<%08lx>]\n",
 867                isize << 1,
 868                isize == 2 ? tinstr : instr, instrptr);
 869        ai_skipped += 1;
 870        return 1;
 871
 872 user:
 873        ai_user += 1;
 874
 875        if (ai_usermode & UM_WARN)
 876                printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx "
 877                       "Address=0x%08lx FSR 0x%03x\n", current->comm,
 878                        task_pid_nr(current), instrptr,
 879                        isize << 1,
 880                        isize == 2 ? tinstr : instr,
 881                        addr, fsr);
 882
 883        if (ai_usermode & UM_FIXUP)
 884                goto fixup;
 885
 886        if (ai_usermode & UM_SIGNAL)
 887                force_sig(SIGBUS, current);
 888        else {
 889                /*
 890                 * We're about to disable the alignment trap and return to
 891                 * user space.  But if an interrupt occurs before actually
 892                 * reaching user space, then the IRQ vector entry code will
 893                 * notice that we were still in kernel space and therefore
 894                 * the alignment trap won't be re-enabled in that case as it
 895                 * is presumed to be always on from kernel space.
 896                 * Let's prevent that race by disabling interrupts here (they
 897                 * are disabled on the way back to user space anyway in
 898                 * entry-common.S) and disable the alignment trap only if
 899                 * there is no work pending for this thread.
 900                 */
 901                raw_local_irq_disable();
 902                if (!(current_thread_info()->flags & _TIF_WORK_MASK))
 903                        set_cr(cr_no_alignment);
 904        }
 905
 906        return 0;
 907}
 908
 909/*
 910 * This needs to be done after sysctl_init, otherwise sys/ will be
 911 * overwritten.  Actually, this shouldn't be in sys/ at all since
 912 * it isn't a sysctl, and it doesn't contain sysctl information.
 913 * We now locate it in /proc/cpu/alignment instead.
 914 */
 915static int __init alignment_init(void)
 916{
 917#ifdef CONFIG_PROC_FS
 918        struct proc_dir_entry *res;
 919
 920        res = proc_create("cpu/alignment", S_IWUSR | S_IRUGO, NULL,
 921                          &alignment_proc_fops);
 922        if (!res)
 923                return -ENOMEM;
 924#endif
 925
 926        /*
 927         * ARMv6 and later CPUs can perform unaligned accesses for
 928         * most single load and store instructions up to word size.
 929         * LDM, STM, LDRD and STRD still need to be handled.
 930         *
 931         * Ignoring the alignment fault is not an option on these
 932         * CPUs since we spin re-faulting the instruction without
 933         * making any progress.
 934         */
 935        if (cpu_architecture() >= CPU_ARCH_ARMv6 && (cr_alignment & CR_U)) {
 936                cr_alignment &= ~CR_A;
 937                cr_no_alignment &= ~CR_A;
 938                set_cr(cr_alignment);
 939                ai_usermode = UM_FIXUP;
 940        }
 941
 942        hook_fault_code(1, do_alignment, SIGBUS, BUS_ADRALN,
 943                        "alignment exception");
 944
 945        /*
 946         * ARMv6K and ARMv7 use fault status 3 (0b00011) as Access Flag section
 947         * fault, not as alignment error.
 948         *
 949         * TODO: handle ARMv6K properly. Runtime check for 'K' extension is
 950         * needed.
 951         */
 952        if (cpu_architecture() <= CPU_ARCH_ARMv6) {
 953                hook_fault_code(3, do_alignment, SIGBUS, BUS_ADRALN,
 954                                "alignment exception");
 955        }
 956
 957        return 0;
 958}
 959
 960fs_initcall(alignment_init);
 961