LXR linux/arch/arm/plat-mxc/time.c

   1/*
   2 *  linux/arch/arm/plat-mxc/time.c
   3 *
   4 *  Copyright (C) 2000-2001 Deep Blue Solutions
   5 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   6 *  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
   7 *  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License
  11 * as published by the Free Software Foundation; either version 2
  12 * of the License, or (at your option) any later version.
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  21 * MA 02110-1301, USA.
  22 */
  23
  24#include <linux/interrupt.h>
  25#include <linux/irq.h>
  26#include <linux/clockchips.h>
  27#include <linux/clk.h>
  28
  29#include <mach/hardware.h>
  30#include <asm/mach/time.h>
  31#include <mach/common.h>
  32
  33/*
  34 * There are 2 versions of the timer hardware on Freescale MXC hardware.
  35 * Version 1: MX1/MXL, MX21, MX27.
  36 * Version 2: MX25, MX31, MX35, MX37, MX51
  37 */
  38
  39/* defines common for all i.MX */
  40#define MXC_TCTL                0x00
  41#define MXC_TCTL_TEN            (1 << 0) /* Enable module */
  42#define MXC_TPRER               0x04
  43
  44/* MX1, MX21, MX27 */
  45#define MX1_2_TCTL_CLK_PCLK1    (1 << 1)
  46#define MX1_2_TCTL_IRQEN        (1 << 4)
  47#define MX1_2_TCTL_FRR          (1 << 8)
  48#define MX1_2_TCMP              0x08
  49#define MX1_2_TCN               0x10
  50#define MX1_2_TSTAT             0x14
  51
  52/* MX21, MX27 */
  53#define MX2_TSTAT_CAPT          (1 << 1)
  54#define MX2_TSTAT_COMP          (1 << 0)
  55
  56/* MX31, MX35, MX25, MXC91231, MX5 */
  57#define V2_TCTL_WAITEN          (1 << 3) /* Wait enable mode */
  58#define V2_TCTL_CLK_IPG         (1 << 6)
  59#define V2_TCTL_FRR             (1 << 9)
  60#define V2_IR                   0x0c
  61#define V2_TSTAT                0x08
  62#define V2_TSTAT_OF1            (1 << 0)
  63#define V2_TCN                  0x24
  64#define V2_TCMP                 0x10
  65
  66#define timer_is_v1()   (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
  67#define timer_is_v2()   (!timer_is_v1())
  68
  69static struct clock_event_device clockevent_mxc;
  70static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
  71
  72static void __iomem *timer_base;
  73
  74static inline void gpt_irq_disable(void)
  75{
  76        unsigned int tmp;
  77
  78        if (timer_is_v2())
  79                __raw_writel(0, timer_base + V2_IR);
  80        else {
  81                tmp = __raw_readl(timer_base + MXC_TCTL);
  82                __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
  83        }
  84}
  85
  86static inline void gpt_irq_enable(void)
  87{
  88        if (timer_is_v2())
  89                __raw_writel(1<<0, timer_base + V2_IR);
  90        else {
  91                __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
  92                        timer_base + MXC_TCTL);
  93        }
  94}
  95
  96static void gpt_irq_acknowledge(void)
  97{
  98        if (timer_is_v1()) {
  99                if (cpu_is_mx1())
 100                        __raw_writel(0, timer_base + MX1_2_TSTAT);
 101                else
 102                        __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
 103                                timer_base + MX1_2_TSTAT);
 104        } else if (timer_is_v2())
 105                __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
 106}
 107
 108static cycle_t mx1_2_get_cycles(struct clocksource *cs)
 109{
 110        return __raw_readl(timer_base + MX1_2_TCN);
 111}
 112
 113static cycle_t v2_get_cycles(struct clocksource *cs)
 114{
 115        return __raw_readl(timer_base + V2_TCN);
 116}
 117
 118static struct clocksource clocksource_mxc = {
 119        .name           = "mxc_timer1",
 120        .rating         = 200,
 121        .read           = mx1_2_get_cycles,
 122        .mask           = CLOCKSOURCE_MASK(32),
 123        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 124};
 125
 126static int __init mxc_clocksource_init(struct clk *timer_clk)
 127{
 128        unsigned int c = clk_get_rate(timer_clk);
 129
 130        if (timer_is_v2())
 131                clocksource_mxc.read = v2_get_cycles;
 132
 133        clocksource_register_hz(&clocksource_mxc, c);
 134
 135        return 0;
 136}
 137
 138/* clock event */
 139
 140static int mx1_2_set_next_event(unsigned long evt,
 141                              struct clock_event_device *unused)
 142{
 143        unsigned long tcmp;
 144
 145        tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt;
 146
 147        __raw_writel(tcmp, timer_base + MX1_2_TCMP);
 148
 149        return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ?
 150                                -ETIME : 0;
 151}
 152
 153static int v2_set_next_event(unsigned long evt,
 154                              struct clock_event_device *unused)
 155{
 156        unsigned long tcmp;
 157
 158        tcmp = __raw_readl(timer_base + V2_TCN) + evt;
 159
 160        __raw_writel(tcmp, timer_base + V2_TCMP);
 161
 162        return (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
 163                                -ETIME : 0;
 164}
 165
 166#ifdef DEBUG
 167static const char *clock_event_mode_label[] = {
 168        [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
 169        [CLOCK_EVT_MODE_ONESHOT]  = "CLOCK_EVT_MODE_ONESHOT",
 170        [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
 171        [CLOCK_EVT_MODE_UNUSED]   = "CLOCK_EVT_MODE_UNUSED"
 172};
 173#endif /* DEBUG */
 174
 175static void mxc_set_mode(enum clock_event_mode mode,
 176                                struct clock_event_device *evt)
 177{
 178        unsigned long flags;
 179
 180        /*
 181         * The timer interrupt generation is disabled at least
 182         * for enough time to call mxc_set_next_event()
 183         */
 184        local_irq_save(flags);
 185
 186        /* Disable interrupt in GPT module */
 187        gpt_irq_disable();
 188
 189        if (mode != clockevent_mode) {
 190                /* Set event time into far-far future */
 191                if (timer_is_v2())
 192                        __raw_writel(__raw_readl(timer_base + V2_TCN) - 3,
 193                                        timer_base + V2_TCMP);
 194                else
 195                        __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3,
 196                                        timer_base + MX1_2_TCMP);
 197
 198                /* Clear pending interrupt */
 199                gpt_irq_acknowledge();
 200        }
 201
 202#ifdef DEBUG
 203        printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
 204                clock_event_mode_label[clockevent_mode],
 205                clock_event_mode_label[mode]);
 206#endif /* DEBUG */
 207
 208        /* Remember timer mode */
 209        clockevent_mode = mode;
 210        local_irq_restore(flags);
 211
 212        switch (mode) {
 213        case CLOCK_EVT_MODE_PERIODIC:
 214                printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
 215                                "supported for i.MX\n");
 216                break;
 217        case CLOCK_EVT_MODE_ONESHOT:
 218        /*
 219         * Do not put overhead of interrupt enable/disable into
 220         * mxc_set_next_event(), the core has about 4 minutes
 221         * to call mxc_set_next_event() or shutdown clock after
 222         * mode switching
 223         */
 224                local_irq_save(flags);
 225                gpt_irq_enable();
 226                local_irq_restore(flags);
 227                break;
 228        case CLOCK_EVT_MODE_SHUTDOWN:
 229        case CLOCK_EVT_MODE_UNUSED:
 230        case CLOCK_EVT_MODE_RESUME:
 231                /* Left event sources disabled, no more interrupts appear */
 232                break;
 233        }
 234}
 235
 236/*
 237 * IRQ handler for the timer
 238 */
 239static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
 240{
 241        struct clock_event_device *evt = &clockevent_mxc;
 242        uint32_t tstat;
 243
 244        if (timer_is_v2())
 245                tstat = __raw_readl(timer_base + V2_TSTAT);
 246        else
 247                tstat = __raw_readl(timer_base + MX1_2_TSTAT);
 248
 249        gpt_irq_acknowledge();
 250
 251        evt->event_handler(evt);
 252
 253        return IRQ_HANDLED;
 254}
 255
 256static struct irqaction mxc_timer_irq = {
 257        .name           = "i.MX Timer Tick",
 258        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 259        .handler        = mxc_timer_interrupt,
 260};
 261
 262static struct clock_event_device clockevent_mxc = {
 263        .name           = "mxc_timer1",
 264        .features       = CLOCK_EVT_FEAT_ONESHOT,
 265        .shift          = 32,
 266        .set_mode       = mxc_set_mode,
 267        .set_next_event = mx1_2_set_next_event,
 268        .rating         = 200,
 269};
 270
 271static int __init mxc_clockevent_init(struct clk *timer_clk)
 272{
 273        unsigned int c = clk_get_rate(timer_clk);
 274
 275        if (timer_is_v2())
 276                clockevent_mxc.set_next_event = v2_set_next_event;
 277
 278        clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
 279                                        clockevent_mxc.shift);
 280        clockevent_mxc.max_delta_ns =
 281                        clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
 282        clockevent_mxc.min_delta_ns =
 283                        clockevent_delta2ns(0xff, &clockevent_mxc);
 284
 285        clockevent_mxc.cpumask = cpumask_of(0);
 286
 287        clockevents_register_device(&clockevent_mxc);
 288
 289        return 0;
 290}
 291
 292void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
 293{
 294        uint32_t tctl_val;
 295
 296        clk_enable(timer_clk);
 297
 298        timer_base = base;
 299
 300        /*
 301         * Initialise to a known state (all timers off, and timing reset)
 302         */
 303
 304        __raw_writel(0, timer_base + MXC_TCTL);
 305        __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
 306
 307        if (timer_is_v2())
 308                tctl_val = V2_TCTL_CLK_IPG | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
 309        else
 310                tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
 311
 312        __raw_writel(tctl_val, timer_base + MXC_TCTL);
 313
 314        /* init and register the timer to the framework */
 315        mxc_clocksource_init(timer_clk);
 316        mxc_clockevent_init(timer_clk);
 317
 318        /* Make irqs happen */
 319        setup_irq(irq, &mxc_timer_irq);
 320}
 321