1
2
3#ifndef __ASM_ARCH_OMAP_USB_H
4#define __ASM_ARCH_OMAP_USB_H
5
6#include <linux/usb/musb.h>
7#include <plat/board.h>
8
9#define OMAP3_HS_USB_PORTS 3
10enum ehci_hcd_omap_mode {
11 EHCI_HCD_OMAP_MODE_UNKNOWN,
12 EHCI_HCD_OMAP_MODE_PHY,
13 EHCI_HCD_OMAP_MODE_TLL,
14 EHCI_HCD_OMAP_MODE_HSIC,
15};
16
17enum ohci_omap3_port_mode {
18 OMAP_OHCI_PORT_MODE_UNUSED,
19 OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
20 OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
21 OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
22 OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM,
23 OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0,
24 OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM,
25 OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
26 OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
27 OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
28 OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM,
29};
30
31struct ehci_hcd_omap_platform_data {
32 enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS];
33 unsigned phy_reset:1;
34
35
36 int reset_gpio_port[OMAP3_HS_USB_PORTS];
37};
38
39struct ohci_hcd_omap_platform_data {
40 enum ohci_omap3_port_mode port_mode[OMAP3_HS_USB_PORTS];
41
42
43 unsigned es2_compatibility:1;
44};
45
46
47
48#define OMAP1_OTG_BASE 0xfffb0400
49#define OMAP1_UDC_BASE 0xfffb4000
50#define OMAP1_OHCI_BASE 0xfffba000
51
52#define OMAP2_OHCI_BASE 0x4805e000
53#define OMAP2_UDC_BASE 0x4805e200
54#define OMAP2_OTG_BASE 0x4805e300
55
56#ifdef CONFIG_ARCH_OMAP1
57
58#define OTG_BASE OMAP1_OTG_BASE
59#define UDC_BASE OMAP1_UDC_BASE
60#define OMAP_OHCI_BASE OMAP1_OHCI_BASE
61
62#else
63
64#define OTG_BASE OMAP2_OTG_BASE
65#define UDC_BASE OMAP2_UDC_BASE
66#define OMAP_OHCI_BASE OMAP2_OHCI_BASE
67
68struct omap_musb_board_data {
69 u8 interface_type;
70 u8 mode;
71 u16 power;
72 unsigned extvbus:1;
73 void (*set_phy_power)(u8 on);
74 void (*clear_irq)(void);
75 void (*set_mode)(u8 mode);
76 void (*reset)(void);
77};
78
79enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
80
81extern void usb_musb_init(struct omap_musb_board_data *board_data);
82
83extern void usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata);
84
85extern void usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata);
86
87extern int omap4430_phy_power(struct device *dev, int ID, int on);
88extern int omap4430_phy_set_clk(struct device *dev, int on);
89extern int omap4430_phy_init(struct device *dev);
90extern int omap4430_phy_exit(struct device *dev);
91
92#endif
93
94
95
96
97
98
99#ifdef CONFIG_USB_GADGET_OMAP
100#define is_usb0_device(config) 1
101#else
102#define is_usb0_device(config) 0
103#endif
104
105void omap_otg_init(struct omap_usb_config *config);
106
107#if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE)
108void omap1_usb_init(struct omap_usb_config *pdata);
109#else
110static inline void omap1_usb_init(struct omap_usb_config *pdata)
111{
112}
113#endif
114
115#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE)
116void omap2_usbfs_init(struct omap_usb_config *pdata);
117#else
118static inline void omap2_usbfs_init(struct omap_usb_config *pdata)
119{
120}
121#endif
122
123
124
125
126
127
128#define OTG_REV (OTG_BASE + 0x00)
129#define OTG_SYSCON_1 (OTG_BASE + 0x04)
130# define USB2_TRX_MODE(w) (((w)>>24)&0x07)
131# define USB1_TRX_MODE(w) (((w)>>20)&0x07)
132# define USB0_TRX_MODE(w) (((w)>>16)&0x07)
133# define OTG_IDLE_EN (1 << 15)
134# define HST_IDLE_EN (1 << 14)
135# define DEV_IDLE_EN (1 << 13)
136# define OTG_RESET_DONE (1 << 2)
137# define OTG_SOFT_RESET (1 << 1)
138#define OTG_SYSCON_2 (OTG_BASE + 0x08)
139# define OTG_EN (1 << 31)
140# define USBX_SYNCHRO (1 << 30)
141# define OTG_MST16 (1 << 29)
142# define SRP_GPDATA (1 << 28)
143# define SRP_GPDVBUS (1 << 27)
144# define SRP_GPUVBUS(w) (((w)>>24)&0x07)
145# define A_WAIT_VRISE(w) (((w)>>20)&0x07)
146# define B_ASE_BRST(w) (((w)>>16)&0x07)
147# define SRP_DPW (1 << 14)
148# define SRP_DATA (1 << 13)
149# define SRP_VBUS (1 << 12)
150# define OTG_PADEN (1 << 10)
151# define HMC_PADEN (1 << 9)
152# define UHOST_EN (1 << 8)
153# define HMC_TLLSPEED (1 << 7)
154# define HMC_TLLATTACH (1 << 6)
155# define OTG_HMC(w) (((w)>>0)&0x3f)
156#define OTG_CTRL (OTG_BASE + 0x0c)
157# define OTG_USB2_EN (1 << 29)
158# define OTG_USB2_DP (1 << 28)
159# define OTG_USB2_DM (1 << 27)
160# define OTG_USB1_EN (1 << 26)
161# define OTG_USB1_DP (1 << 25)
162# define OTG_USB1_DM (1 << 24)
163# define OTG_USB0_EN (1 << 23)
164# define OTG_USB0_DP (1 << 22)
165# define OTG_USB0_DM (1 << 21)
166# define OTG_ASESSVLD (1 << 20)
167# define OTG_BSESSEND (1 << 19)
168# define OTG_BSESSVLD (1 << 18)
169# define OTG_VBUSVLD (1 << 17)
170# define OTG_ID (1 << 16)
171# define OTG_DRIVER_SEL (1 << 15)
172# define OTG_A_SETB_HNPEN (1 << 12)
173# define OTG_A_BUSREQ (1 << 11)
174# define OTG_B_HNPEN (1 << 9)
175# define OTG_B_BUSREQ (1 << 8)
176# define OTG_BUSDROP (1 << 7)
177# define OTG_PULLDOWN (1 << 5)
178# define OTG_PULLUP (1 << 4)
179# define OTG_DRV_VBUS (1 << 3)
180# define OTG_PD_VBUS (1 << 2)
181# define OTG_PU_VBUS (1 << 1)
182# define OTG_PU_ID (1 << 0)
183#define OTG_IRQ_EN (OTG_BASE + 0x10)
184# define DRIVER_SWITCH (1 << 15)
185# define A_VBUS_ERR (1 << 13)
186# define A_REQ_TMROUT (1 << 12)
187# define A_SRP_DETECT (1 << 11)
188# define B_HNP_FAIL (1 << 10)
189# define B_SRP_TMROUT (1 << 9)
190# define B_SRP_DONE (1 << 8)
191# define B_SRP_STARTED (1 << 7)
192# define OPRT_CHG (1 << 0)
193#define OTG_IRQ_SRC (OTG_BASE + 0x14)
194
195#define OTG_OUTCTRL (OTG_BASE + 0x18)
196# define OTGVPD (1 << 14)
197# define OTGVPU (1 << 13)
198# define OTGPUID (1 << 12)
199# define USB2VDR (1 << 10)
200# define USB2PDEN (1 << 9)
201# define USB2PUEN (1 << 8)
202# define USB1VDR (1 << 6)
203# define USB1PDEN (1 << 5)
204# define USB1PUEN (1 << 4)
205# define USB0VDR (1 << 2)
206# define USB0PDEN (1 << 1)
207# define USB0PUEN (1 << 0)
208#define OTG_TEST (OTG_BASE + 0x20)
209#define OTG_VENDOR_CODE (OTG_BASE + 0xfc)
210
211
212
213
214#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064)
215# define CONF_USB2_UNI_R (1 << 8)
216# define CONF_USB1_UNI_R (1 << 7)
217# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
218# define CONF_USB0_ISOLATE_R (1 << 3)
219# define CONF_USB_PWRDN_DM_R (1 << 2)
220# define CONF_USB_PWRDN_DP_R (1 << 1)
221
222
223# define USB_UNIDIR 0x0
224# define USB_UNIDIR_TLL 0x1
225# define USB_BIDIR 0x2
226# define USB_BIDIR_TLL 0x3
227# define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2)))
228# define USBT2TLL5PI (1 << 17)
229# define USB0PUENACTLOI (1 << 16)
230# define USBSTANDBYCTRL (1 << 15)
231
232
233#define CONF2_PHY_GPIOMODE (1 << 23)
234#define CONF2_OTGMODE (3 << 14)
235#define CONF2_NO_OVERRIDE (0 << 14)
236#define CONF2_FORCE_HOST (1 << 14)
237#define CONF2_FORCE_DEVICE (2 << 14)
238#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
239#define CONF2_SESENDEN (1 << 13)
240#define CONF2_VBDTCTEN (1 << 12)
241#define CONF2_REFFREQ_24MHZ (2 << 8)
242#define CONF2_REFFREQ_26MHZ (7 << 8)
243#define CONF2_REFFREQ_13MHZ (6 << 8)
244#define CONF2_REFFREQ (0xf << 8)
245#define CONF2_PHYCLKGD (1 << 7)
246#define CONF2_VBUSSENSE (1 << 6)
247#define CONF2_PHY_PLLON (1 << 5)
248#define CONF2_RESET (1 << 4)
249#define CONF2_PHYPWRDN (1 << 3)
250#define CONF2_OTGPWRDN (1 << 2)
251#define CONF2_DATPOL (1 << 1)
252
253#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
254u32 omap1_usb0_init(unsigned nwires, unsigned is_device);
255u32 omap1_usb1_init(unsigned nwires);
256u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup);
257#else
258static inline u32 omap1_usb0_init(unsigned nwires, unsigned is_device)
259{
260 return 0;
261}
262static inline u32 omap1_usb1_init(unsigned nwires)
263{
264 return 0;
265
266}
267static inline u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
268{
269 return 0;
270}
271#endif
272
273#endif
274
