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9#include <linux/kernel.h>
10#include <linux/hardirq.h>
11#include <linux/thread_info.h>
12#include <linux/mm.h>
13#include <linux/uaccess.h>
14#include <linux/module.h>
15#include <linux/kallsyms.h>
16#include <linux/err.h>
17#include <linux/fs.h>
18#include <linux/irq.h>
19#include <asm/dma.h>
20#include <asm/trace.h>
21#include <asm/fixed_code.h>
22#include <asm/traps.h>
23#include <asm/irq_handler.h>
24
25void decode_address(char *buf, unsigned long address)
26{
27 struct task_struct *p;
28 struct mm_struct *mm;
29 unsigned long flags, offset;
30 unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic();
31 struct rb_node *n;
32
33#ifdef CONFIG_KALLSYMS
34 unsigned long symsize;
35 const char *symname;
36 char *modname;
37 char *delim = ":";
38 char namebuf[128];
39#endif
40
41 buf += sprintf(buf, "<0x%08lx> ", address);
42
43#ifdef CONFIG_KALLSYMS
44
45 symname = kallsyms_lookup(address, &symsize, &offset, &modname, namebuf);
46
47 if (symname) {
48
49 if (!modname)
50 modname = delim = "";
51 sprintf(buf, "{ %s%s%s%s + 0x%lx }",
52 delim, modname, delim, symname,
53 (unsigned long)offset);
54 return;
55 }
56#endif
57
58 if (address >= FIXED_CODE_START && address < FIXED_CODE_END) {
59
60 strcat(buf, "/* Maybe fixed code section */");
61 return;
62
63 } else if (address < CONFIG_BOOT_LOAD) {
64
65 strcat(buf, "/* Maybe null pointer? */");
66 return;
67
68 } else if (address >= COREMMR_BASE) {
69 strcat(buf, "/* core mmrs */");
70 return;
71
72 } else if (address >= SYSMMR_BASE) {
73 strcat(buf, "/* system mmrs */");
74 return;
75
76 } else if (address >= L1_ROM_START && address < L1_ROM_START + L1_ROM_LENGTH) {
77 strcat(buf, "/* on-chip L1 ROM */");
78 return;
79
80 } else if (address >= L1_SCRATCH_START && address < L1_SCRATCH_START + L1_SCRATCH_LENGTH) {
81 strcat(buf, "/* on-chip scratchpad */");
82 return;
83
84 } else if (address >= physical_mem_end && address < ASYNC_BANK0_BASE) {
85 strcat(buf, "/* unconnected memory */");
86 return;
87
88 } else if (address >= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE && address < BOOT_ROM_START) {
89 strcat(buf, "/* reserved memory */");
90 return;
91
92 } else if (address >= L1_DATA_A_START && address < L1_DATA_A_START + L1_DATA_A_LENGTH) {
93 strcat(buf, "/* on-chip Data Bank A */");
94 return;
95
96 } else if (address >= L1_DATA_B_START && address < L1_DATA_B_START + L1_DATA_B_LENGTH) {
97 strcat(buf, "/* on-chip Data Bank B */");
98 return;
99 }
100
101
102
103
104
105 if (oops_in_progress) {
106 strcat(buf, "/* kernel dynamic memory (maybe user-space) */");
107 return;
108 }
109
110
111
112
113
114 write_lock_irqsave(&tasklist_lock, flags);
115 for_each_process(p) {
116 mm = (in_atomic ? p->mm : get_task_mm(p));
117 if (!mm)
118 continue;
119
120 if (!down_read_trylock(&mm->mmap_sem)) {
121 if (!in_atomic)
122 mmput(mm);
123 continue;
124 }
125
126 for (n = rb_first(&mm->mm_rb); n; n = rb_next(n)) {
127 struct vm_area_struct *vma;
128
129 vma = rb_entry(n, struct vm_area_struct, vm_rb);
130
131 if (address >= vma->vm_start && address < vma->vm_end) {
132 char _tmpbuf[256];
133 char *name = p->comm;
134 struct file *file = vma->vm_file;
135
136 if (file) {
137 char *d_name = d_path(&file->f_path, _tmpbuf,
138 sizeof(_tmpbuf));
139 if (!IS_ERR(d_name))
140 name = d_name;
141 }
142
143
144
145
146
147
148
149
150 if ((unsigned long)current >= FIXED_CODE_START &&
151 !((unsigned long)current & 0x3)) {
152 if (current->mm &&
153 (address > current->mm->start_code) &&
154 (address < current->mm->end_code))
155 offset = address - current->mm->start_code;
156 else
157 offset = (address - vma->vm_start) +
158 (vma->vm_pgoff << PAGE_SHIFT);
159
160 sprintf(buf, "[ %s + 0x%lx ]", name, offset);
161 } else
162 sprintf(buf, "[ %s vma:0x%lx-0x%lx]",
163 name, vma->vm_start, vma->vm_end);
164
165 up_read(&mm->mmap_sem);
166 if (!in_atomic)
167 mmput(mm);
168
169 if (buf[0] == '\0')
170 sprintf(buf, "[ %s ] dynamic memory", name);
171
172 goto done;
173 }
174 }
175
176 up_read(&mm->mmap_sem);
177 if (!in_atomic)
178 mmput(mm);
179 }
180
181
182
183
184
185 sprintf(buf, "/* kernel dynamic memory */");
186
187done:
188 write_unlock_irqrestore(&tasklist_lock, flags);
189}
190
191#define EXPAND_LEN ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 256 - 1)
192
193
194
195
196
197bool get_mem16(unsigned short *val, unsigned short *address)
198{
199 unsigned long addr = (unsigned long)address;
200
201
202 if (addr & 0x1)
203 return false;
204
205 switch (bfin_mem_access_type(addr, 2)) {
206 case BFIN_MEM_ACCESS_CORE:
207 case BFIN_MEM_ACCESS_CORE_ONLY:
208 *val = *address;
209 return true;
210 case BFIN_MEM_ACCESS_DMA:
211 dma_memcpy(val, address, 2);
212 return true;
213 case BFIN_MEM_ACCESS_ITEST:
214 isram_memcpy(val, address, 2);
215 return true;
216 default:
217 return false;
218 }
219}
220
221bool get_instruction(unsigned int *val, unsigned short *address)
222{
223 unsigned long addr = (unsigned long)address;
224 unsigned short opcode0, opcode1;
225
226
227 if (addr & 0x1)
228 return false;
229
230
231 if (addr >= SYSMMR_BASE)
232 return false;
233
234
235 if (addr >= L1_SCRATCH_START && addr < L1_SCRATCH_START + L1_SCRATCH_LENGTH)
236 return false;
237
238
239 if (addr >= BOOT_ROM_START + BOOT_ROM_LENGTH && addr < L1_CODE_START)
240 return false;
241
242 if (!get_mem16(&opcode0, address))
243 return false;
244
245
246 if ((opcode0 & 0xc000) == 0xc000) {
247 if (!get_mem16(&opcode1, address + 1))
248 return false;
249 *val = (opcode0 << 16) + opcode1;
250 } else
251 *val = opcode0;
252
253 return true;
254}
255
256#if defined(CONFIG_DEBUG_BFIN_HWTRACE_ON)
257
258
259
260
261
262
263
264
265#define ProgCtrl_opcode 0x0000
266#define ProgCtrl_poprnd_bits 0
267#define ProgCtrl_poprnd_mask 0xf
268#define ProgCtrl_prgfunc_bits 4
269#define ProgCtrl_prgfunc_mask 0xf
270#define ProgCtrl_code_bits 8
271#define ProgCtrl_code_mask 0xff
272
273static void decode_ProgCtrl_0(unsigned int opcode)
274{
275 int poprnd = ((opcode >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
276 int prgfunc = ((opcode >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
277
278 if (prgfunc == 0 && poprnd == 0)
279 pr_cont("NOP");
280 else if (prgfunc == 1 && poprnd == 0)
281 pr_cont("RTS");
282 else if (prgfunc == 1 && poprnd == 1)
283 pr_cont("RTI");
284 else if (prgfunc == 1 && poprnd == 2)
285 pr_cont("RTX");
286 else if (prgfunc == 1 && poprnd == 3)
287 pr_cont("RTN");
288 else if (prgfunc == 1 && poprnd == 4)
289 pr_cont("RTE");
290 else if (prgfunc == 2 && poprnd == 0)
291 pr_cont("IDLE");
292 else if (prgfunc == 2 && poprnd == 3)
293 pr_cont("CSYNC");
294 else if (prgfunc == 2 && poprnd == 4)
295 pr_cont("SSYNC");
296 else if (prgfunc == 2 && poprnd == 5)
297 pr_cont("EMUEXCPT");
298 else if (prgfunc == 3)
299 pr_cont("CLI R%i", poprnd);
300 else if (prgfunc == 4)
301 pr_cont("STI R%i", poprnd);
302 else if (prgfunc == 5)
303 pr_cont("JUMP (P%i)", poprnd);
304 else if (prgfunc == 6)
305 pr_cont("CALL (P%i)", poprnd);
306 else if (prgfunc == 7)
307 pr_cont("CALL (PC + P%i)", poprnd);
308 else if (prgfunc == 8)
309 pr_cont("JUMP (PC + P%i", poprnd);
310 else if (prgfunc == 9)
311 pr_cont("RAISE %i", poprnd);
312 else if (prgfunc == 10)
313 pr_cont("EXCPT %i", poprnd);
314 else
315 pr_cont("0x%04x", opcode);
316
317}
318
319#define BRCC_opcode 0x1000
320#define BRCC_offset_bits 0
321#define BRCC_offset_mask 0x3ff
322#define BRCC_B_bits 10
323#define BRCC_B_mask 0x1
324#define BRCC_T_bits 11
325#define BRCC_T_mask 0x1
326#define BRCC_code_bits 12
327#define BRCC_code_mask 0xf
328
329static void decode_BRCC_0(unsigned int opcode)
330{
331 int B = ((opcode >> BRCC_B_bits) & BRCC_B_mask);
332 int T = ((opcode >> BRCC_T_bits) & BRCC_T_mask);
333
334 pr_cont("IF %sCC JUMP pcrel %s", T ? "" : "!", B ? "(BP)" : "");
335}
336
337#define CALLa_opcode 0xe2000000
338#define CALLa_addr_bits 0
339#define CALLa_addr_mask 0xffffff
340#define CALLa_S_bits 24
341#define CALLa_S_mask 0x1
342#define CALLa_code_bits 25
343#define CALLa_code_mask 0x7f
344
345static void decode_CALLa_0(unsigned int opcode)
346{
347 int S = ((opcode >> (CALLa_S_bits - 16)) & CALLa_S_mask);
348
349 if (S)
350 pr_cont("CALL pcrel");
351 else
352 pr_cont("JUMP.L");
353}
354
355#define LoopSetup_opcode 0xe0800000
356#define LoopSetup_eoffset_bits 0
357#define LoopSetup_eoffset_mask 0x3ff
358#define LoopSetup_dontcare_bits 10
359#define LoopSetup_dontcare_mask 0x3
360#define LoopSetup_reg_bits 12
361#define LoopSetup_reg_mask 0xf
362#define LoopSetup_soffset_bits 16
363#define LoopSetup_soffset_mask 0xf
364#define LoopSetup_c_bits 20
365#define LoopSetup_c_mask 0x1
366#define LoopSetup_rop_bits 21
367#define LoopSetup_rop_mask 0x3
368#define LoopSetup_code_bits 23
369#define LoopSetup_code_mask 0x1ff
370
371static void decode_LoopSetup_0(unsigned int opcode)
372{
373 int c = ((opcode >> LoopSetup_c_bits) & LoopSetup_c_mask);
374 int reg = ((opcode >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
375 int rop = ((opcode >> LoopSetup_rop_bits) & LoopSetup_rop_mask);
376
377 pr_cont("LSETUP <> LC%i", c);
378 if ((rop & 1) == 1)
379 pr_cont("= P%i", reg);
380 if ((rop & 2) == 2)
381 pr_cont(" >> 0x1");
382}
383
384#define DspLDST_opcode 0x9c00
385#define DspLDST_reg_bits 0
386#define DspLDST_reg_mask 0x7
387#define DspLDST_i_bits 3
388#define DspLDST_i_mask 0x3
389#define DspLDST_m_bits 5
390#define DspLDST_m_mask 0x3
391#define DspLDST_aop_bits 7
392#define DspLDST_aop_mask 0x3
393#define DspLDST_W_bits 9
394#define DspLDST_W_mask 0x1
395#define DspLDST_code_bits 10
396#define DspLDST_code_mask 0x3f
397
398static void decode_dspLDST_0(unsigned int opcode)
399{
400 int i = ((opcode >> DspLDST_i_bits) & DspLDST_i_mask);
401 int m = ((opcode >> DspLDST_m_bits) & DspLDST_m_mask);
402 int W = ((opcode >> DspLDST_W_bits) & DspLDST_W_mask);
403 int aop = ((opcode >> DspLDST_aop_bits) & DspLDST_aop_mask);
404 int reg = ((opcode >> DspLDST_reg_bits) & DspLDST_reg_mask);
405
406 if (W == 0) {
407 pr_cont("R%i", reg);
408 switch (m) {
409 case 0:
410 pr_cont(" = ");
411 break;
412 case 1:
413 pr_cont(".L = ");
414 break;
415 case 2:
416 pr_cont(".W = ");
417 break;
418 }
419 }
420
421 pr_cont("[ I%i", i);
422
423 switch (aop) {
424 case 0:
425 pr_cont("++ ]");
426 break;
427 case 1:
428 pr_cont("-- ]");
429 break;
430 }
431
432 if (W == 1) {
433 pr_cont(" = R%i", reg);
434 switch (m) {
435 case 1:
436 pr_cont(".L = ");
437 break;
438 case 2:
439 pr_cont(".W = ");
440 break;
441 }
442 }
443}
444
445#define LDST_opcode 0x9000
446#define LDST_reg_bits 0
447#define LDST_reg_mask 0x7
448#define LDST_ptr_bits 3
449#define LDST_ptr_mask 0x7
450#define LDST_Z_bits 6
451#define LDST_Z_mask 0x1
452#define LDST_aop_bits 7
453#define LDST_aop_mask 0x3
454#define LDST_W_bits 9
455#define LDST_W_mask 0x1
456#define LDST_sz_bits 10
457#define LDST_sz_mask 0x3
458#define LDST_code_bits 12
459#define LDST_code_mask 0xf
460
461static void decode_LDST_0(unsigned int opcode)
462{
463 int Z = ((opcode >> LDST_Z_bits) & LDST_Z_mask);
464 int W = ((opcode >> LDST_W_bits) & LDST_W_mask);
465 int sz = ((opcode >> LDST_sz_bits) & LDST_sz_mask);
466 int aop = ((opcode >> LDST_aop_bits) & LDST_aop_mask);
467 int reg = ((opcode >> LDST_reg_bits) & LDST_reg_mask);
468 int ptr = ((opcode >> LDST_ptr_bits) & LDST_ptr_mask);
469
470 if (W == 0)
471 pr_cont("%s%i = ", (sz == 0 && Z == 1) ? "P" : "R", reg);
472
473 switch (sz) {
474 case 1:
475 pr_cont("W");
476 break;
477 case 2:
478 pr_cont("B");
479 break;
480 }
481
482 pr_cont("[P%i", ptr);
483
484 switch (aop) {
485 case 0:
486 pr_cont("++");
487 break;
488 case 1:
489 pr_cont("--");
490 break;
491 }
492 pr_cont("]");
493
494 if (W == 1)
495 pr_cont(" = %s%i ", (sz == 0 && Z == 1) ? "P" : "R", reg);
496
497 if (sz) {
498 if (Z)
499 pr_cont(" (X)");
500 else
501 pr_cont(" (Z)");
502 }
503}
504
505#define LDSTii_opcode 0xa000
506#define LDSTii_reg_bit 0
507#define LDSTii_reg_mask 0x7
508#define LDSTii_ptr_bit 3
509#define LDSTii_ptr_mask 0x7
510#define LDSTii_offset_bit 6
511#define LDSTii_offset_mask 0xf
512#define LDSTii_op_bit 10
513#define LDSTii_op_mask 0x3
514#define LDSTii_W_bit 12
515#define LDSTii_W_mask 0x1
516#define LDSTii_code_bit 13
517#define LDSTii_code_mask 0x7
518
519static void decode_LDSTii_0(unsigned int opcode)
520{
521 int reg = ((opcode >> LDSTii_reg_bit) & LDSTii_reg_mask);
522 int ptr = ((opcode >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
523 int offset = ((opcode >> LDSTii_offset_bit) & LDSTii_offset_mask);
524 int op = ((opcode >> LDSTii_op_bit) & LDSTii_op_mask);
525 int W = ((opcode >> LDSTii_W_bit) & LDSTii_W_mask);
526
527 if (W == 0) {
528 pr_cont("%s%i = %s[P%i + %i]", op == 3 ? "R" : "P", reg,
529 op == 1 || op == 2 ? "" : "W", ptr, offset);
530 if (op == 2)
531 pr_cont("(Z)");
532 if (op == 3)
533 pr_cont("(X)");
534 } else {
535 pr_cont("%s[P%i + %i] = %s%i", op == 0 ? "" : "W", ptr,
536 offset, op == 3 ? "P" : "R", reg);
537 }
538}
539
540#define LDSTidxI_opcode 0xe4000000
541#define LDSTidxI_offset_bits 0
542#define LDSTidxI_offset_mask 0xffff
543#define LDSTidxI_reg_bits 16
544#define LDSTidxI_reg_mask 0x7
545#define LDSTidxI_ptr_bits 19
546#define LDSTidxI_ptr_mask 0x7
547#define LDSTidxI_sz_bits 22
548#define LDSTidxI_sz_mask 0x3
549#define LDSTidxI_Z_bits 24
550#define LDSTidxI_Z_mask 0x1
551#define LDSTidxI_W_bits 25
552#define LDSTidxI_W_mask 0x1
553#define LDSTidxI_code_bits 26
554#define LDSTidxI_code_mask 0x3f
555
556static void decode_LDSTidxI_0(unsigned int opcode)
557{
558 int Z = ((opcode >> LDSTidxI_Z_bits) & LDSTidxI_Z_mask);
559 int W = ((opcode >> LDSTidxI_W_bits) & LDSTidxI_W_mask);
560 int sz = ((opcode >> LDSTidxI_sz_bits) & LDSTidxI_sz_mask);
561 int reg = ((opcode >> LDSTidxI_reg_bits) & LDSTidxI_reg_mask);
562 int ptr = ((opcode >> LDSTidxI_ptr_bits) & LDSTidxI_ptr_mask);
563 int offset = ((opcode >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
564
565 if (W == 0)
566 pr_cont("%s%i = ", sz == 0 && Z == 1 ? "P" : "R", reg);
567
568 if (sz == 1)
569 pr_cont("W");
570 if (sz == 2)
571 pr_cont("B");
572
573 pr_cont("[P%i + %s0x%x]", ptr, offset & 0x20 ? "-" : "",
574 (offset & 0x1f) << 2);
575
576 if (W == 0 && sz != 0) {
577 if (Z)
578 pr_cont("(X)");
579 else
580 pr_cont("(Z)");
581 }
582
583 if (W == 1)
584 pr_cont("= %s%i", (sz == 0 && Z == 1) ? "P" : "R", reg);
585
586}
587
588static void decode_opcode(unsigned int opcode)
589{
590#ifdef CONFIG_BUG
591 if (opcode == BFIN_BUG_OPCODE)
592 pr_cont("BUG");
593 else
594#endif
595 if ((opcode & 0xffffff00) == ProgCtrl_opcode)
596 decode_ProgCtrl_0(opcode);
597 else if ((opcode & 0xfffff000) == BRCC_opcode)
598 decode_BRCC_0(opcode);
599 else if ((opcode & 0xfffff000) == 0x2000)
600 pr_cont("JUMP.S");
601 else if ((opcode & 0xfe000000) == CALLa_opcode)
602 decode_CALLa_0(opcode);
603 else if ((opcode & 0xff8000C0) == LoopSetup_opcode)
604 decode_LoopSetup_0(opcode);
605 else if ((opcode & 0xfffffc00) == DspLDST_opcode)
606 decode_dspLDST_0(opcode);
607 else if ((opcode & 0xfffff000) == LDST_opcode)
608 decode_LDST_0(opcode);
609 else if ((opcode & 0xffffe000) == LDSTii_opcode)
610 decode_LDSTii_0(opcode);
611 else if ((opcode & 0xfc000000) == LDSTidxI_opcode)
612 decode_LDSTidxI_0(opcode);
613 else if (opcode & 0xffff0000)
614 pr_cont("0x%08x", opcode);
615 else
616 pr_cont("0x%04x", opcode);
617}
618
619#define BIT_MULTI_INS 0x08000000
620static void decode_instruction(unsigned short *address)
621{
622 unsigned int opcode;
623
624 if (!get_instruction(&opcode, address))
625 return;
626
627 decode_opcode(opcode);
628
629
630
631
632
633 if ((opcode & 0xc0000000) == 0xc0000000 &&
634 (opcode & BIT_MULTI_INS) &&
635 (opcode & 0xe8000000) != 0xe8000000) {
636 pr_cont(" || ");
637 if (!get_instruction(&opcode, address + 2))
638 return;
639 decode_opcode(opcode);
640 pr_cont(" || ");
641 if (!get_instruction(&opcode, address + 3))
642 return;
643 decode_opcode(opcode);
644 }
645}
646#endif
647
648void dump_bfin_trace_buffer(void)
649{
650#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
651 int tflags, i = 0, fault = 0;
652 char buf[150];
653 unsigned short *addr;
654 unsigned int cpu = raw_smp_processor_id();
655#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
656 int j, index;
657#endif
658
659 trace_buffer_save(tflags);
660
661 pr_notice("Hardware Trace:\n");
662
663#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
664 pr_notice("WARNING: Expanded trace turned on - can not trace exceptions\n");
665#endif
666
667 if (likely(bfin_read_TBUFSTAT() & TBUFCNT)) {
668 for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) {
669 addr = (unsigned short *)bfin_read_TBUF();
670 decode_address(buf, (unsigned long)addr);
671 pr_notice("%4i Target : %s\n", i, buf);
672
673
674
675
676 if (!fault && addr == ((unsigned short *)evt_ivhw)) {
677 addr = (unsigned short *)bfin_read_TBUF();
678 decode_address(buf, (unsigned long)addr);
679 pr_notice(" FAULT : %s ", buf);
680 decode_instruction(addr);
681 pr_cont("\n");
682 fault = 1;
683 continue;
684 }
685 if (!fault && addr == (unsigned short *)trap &&
686 (cpu_pda[cpu].seqstat & SEQSTAT_EXCAUSE) > VEC_EXCPT15) {
687 decode_address(buf, cpu_pda[cpu].icplb_fault_addr);
688 pr_notice(" FAULT : %s ", buf);
689 decode_instruction((unsigned short *)cpu_pda[cpu].icplb_fault_addr);
690 pr_cont("\n");
691 fault = 1;
692 }
693 addr = (unsigned short *)bfin_read_TBUF();
694 decode_address(buf, (unsigned long)addr);
695 pr_notice(" Source : %s ", buf);
696 decode_instruction(addr);
697 pr_cont("\n");
698 }
699 }
700
701#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
702 if (trace_buff_offset)
703 index = trace_buff_offset / 4;
704 else
705 index = EXPAND_LEN;
706
707 j = (1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 128;
708 while (j) {
709 decode_address(buf, software_trace_buff[index]);
710 pr_notice("%4i Target : %s\n", i, buf);
711 index -= 1;
712 if (index < 0)
713 index = EXPAND_LEN;
714 decode_address(buf, software_trace_buff[index]);
715 pr_notice(" Source : %s ", buf);
716 decode_instruction((unsigned short *)software_trace_buff[index]);
717 pr_cont("\n");
718 index -= 1;
719 if (index < 0)
720 index = EXPAND_LEN;
721 j--;
722 i++;
723 }
724#endif
725
726 trace_buffer_restore(tflags);
727#endif
728}
729EXPORT_SYMBOL(dump_bfin_trace_buffer);
730
731void dump_bfin_process(struct pt_regs *fp)
732{
733
734
735 unsigned int context = bfin_read_IPEND();
736
737 if (oops_in_progress)
738 pr_emerg("Kernel OOPS in progress\n");
739
740 if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR)
741 pr_notice("HW Error context\n");
742 else if (context & 0x0020)
743 pr_notice("Deferred Exception context\n");
744 else if (context & 0x3FC0)
745 pr_notice("Interrupt context\n");
746 else if (context & 0x4000)
747 pr_notice("Deferred Interrupt context\n");
748 else if (context & 0x8000)
749 pr_notice("Kernel process context\n");
750
751
752
753
754 if ((unsigned long)current >= FIXED_CODE_START &&
755 !((unsigned long)current & 0x3) && current->pid) {
756 pr_notice("CURRENT PROCESS:\n");
757 if (current->comm >= (char *)FIXED_CODE_START)
758 pr_notice("COMM=%s PID=%d",
759 current->comm, current->pid);
760 else
761 pr_notice("COMM= invalid");
762
763 pr_cont(" CPU=%d\n", current_thread_info()->cpu);
764 if (!((unsigned long)current->mm & 0x3) &&
765 (unsigned long)current->mm >= FIXED_CODE_START) {
766 pr_notice("TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n",
767 (void *)current->mm->start_code,
768 (void *)current->mm->end_code,
769 (void *)current->mm->start_data,
770 (void *)current->mm->end_data);
771 pr_notice(" BSS = 0x%p-0x%p USER-STACK = 0x%p\n\n",
772 (void *)current->mm->end_data,
773 (void *)current->mm->brk,
774 (void *)current->mm->start_stack);
775 } else
776 pr_notice("invalid mm\n");
777 } else
778 pr_notice("No Valid process in current context\n");
779}
780
781void dump_bfin_mem(struct pt_regs *fp)
782{
783 unsigned short *addr, *erraddr, val = 0, err = 0;
784 char sti = 0, buf[6];
785
786 erraddr = (void *)fp->pc;
787
788 pr_notice("return address: [0x%p]; contents of:", erraddr);
789
790 for (addr = (unsigned short *)((unsigned long)erraddr & ~0xF) - 0x10;
791 addr < (unsigned short *)((unsigned long)erraddr & ~0xF) + 0x10;
792 addr++) {
793 if (!((unsigned long)addr & 0xF))
794 pr_notice("0x%p: ", addr);
795
796 if (!get_mem16(&val, addr)) {
797 val = 0;
798 sprintf(buf, "????");
799 } else
800 sprintf(buf, "%04x", val);
801
802 if (addr == erraddr) {
803 pr_cont("[%s]", buf);
804 err = val;
805 } else
806 pr_cont(" %s ", buf);
807
808
809 if (addr <= erraddr &&
810 ((val >= 0x0040 && val <= 0x0047) ||
811 val == 0x017b))
812 sti = 1;
813 }
814
815 pr_cont("\n");
816
817
818 if (unlikely(sti && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR &&
819 oops_in_progress)){
820 pr_notice("Looks like this was a deferred error - sorry\n");
821#ifndef CONFIG_DEBUG_HWERR
822 pr_notice("The remaining message may be meaningless\n");
823 pr_notice("You should enable CONFIG_DEBUG_HWERR to get a better idea where it came from\n");
824#else
825
826
827
828
829
830 if ((!(((fp)->ipend & ~0x30) & (((fp)->ipend & ~0x30) - 1))) &&
831 (current->pid && current->mm)) {
832
833 if ((fp + 1)->pc >= current->mm->start_code &&
834 (fp + 1)->pc <= current->mm->end_code) {
835 pr_notice("It might be better to look around here :\n");
836 pr_notice("-------------------------------------------\n");
837 show_regs(fp + 1);
838 pr_notice("-------------------------------------------\n");
839 }
840 }
841#endif
842 }
843}
844
845void show_regs(struct pt_regs *fp)
846{
847 char buf[150];
848 struct irqaction *action;
849 unsigned int i;
850 unsigned long flags = 0;
851 unsigned int cpu = raw_smp_processor_id();
852 unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic();
853
854 pr_notice("\n");
855 if (CPUID != bfin_cpuid())
856 pr_notice("Compiled for cpu family 0x%04x (Rev %d), "
857 "but running on:0x%04x (Rev %d)\n",
858 CPUID, bfin_compiled_revid(), bfin_cpuid(), bfin_revid());
859
860 pr_notice("ADSP-%s-0.%d",
861 CPU, bfin_compiled_revid());
862
863 if (bfin_compiled_revid() != bfin_revid())
864 pr_cont("(Detected 0.%d)", bfin_revid());
865
866 pr_cont(" %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n",
867 get_cclk()/1000000, get_sclk()/1000000,
868#ifdef CONFIG_MPU
869 "mpu on"
870#else
871 "mpu off"
872#endif
873 );
874
875 pr_notice("%s", linux_banner);
876
877 pr_notice("\nSEQUENCER STATUS:\t\t%s\n", print_tainted());
878 pr_notice(" SEQSTAT: %08lx IPEND: %04lx IMASK: %04lx SYSCFG: %04lx\n",
879 (long)fp->seqstat, fp->ipend, cpu_pda[raw_smp_processor_id()].ex_imask, fp->syscfg);
880 if (fp->ipend & EVT_IRPTEN)
881 pr_notice(" Global Interrupts Disabled (IPEND[4])\n");
882 if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG13 | EVT_IVG12 | EVT_IVG11 |
883 EVT_IVG10 | EVT_IVG9 | EVT_IVG8 | EVT_IVG7 | EVT_IVTMR)))
884 pr_notice(" Peripheral interrupts masked off\n");
885 if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG15 | EVT_IVG14)))
886 pr_notice(" Kernel interrupts masked off\n");
887 if ((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) {
888 pr_notice(" HWERRCAUSE: 0x%lx\n",
889 (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14);
890#ifdef EBIU_ERRMST
891
892 if (bfin_read_EBIU_ERRMST() & CORE_ERROR) {
893 pr_notice(" EBIU Error Reason : 0x%04x\n",
894 bfin_read_EBIU_ERRMST());
895 pr_notice(" EBIU Error Address : 0x%08x\n",
896 bfin_read_EBIU_ERRADD());
897 }
898#endif
899 }
900 pr_notice(" EXCAUSE : 0x%lx\n",
901 fp->seqstat & SEQSTAT_EXCAUSE);
902 for (i = 2; i <= 15 ; i++) {
903 if (fp->ipend & (1 << i)) {
904 if (i != 4) {
905 decode_address(buf, bfin_read32(EVT0 + 4*i));
906 pr_notice(" physical IVG%i asserted : %s\n", i, buf);
907 } else
908 pr_notice(" interrupts disabled\n");
909 }
910 }
911
912
913 if (fp->ipend & ~0x3F) {
914 for (i = 0; i < (NR_IRQS - 1); i++) {
915 if (!in_atomic)
916 raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
917
918 action = irq_desc[i].action;
919 if (!action)
920 goto unlock;
921
922 decode_address(buf, (unsigned int)action->handler);
923 pr_notice(" logical irq %3d mapped : %s", i, buf);
924 for (action = action->next; action; action = action->next) {
925 decode_address(buf, (unsigned int)action->handler);
926 pr_cont(", %s", buf);
927 }
928 pr_cont("\n");
929unlock:
930 if (!in_atomic)
931 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
932 }
933 }
934
935 decode_address(buf, fp->rete);
936 pr_notice(" RETE: %s\n", buf);
937 decode_address(buf, fp->retn);
938 pr_notice(" RETN: %s\n", buf);
939 decode_address(buf, fp->retx);
940 pr_notice(" RETX: %s\n", buf);
941 decode_address(buf, fp->rets);
942 pr_notice(" RETS: %s\n", buf);
943 decode_address(buf, fp->pc);
944 pr_notice(" PC : %s\n", buf);
945
946 if (((long)fp->seqstat & SEQSTAT_EXCAUSE) &&
947 (((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) {
948 decode_address(buf, cpu_pda[cpu].dcplb_fault_addr);
949 pr_notice("DCPLB_FAULT_ADDR: %s\n", buf);
950 decode_address(buf, cpu_pda[cpu].icplb_fault_addr);
951 pr_notice("ICPLB_FAULT_ADDR: %s\n", buf);
952 }
953
954 pr_notice("PROCESSOR STATE:\n");
955 pr_notice(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n",
956 fp->r0, fp->r1, fp->r2, fp->r3);
957 pr_notice(" R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n",
958 fp->r4, fp->r5, fp->r6, fp->r7);
959 pr_notice(" P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n",
960 fp->p0, fp->p1, fp->p2, fp->p3);
961 pr_notice(" P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n",
962 fp->p4, fp->p5, fp->fp, (long)fp);
963 pr_notice(" LB0: %08lx LT0: %08lx LC0: %08lx\n",
964 fp->lb0, fp->lt0, fp->lc0);
965 pr_notice(" LB1: %08lx LT1: %08lx LC1: %08lx\n",
966 fp->lb1, fp->lt1, fp->lc1);
967 pr_notice(" B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n",
968 fp->b0, fp->l0, fp->m0, fp->i0);
969 pr_notice(" B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n",
970 fp->b1, fp->l1, fp->m1, fp->i1);
971 pr_notice(" B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n",
972 fp->b2, fp->l2, fp->m2, fp->i2);
973 pr_notice(" B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n",
974 fp->b3, fp->l3, fp->m3, fp->i3);
975 pr_notice("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
976 fp->a0w, fp->a0x, fp->a1w, fp->a1x);
977
978 pr_notice("USP : %08lx ASTAT: %08lx\n",
979 rdusp(), fp->astat);
980
981 pr_notice("\n");
982}
983
