LXR linux/arch/m32r/kernel/sys

   1/*
   2 * linux/arch/m32r/kernel/sys_m32r.c
   3 *
   4 * This file contains various random system calls that
   5 * have a non-standard calling sequence on the Linux/M32R platform.
   6 *
   7 * Taken from i386 version.
   8 */
   9
  10#include <linux/errno.h>
  11#include <linux/sched.h>
  12#include <linux/mm.h>
  13#include <linux/fs.h>
  14#include <linux/smp.h>
  15#include <linux/sem.h>
  16#include <linux/msg.h>
  17#include <linux/shm.h>
  18#include <linux/stat.h>
  19#include <linux/syscalls.h>
  20#include <linux/mman.h>
  21#include <linux/file.h>
  22#include <linux/utsname.h>
  23#include <linux/ipc.h>
  24
  25#include <asm/uaccess.h>
  26#include <asm/cachectl.h>
  27#include <asm/cacheflush.h>
  28#include <asm/syscall.h>
  29#include <asm/unistd.h>
  30
  31/*
  32 * sys_tas() - test-and-set
  33 */
  34asmlinkage int sys_tas(int __user *addr)
  35{
  36        int oldval;
  37
  38        if (!access_ok(VERIFY_WRITE, addr, sizeof (int)))
  39                return -EFAULT;
  40
  41        /* atomic operation:
  42         *   oldval = *addr; *addr = 1;
  43         */
  44        __asm__ __volatile__ (
  45                DCACHE_CLEAR("%0", "r4", "%1")
  46                "       .fillinsn\n"
  47                "1:\n"
  48                "       lock    %0, @%1     ->  unlock  %2, @%1\n"
  49                "2:\n"
  50                /* NOTE:
  51                 *   The m32r processor can accept interrupts only
  52                 *   at the 32-bit instruction boundary.
  53                 *   So, in the above code, the "unlock" instruction
  54                 *   can be executed continuously after the "lock"
  55                 *   instruction execution without any interruptions.
  56                 */
  57                ".section .fixup,\"ax\"\n"
  58                "       .balign 4\n"
  59                "3:     ldi     %0, #%3\n"
  60                "       seth    r14, #high(2b)\n"
  61                "       or3     r14, r14, #low(2b)\n"
  62                "       jmp     r14\n"
  63                ".previous\n"
  64                ".section __ex_table,\"a\"\n"
  65                "       .balign 4\n"
  66                "       .long 1b,3b\n"
  67                ".previous\n"
  68                : "=&r" (oldval)
  69                : "r" (addr), "r" (1), "i"(-EFAULT)
  70                : "r14", "memory"
  71#ifdef CONFIG_CHIP_M32700_TS1
  72                  , "r4"
  73#endif /* CONFIG_CHIP_M32700_TS1 */
  74        );
  75
  76        return oldval;
  77}
  78
  79asmlinkage int sys_cacheflush(void *addr, int bytes, int cache)
  80{
  81        /* This should flush more selectively ...  */
  82        _flush_cache_all();
  83        return 0;
  84}
  85
  86asmlinkage int sys_cachectl(char *addr, int nbytes, int op)
  87{
  88        /* Not implemented yet. */
  89        return -ENOSYS;
  90}
  91
  92/*
  93 * Do a system call from kernel instead of calling sys_execve so we
  94 * end up with proper pt_regs.
  95 */
  96int kernel_execve(const char *filename,
  97                  const char *const argv[],
  98                  const char *const envp[])
  99{
 100        register long __scno __asm__ ("r7") = __NR_execve;
 101        register long __arg3 __asm__ ("r2") = (long)(envp);
 102        register long __arg2 __asm__ ("r1") = (long)(argv);
 103        register long __res __asm__ ("r0") = (long)(filename);
 104        __asm__ __volatile__ (
 105                "trap #" SYSCALL_VECTOR "|| nop"
 106                : "=r" (__res)
 107                : "r" (__scno), "0" (__res), "r" (__arg2),
 108                        "r" (__arg3)
 109                : "memory");
 110        return __res;
 111}
 112