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20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/irq.h>
23
24#include <asm/irq_cpu.h>
25#include <asm/mipsregs.h>
26#include <asm/mach-ar7/ar7.h>
27
28#define EXCEPT_OFFSET 0x80
29#define PACE_OFFSET 0xA0
30#define CHNLS_OFFSET 0x200
31
32#define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10)
33#define SEC_REG_OFFSET(reg) (EXCEPT_OFFSET + reg * 0x8)
34#define SEC_SR_OFFSET (SEC_REG_OFFSET(0))
35#define CR_OFFSET(irq) (REG_OFFSET(irq, 1))
36#define SEC_CR_OFFSET (SEC_REG_OFFSET(1))
37#define ESR_OFFSET(irq) (REG_OFFSET(irq, 2))
38#define SEC_ESR_OFFSET (SEC_REG_OFFSET(2))
39#define ECR_OFFSET(irq) (REG_OFFSET(irq, 3))
40#define SEC_ECR_OFFSET (SEC_REG_OFFSET(3))
41#define PIR_OFFSET (0x40)
42#define MSR_OFFSET (0x44)
43#define PM_OFFSET(irq) (REG_OFFSET(irq, 5))
44#define TM_OFFSET(irq) (REG_OFFSET(irq, 6))
45
46#define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr))
47
48#define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4))
49
50static int ar7_irq_base;
51
52static void ar7_unmask_irq(unsigned int irq)
53{
54 writel(1 << ((irq - ar7_irq_base) % 32),
55 REG(ESR_OFFSET(irq - ar7_irq_base)));
56}
57
58static void ar7_mask_irq(unsigned int irq)
59{
60 writel(1 << ((irq - ar7_irq_base) % 32),
61 REG(ECR_OFFSET(irq - ar7_irq_base)));
62}
63
64static void ar7_ack_irq(unsigned int irq)
65{
66 writel(1 << ((irq - ar7_irq_base) % 32),
67 REG(CR_OFFSET(irq - ar7_irq_base)));
68}
69
70static void ar7_unmask_sec_irq(unsigned int irq)
71{
72 writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET));
73}
74
75static void ar7_mask_sec_irq(unsigned int irq)
76{
77 writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET));
78}
79
80static void ar7_ack_sec_irq(unsigned int irq)
81{
82 writel(1 << (irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET));
83}
84
85static struct irq_chip ar7_irq_type = {
86 .name = "AR7",
87 .unmask = ar7_unmask_irq,
88 .mask = ar7_mask_irq,
89 .ack = ar7_ack_irq
90};
91
92static struct irq_chip ar7_sec_irq_type = {
93 .name = "AR7",
94 .unmask = ar7_unmask_sec_irq,
95 .mask = ar7_mask_sec_irq,
96 .ack = ar7_ack_sec_irq,
97};
98
99static struct irqaction ar7_cascade_action = {
100 .handler = no_action,
101 .name = "AR7 cascade interrupt"
102};
103
104static void __init ar7_irq_init(int base)
105{
106 int i;
107
108
109
110 writel(0xffffffff, REG(ECR_OFFSET(0)));
111 writel(0xff, REG(ECR_OFFSET(32)));
112 writel(0xffffffff, REG(SEC_ECR_OFFSET));
113 writel(0xffffffff, REG(CR_OFFSET(0)));
114 writel(0xff, REG(CR_OFFSET(32)));
115 writel(0xffffffff, REG(SEC_CR_OFFSET));
116
117 ar7_irq_base = base;
118
119 for (i = 0; i < 40; i++) {
120 writel(i, REG(CHNL_OFFSET(i)));
121
122 set_irq_chip_and_handler(base + i, &ar7_irq_type,
123 handle_level_irq);
124
125 if (i < 32)
126 set_irq_chip_and_handler(base + i + 40,
127 &ar7_sec_irq_type,
128 handle_level_irq);
129 }
130
131 setup_irq(2, &ar7_cascade_action);
132 setup_irq(ar7_irq_base, &ar7_cascade_action);
133 set_c0_status(IE_IRQ0);
134}
135
136void __init arch_init_irq(void)
137{
138 mips_cpu_irq_init();
139 ar7_irq_init(8);
140}
141
142static void ar7_cascade(void)
143{
144 u32 status;
145 int i, irq;
146
147
148 irq = readl(REG(PIR_OFFSET)) & 0x3f;
149 if (irq) {
150 do_IRQ(ar7_irq_base + irq);
151 return;
152 }
153
154
155 writel(1, REG(CR_OFFSET(irq)));
156 status = readl(REG(SEC_SR_OFFSET));
157 for (i = 0; i < 32; i++) {
158 if (status & 1) {
159 do_IRQ(ar7_irq_base + i + 40);
160 return;
161 }
162 status >>= 1;
163 }
164
165 spurious_interrupt();
166}
167
168asmlinkage void plat_irq_dispatch(void)
169{
170 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
171 if (pending & STATUSF_IP7)
172 do_IRQ(7);
173 else if (pending & STATUSF_IP2)
174 ar7_cascade();
175 else
176 spurious_interrupt();
177}
178