LXR linux/arch/mips/include/asm/processor.h

   1/*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 1994 Waldorf GMBH
   7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
   8 * Copyright (C) 1996 Paul M. Antoine
   9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  10 */
  11#ifndef _ASM_PROCESSOR_H
  12#define _ASM_PROCESSOR_H
  13
  14#include <linux/cpumask.h>
  15#include <linux/threads.h>
  16
  17#include <asm/cachectl.h>
  18#include <asm/cpu.h>
  19#include <asm/cpu-info.h>
  20#include <asm/mipsregs.h>
  21#include <asm/prefetch.h>
  22#include <asm/system.h>
  23
  24/*
  25 * Return current * instruction pointer ("program counter").
  26 */
  27#define current_text_addr() ({ __label__ _l; _l: &&_l;})
  28
  29/*
  30 * System setup and hardware flags..
  31 */
  32extern void (*cpu_wait)(void);
  33
  34extern unsigned int vced_count, vcei_count;
  35
  36/*
  37 * MIPS does have an arch_pick_mmap_layout()
  38 */
  39#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
  40
  41/*
  42 * A special page (the vdso) is mapped into all processes at the very
  43 * top of the virtual memory space.
  44 */
  45#define SPECIAL_PAGES_SIZE PAGE_SIZE
  46
  47#ifdef CONFIG_32BIT
  48/*
  49 * User space process size: 2GB. This is hardcoded into a few places,
  50 * so don't change it unless you know what you are doing.
  51 */
  52#define TASK_SIZE       0x7fff8000UL
  53
  54#ifdef __KERNEL__
  55#define STACK_TOP_MAX   TASK_SIZE
  56#endif
  57
  58#define TASK_IS_32BIT_ADDR 1
  59
  60#endif
  61
  62#ifdef CONFIG_64BIT
  63/*
  64 * User space process size: 1TB. This is hardcoded into a few places,
  65 * so don't change it unless you know what you are doing.  TASK_SIZE
  66 * is limited to 1TB by the R4000 architecture; R10000 and better can
  67 * support 16TB; the architectural reserve for future expansion is
  68 * 8192EB ...
  69 */
  70#define TASK_SIZE32     0x7fff8000UL
  71#define TASK_SIZE64     0x10000000000UL
  72#define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
  73
  74#ifdef __KERNEL__
  75#define STACK_TOP_MAX   TASK_SIZE64
  76#endif
  77
  78
  79#define TASK_SIZE_OF(tsk)                                               \
  80        (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
  81
  82#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
  83
  84#endif
  85
  86#define STACK_TOP       ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE)
  87
  88/*
  89 * This decides where the kernel will search for a free chunk of vm
  90 * space during mmap's.
  91 */
  92#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
  93
  94
  95#define NUM_FPU_REGS    32
  96
  97typedef __u64 fpureg_t;
  98
  99/*
 100 * It would be nice to add some more fields for emulator statistics, but there
 101 * are a number of fixed offsets in offset.h and elsewhere that would have to
 102 * be recalculated by hand.  So the additional information will be private to
 103 * the FPU emulator for now.  See asm-mips/fpu_emulator.h.
 104 */
 105
 106struct mips_fpu_struct {
 107        fpureg_t        fpr[NUM_FPU_REGS];
 108        unsigned int    fcr31;
 109};
 110
 111#define NUM_DSP_REGS   6
 112
 113typedef __u32 dspreg_t;
 114
 115struct mips_dsp_state {
 116        dspreg_t        dspr[NUM_DSP_REGS];
 117        unsigned int    dspcontrol;
 118};
 119
 120#define INIT_CPUMASK { \
 121        {0,} \
 122}
 123
 124struct mips3264_watch_reg_state {
 125        /* The width of watchlo is 32 in a 32 bit kernel and 64 in a
 126           64 bit kernel.  We use unsigned long as it has the same
 127           property. */
 128        unsigned long watchlo[NUM_WATCH_REGS];
 129        /* Only the mask and IRW bits from watchhi. */
 130        u16 watchhi[NUM_WATCH_REGS];
 131};
 132
 133union mips_watch_reg_state {
 134        struct mips3264_watch_reg_state mips3264;
 135};
 136
 137#ifdef CONFIG_CPU_CAVIUM_OCTEON
 138
 139struct octeon_cop2_state {
 140        /* DMFC2 rt, 0x0201 */
 141        unsigned long   cop2_crc_iv;
 142        /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
 143        unsigned long   cop2_crc_length;
 144        /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
 145        unsigned long   cop2_crc_poly;
 146        /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
 147        unsigned long   cop2_llm_dat[2];
 148       /* DMFC2 rt, 0x0084 */
 149        unsigned long   cop2_3des_iv;
 150        /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
 151        unsigned long   cop2_3des_key[3];
 152        /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
 153        unsigned long   cop2_3des_result;
 154        /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
 155        unsigned long   cop2_aes_inp0;
 156        /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
 157        unsigned long   cop2_aes_iv[2];
 158        /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
 159         * rt, 0x0107 */
 160        unsigned long   cop2_aes_key[4];
 161        /* DMFC2 rt, 0x0110 */
 162        unsigned long   cop2_aes_keylen;
 163        /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
 164        unsigned long   cop2_aes_result[2];
 165        /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
 166         * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
 167         * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
 168         * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
 169         * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
 170        unsigned long   cop2_hsh_datw[15];
 171        /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
 172         * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
 173         * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
 174        unsigned long   cop2_hsh_ivw[8];
 175        /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
 176        unsigned long   cop2_gfm_mult[2];
 177        /* DMFC2 rt, 0x025E - Pass2 */
 178        unsigned long   cop2_gfm_poly;
 179        /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
 180        unsigned long   cop2_gfm_result[2];
 181};
 182#define INIT_OCTEON_COP2 {0,}
 183
 184struct octeon_cvmseg_state {
 185        unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
 186                            [cpu_dcache_line_size() / sizeof(unsigned long)];
 187};
 188
 189#endif
 190
 191typedef struct {
 192        unsigned long seg;
 193} mm_segment_t;
 194
 195#define ARCH_MIN_TASKALIGN      8
 196
 197struct mips_abi;
 198
 199/*
 200 * If you change thread_struct remember to change the #defines below too!
 201 */
 202struct thread_struct {
 203        /* Saved main processor registers. */
 204        unsigned long reg16;
 205        unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
 206        unsigned long reg29, reg30, reg31;
 207
 208        /* Saved cp0 stuff. */
 209        unsigned long cp0_status;
 210
 211        /* Saved fpu/fpu emulator stuff. */
 212        struct mips_fpu_struct fpu;
 213#ifdef CONFIG_MIPS_MT_FPAFF
 214        /* Emulated instruction count */
 215        unsigned long emulated_fp;
 216        /* Saved per-thread scheduler affinity mask */
 217        cpumask_t user_cpus_allowed;
 218#endif /* CONFIG_MIPS_MT_FPAFF */
 219
 220        /* Saved state of the DSP ASE, if available. */
 221        struct mips_dsp_state dsp;
 222
 223        /* Saved watch register state, if available. */
 224        union mips_watch_reg_state watch;
 225
 226        /* Other stuff associated with the thread. */
 227        unsigned long cp0_badvaddr;     /* Last user fault */
 228        unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
 229        unsigned long error_code;
 230        unsigned long irix_trampoline;  /* Wheee... */
 231        unsigned long irix_oldctx;
 232#ifdef CONFIG_CPU_CAVIUM_OCTEON
 233    struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
 234    struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
 235#endif
 236        struct mips_abi *abi;
 237};
 238
 239#ifdef CONFIG_MIPS_MT_FPAFF
 240#define FPAFF_INIT                                              \
 241        .emulated_fp                    = 0,                    \
 242        .user_cpus_allowed              = INIT_CPUMASK,
 243#else
 244#define FPAFF_INIT
 245#endif /* CONFIG_MIPS_MT_FPAFF */
 246
 247#ifdef CONFIG_CPU_CAVIUM_OCTEON
 248#define OCTEON_INIT                                             \
 249        .cp2                    = INIT_OCTEON_COP2,
 250#else
 251#define OCTEON_INIT
 252#endif /* CONFIG_CPU_CAVIUM_OCTEON */
 253
 254#define INIT_THREAD  {                                          \
 255        /*                                                      \
 256         * Saved main processor registers                       \
 257         */                                                     \
 258        .reg16                  = 0,                            \
 259        .reg17                  = 0,                            \
 260        .reg18                  = 0,                            \
 261        .reg19                  = 0,                            \
 262        .reg20                  = 0,                            \
 263        .reg21                  = 0,                            \
 264        .reg22                  = 0,                            \
 265        .reg23                  = 0,                            \
 266        .reg29                  = 0,                            \
 267        .reg30                  = 0,                            \
 268        .reg31                  = 0,                            \
 269        /*                                                      \
 270         * Saved cp0 stuff                                      \
 271         */                                                     \
 272        .cp0_status             = 0,                            \
 273        /*                                                      \
 274         * Saved FPU/FPU emulator stuff                         \
 275         */                                                     \
 276        .fpu                    = {                             \
 277                .fpr            = {0,},                         \
 278                .fcr31          = 0,                            \
 279        },                                                      \
 280        /*                                                      \
 281         * FPU affinity state (null if not FPAFF)               \
 282         */                                                     \
 283        FPAFF_INIT                                              \
 284        /*                                                      \
 285         * Saved DSP stuff                                      \
 286         */                                                     \
 287        .dsp                    = {                             \
 288                .dspr           = {0, },                        \
 289                .dspcontrol     = 0,                            \
 290        },                                                      \
 291        /*                                                      \
 292         * saved watch register stuff                           \
 293         */                                                     \
 294        .watch = {{{0,},},},                                    \
 295        /*                                                      \
 296         * Other stuff associated with the process              \
 297         */                                                     \
 298        .cp0_badvaddr           = 0,                            \
 299        .cp0_baduaddr           = 0,                            \
 300        .error_code             = 0,                            \
 301        .irix_trampoline        = 0,                            \
 302        .irix_oldctx            = 0,                            \
 303        /*                                                      \
 304         * Cavium Octeon specifics (null if not Octeon)         \
 305         */                                                     \
 306        OCTEON_INIT                                             \
 307}
 308
 309struct task_struct;
 310
 311/* Free all resources held by a thread. */
 312#define release_thread(thread) do { } while(0)
 313
 314/* Prepare to copy thread state - unlazy all lazy status */
 315#define prepare_to_copy(tsk)    do { } while (0)
 316
 317extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
 318
 319extern unsigned long thread_saved_pc(struct task_struct *tsk);
 320
 321/*
 322 * Do necessary setup to start up a newly executed thread.
 323 */
 324extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
 325
 326unsigned long get_wchan(struct task_struct *p);
 327
 328#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
 329                         THREAD_SIZE - 32 - sizeof(struct pt_regs))
 330#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
 331#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
 332#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
 333#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
 334
 335#define cpu_relax()     barrier()
 336
 337/*
 338 * Return_address is a replacement for __builtin_return_address(count)
 339 * which on certain architectures cannot reasonably be implemented in GCC
 340 * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386).
 341 * Note that __builtin_return_address(x>=1) is forbidden because GCC
 342 * aborts compilation on some CPUs.  It's simply not possible to unwind
 343 * some CPU's stackframes.
 344 *
 345 * __builtin_return_address works only for non-leaf functions.  We avoid the
 346 * overhead of a function call by forcing the compiler to save the return
 347 * address register on the stack.
 348 */
 349#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
 350
 351#ifdef CONFIG_CPU_HAS_PREFETCH
 352
 353#define ARCH_HAS_PREFETCH
 354#define prefetch(x) __builtin_prefetch((x), 0, 1)
 355
 356#define ARCH_HAS_PREFETCHW
 357#define prefetchw(x) __builtin_prefetch((x), 1, 1)
 358
 359#endif
 360
 361#endif /* _ASM_PROCESSOR_H */
 362