LXR linux/arch/mips/math-emu/dsemul.c

   1#include <linux/compiler.h>
   2#include <linux/mm.h>
   3#include <linux/signal.h>
   4#include <linux/smp.h>
   5
   6#include <asm/asm.h>
   7#include <asm/bootinfo.h>
   8#include <asm/byteorder.h>
   9#include <asm/cpu.h>
  10#include <asm/inst.h>
  11#include <asm/processor.h>
  12#include <asm/uaccess.h>
  13#include <asm/branch.h>
  14#include <asm/mipsregs.h>
  15#include <asm/system.h>
  16#include <asm/cacheflush.h>
  17
  18#include <asm/fpu_emulator.h>
  19
  20#include "ieee754.h"
  21
  22/* Strap kernel emulator for full MIPS IV emulation */
  23
  24#ifdef __mips
  25#undef __mips
  26#endif
  27#define __mips 4
  28
  29/*
  30 * Emulate the arbritrary instruction ir at xcp->cp0_epc.  Required when
  31 * we have to emulate the instruction in a COP1 branch delay slot.  Do
  32 * not change cp0_epc due to the instruction
  33 *
  34 * According to the spec:
  35 * 1) it shouldnt be a branch :-)
  36 * 2) it can be a COP instruction :-(
  37 * 3) if we are tring to run a protected memory space we must take
  38 *    special care on memory access instructions :-(
  39 */
  40
  41/*
  42 * "Trampoline" return routine to catch exception following
  43 *  execution of delay-slot instruction execution.
  44 */
  45
  46struct emuframe {
  47        mips_instruction        emul;
  48        mips_instruction        badinst;
  49        mips_instruction        cookie;
  50        unsigned long           epc;
  51};
  52
  53int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
  54{
  55        extern asmlinkage void handle_dsemulret(void);
  56        struct emuframe __user *fr;
  57        int err;
  58
  59        if (ir == 0) {          /* a nop is easy */
  60                regs->cp0_epc = cpc;
  61                regs->cp0_cause &= ~CAUSEF_BD;
  62                return 0;
  63        }
  64#ifdef DSEMUL_TRACE
  65        printk("dsemul %lx %lx\n", regs->cp0_epc, cpc);
  66
  67#endif
  68
  69        /*
  70         * The strategy is to push the instruction onto the user stack
  71         * and put a trap after it which we can catch and jump to
  72         * the required address any alternative apart from full
  73         * instruction emulation!!.
  74         *
  75         * Algorithmics used a system call instruction, and
  76         * borrowed that vector.  MIPS/Linux version is a bit
  77         * more heavyweight in the interests of portability and
  78         * multiprocessor support.  For Linux we generate a
  79         * an unaligned access and force an address error exception.
  80         *
  81         * For embedded systems (stand-alone) we prefer to use a
  82         * non-existing CP1 instruction. This prevents us from emulating
  83         * branches, but gives us a cleaner interface to the exception
  84         * handler (single entry point).
  85         */
  86
  87        /* Ensure that the two instructions are in the same cache line */
  88        fr = (struct emuframe __user *)
  89                ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7);
  90
  91        /* Verify that the stack pointer is not competely insane */
  92        if (unlikely(!access_ok(VERIFY_WRITE, fr, sizeof(struct emuframe))))
  93                return SIGBUS;
  94
  95        err = __put_user(ir, &fr->emul);
  96        err |= __put_user((mips_instruction)BREAK_MATH, &fr->badinst);
  97        err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie);
  98        err |= __put_user(cpc, &fr->epc);
  99
 100        if (unlikely(err)) {
 101                MIPS_FPU_EMU_INC_STATS(errors);
 102                return SIGBUS;
 103        }
 104
 105        regs->cp0_epc = (unsigned long) &fr->emul;
 106
 107        flush_cache_sigtramp((unsigned long)&fr->badinst);
 108
 109        return SIGILL;          /* force out of emulation loop */
 110}
 111
 112int do_dsemulret(struct pt_regs *xcp)
 113{
 114        struct emuframe __user *fr;
 115        unsigned long epc;
 116        u32 insn, cookie;
 117        int err = 0;
 118
 119        fr = (struct emuframe __user *)
 120                (xcp->cp0_epc - sizeof(mips_instruction));
 121
 122        /*
 123         * If we can't even access the area, something is very wrong, but we'll
 124         * leave that to the default handling
 125         */
 126        if (!access_ok(VERIFY_READ, fr, sizeof(struct emuframe)))
 127                return 0;
 128
 129        /*
 130         * Do some sanity checking on the stackframe:
 131         *
 132         *  - Is the instruction pointed to by the EPC an BREAK_MATH?
 133         *  - Is the following memory word the BD_COOKIE?
 134         */
 135        err = __get_user(insn, &fr->badinst);
 136        err |= __get_user(cookie, &fr->cookie);
 137
 138        if (unlikely(err || (insn != BREAK_MATH) || (cookie != BD_COOKIE))) {
 139                MIPS_FPU_EMU_INC_STATS(errors);
 140                return 0;
 141        }
 142
 143        /*
 144         * At this point, we are satisfied that it's a BD emulation trap.  Yes,
 145         * a user might have deliberately put two malformed and useless
 146         * instructions in a row in his program, in which case he's in for a
 147         * nasty surprise - the next instruction will be treated as a
 148         * continuation address!  Alas, this seems to be the only way that we
 149         * can handle signals, recursion, and longjmps() in the context of
 150         * emulating the branch delay instruction.
 151         */
 152
 153#ifdef DSEMUL_TRACE
 154        printk("dsemulret\n");
 155#endif
 156        if (__get_user(epc, &fr->epc)) {                /* Saved EPC */
 157                /* This is not a good situation to be in */
 158                force_sig(SIGBUS, current);
 159
 160                return 0;
 161        }
 162
 163        /* Set EPC to return to post-branch instruction */
 164        xcp->cp0_epc = epc;
 165
 166        return 1;
 167}
 168