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8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/pci.h>
11#include <linux/interrupt.h>
12#include <linux/time.h>
13#include <linux/delay.h>
14#include <linux/swiotlb.h>
15
16#include <asm/time.h>
17
18#include <asm/octeon/octeon.h>
19#include <asm/octeon/cvmx-npi-defs.h>
20#include <asm/octeon/cvmx-pci-defs.h>
21#include <asm/octeon/pci-octeon.h>
22
23#include <dma-coherence.h>
24
25#define USE_OCTEON_INTERNAL_ARBITER
26
27
28
29
30
31
32#define OCTEON_PCI_IOSPACE_BASE 0x80011a0400000000ull
33#define OCTEON_PCI_IOSPACE_SIZE (1ull<<32)
34
35
36#define OCTEON_PCI_MEMSPACE_OFFSET (0x00011b0000000000ull)
37
38u64 octeon_bar1_pci_phys;
39
40
41
42
43union octeon_pci_address {
44 uint64_t u64;
45 struct {
46 uint64_t upper:2;
47 uint64_t reserved:13;
48 uint64_t io:1;
49 uint64_t did:5;
50 uint64_t subdid:3;
51 uint64_t reserved2:4;
52 uint64_t endian_swap:2;
53 uint64_t reserved3:10;
54 uint64_t bus:8;
55 uint64_t dev:5;
56 uint64_t func:3;
57 uint64_t reg:8;
58 } s;
59};
60
61int __initdata (*octeon_pcibios_map_irq)(const struct pci_dev *dev,
62 u8 slot, u8 pin);
63enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
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75
76int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
77{
78 if (octeon_pcibios_map_irq)
79 return octeon_pcibios_map_irq(dev, slot, pin);
80 else
81 panic("octeon_pcibios_map_irq not set.");
82}
83
84
85
86
87
88int pcibios_plat_dev_init(struct pci_dev *dev)
89{
90 uint16_t config;
91 uint32_t dconfig;
92 int pos;
93
94
95
96
97
98
99
100 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
101
102 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48);
103
104
105
106 pci_read_config_word(dev, PCI_COMMAND, &config);
107 config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
108 pci_write_config_word(dev, PCI_COMMAND, config);
109
110 if (dev->subordinate) {
111
112 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48);
113
114 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
115 config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
116 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
117 }
118
119
120 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
121 if (pos) {
122
123 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
124
125 config |= PCI_EXP_DEVCTL_CERE;
126
127 config |= PCI_EXP_DEVCTL_NFERE;
128
129 config |= PCI_EXP_DEVCTL_FERE;
130
131 config |= PCI_EXP_DEVCTL_URRE;
132 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
133 }
134
135
136 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
137 if (pos) {
138
139 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
140 &dconfig);
141 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
142 dconfig);
143
144
145 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
146
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149
150
151
152
153 pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
154 pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
155
156
157 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
158
159 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
160
161 if (config & PCI_ERR_CAP_ECRC_GENC)
162 config |= PCI_ERR_CAP_ECRC_GENE;
163
164 if (config & PCI_ERR_CAP_ECRC_CHKC)
165 config |= PCI_ERR_CAP_ECRC_CHKE;
166 pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
167
168
169 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
170 PCI_ERR_ROOT_CMD_COR_EN |
171 PCI_ERR_ROOT_CMD_NONFATAL_EN |
172 PCI_ERR_ROOT_CMD_FATAL_EN);
173
174 pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
175 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
176 }
177
178 dev->dev.archdata.dma_ops = octeon_pci_dma_map_ops;
179
180 return 0;
181}
182
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190
191
192const char *octeon_get_pci_interrupts(void)
193{
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214
215 switch (octeon_bootinfo->board_type) {
216 case CVMX_BOARD_TYPE_NAO38:
217
218 return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA";
219 case CVMX_BOARD_TYPE_EBH3100:
220 case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
221 case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
222 return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
223 case CVMX_BOARD_TYPE_BBGW_REF:
224 return "AABCD";
225 case CVMX_BOARD_TYPE_THUNDER:
226 case CVMX_BOARD_TYPE_EBH3000:
227 default:
228 return "";
229 }
230}
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242
243int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev,
244 u8 slot, u8 pin)
245{
246 int irq_num;
247 const char *interrupts;
248 int dev_num;
249
250
251 interrupts = octeon_get_pci_interrupts();
252
253 dev_num = dev->devfn >> 3;
254 if (dev_num < strlen(interrupts))
255 irq_num = ((interrupts[dev_num] - 'A' + pin - 1) & 3) +
256 OCTEON_IRQ_PCI_INT0;
257 else
258 irq_num = ((slot + pin - 3) & 3) + OCTEON_IRQ_PCI_INT0;
259 return irq_num;
260}
261
262
263
264
265
266static int octeon_read_config(struct pci_bus *bus, unsigned int devfn,
267 int reg, int size, u32 *val)
268{
269 union octeon_pci_address pci_addr;
270
271 pci_addr.u64 = 0;
272 pci_addr.s.upper = 2;
273 pci_addr.s.io = 1;
274 pci_addr.s.did = 3;
275 pci_addr.s.subdid = 1;
276 pci_addr.s.endian_swap = 1;
277 pci_addr.s.bus = bus->number;
278 pci_addr.s.dev = devfn >> 3;
279 pci_addr.s.func = devfn & 0x7;
280 pci_addr.s.reg = reg;
281
282#if PCI_CONFIG_SPACE_DELAY
283 udelay(PCI_CONFIG_SPACE_DELAY);
284#endif
285 switch (size) {
286 case 4:
287 *val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64));
288 return PCIBIOS_SUCCESSFUL;
289 case 2:
290 *val = le16_to_cpu(cvmx_read64_uint16(pci_addr.u64));
291 return PCIBIOS_SUCCESSFUL;
292 case 1:
293 *val = cvmx_read64_uint8(pci_addr.u64);
294 return PCIBIOS_SUCCESSFUL;
295 }
296 return PCIBIOS_FUNC_NOT_SUPPORTED;
297}
298
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301
302
303static int octeon_write_config(struct pci_bus *bus, unsigned int devfn,
304 int reg, int size, u32 val)
305{
306 union octeon_pci_address pci_addr;
307
308 pci_addr.u64 = 0;
309 pci_addr.s.upper = 2;
310 pci_addr.s.io = 1;
311 pci_addr.s.did = 3;
312 pci_addr.s.subdid = 1;
313 pci_addr.s.endian_swap = 1;
314 pci_addr.s.bus = bus->number;
315 pci_addr.s.dev = devfn >> 3;
316 pci_addr.s.func = devfn & 0x7;
317 pci_addr.s.reg = reg;
318
319#if PCI_CONFIG_SPACE_DELAY
320 udelay(PCI_CONFIG_SPACE_DELAY);
321#endif
322 switch (size) {
323 case 4:
324 cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val));
325 return PCIBIOS_SUCCESSFUL;
326 case 2:
327 cvmx_write64_uint16(pci_addr.u64, cpu_to_le16(val));
328 return PCIBIOS_SUCCESSFUL;
329 case 1:
330 cvmx_write64_uint8(pci_addr.u64, val);
331 return PCIBIOS_SUCCESSFUL;
332 }
333 return PCIBIOS_FUNC_NOT_SUPPORTED;
334}
335
336
337static struct pci_ops octeon_pci_ops = {
338 octeon_read_config,
339 octeon_write_config,
340};
341
342static struct resource octeon_pci_mem_resource = {
343 .start = 0,
344 .end = 0,
345 .name = "Octeon PCI MEM",
346 .flags = IORESOURCE_MEM,
347};
348
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352
353static struct resource octeon_pci_io_resource = {
354 .start = 0x4000,
355 .end = OCTEON_PCI_IOSPACE_SIZE - 1,
356 .name = "Octeon PCI IO",
357 .flags = IORESOURCE_IO,
358};
359
360static struct pci_controller octeon_pci_controller = {
361 .pci_ops = &octeon_pci_ops,
362 .mem_resource = &octeon_pci_mem_resource,
363 .mem_offset = OCTEON_PCI_MEMSPACE_OFFSET,
364 .io_resource = &octeon_pci_io_resource,
365 .io_offset = 0,
366 .io_map_base = OCTEON_PCI_IOSPACE_BASE,
367};
368
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370
371
372
373static void octeon_pci_initialize(void)
374{
375 union cvmx_pci_cfg01 cfg01;
376 union cvmx_npi_ctl_status ctl_status;
377 union cvmx_pci_ctl_status_2 ctl_status_2;
378 union cvmx_pci_cfg19 cfg19;
379 union cvmx_pci_cfg16 cfg16;
380 union cvmx_pci_cfg22 cfg22;
381 union cvmx_pci_cfg56 cfg56;
382
383
384 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1);
385 cvmx_read_csr(CVMX_CIU_SOFT_PRST);
386
387 udelay(2000);
388
389 ctl_status.u64 = 0;
390 ctl_status.s.max_word = 1;
391 ctl_status.s.timer = 1;
392 cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64);
393
394
395
396 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4);
397 cvmx_read_csr(CVMX_CIU_SOFT_PRST);
398
399 udelay(2000);
400
401 ctl_status_2.u32 = 0;
402 ctl_status_2.s.tsr_hwm = 1;
403
404 ctl_status_2.s.bar2pres = 1;
405 ctl_status_2.s.bar2_enb = 1;
406 ctl_status_2.s.bar2_cax = 1;
407 ctl_status_2.s.bar2_esx = 1;
408 ctl_status_2.s.pmo_amod = 1;
409 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
410
411 ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS;
412 ctl_status_2.s.bb1_siz = 1;
413 ctl_status_2.s.bb_ca = 1;
414 ctl_status_2.s.bb_es = 1;
415 ctl_status_2.s.bb1 = 1;
416 ctl_status_2.s.bb0 = 1;
417 }
418
419 octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32);
420 udelay(2000);
421
422 ctl_status_2.u32 = octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2);
423 pr_notice("PCI Status: %s %s-bit\n",
424 ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI",
425 ctl_status_2.s.ap_64ad ? "64" : "32");
426
427 if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
428 union cvmx_pci_cnt_reg cnt_reg_start;
429 union cvmx_pci_cnt_reg cnt_reg_end;
430 unsigned long cycles, pci_clock;
431
432 cnt_reg_start.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
433 cycles = read_c0_cvmcount();
434 udelay(1000);
435 cnt_reg_end.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
436 cycles = read_c0_cvmcount() - cycles;
437 pci_clock = (cnt_reg_end.s.pcicnt - cnt_reg_start.s.pcicnt) /
438 (cycles / (mips_hpt_frequency / 1000000));
439 pr_notice("PCI Clock: %lu MHz\n", pci_clock);
440 }
441
442
443
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447
448
449
450 if (ctl_status_2.s.ap_pcix) {
451 cfg19.u32 = 0;
452
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463
464 cfg19.s.tdomc = 4;
465
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475
476 cfg19.s.mdrrmc = 2;
477
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487
488 cfg19.s.mrbcm = 1;
489 octeon_npi_write32(CVMX_NPI_PCI_CFG19, cfg19.u32);
490 }
491
492
493 cfg01.u32 = 0;
494 cfg01.s.msae = 1;
495 cfg01.s.me = 1;
496 cfg01.s.pee = 1;
497 cfg01.s.see = 1;
498 cfg01.s.fbbe = 1;
499
500 octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
501
502#ifdef USE_OCTEON_INTERNAL_ARBITER
503
504
505
506
507
508 {
509 union cvmx_npi_pci_int_arb_cfg pci_int_arb_cfg;
510
511 pci_int_arb_cfg.u64 = 0;
512 pci_int_arb_cfg.s.en = 1;
513 cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64);
514 }
515#endif
516
517
518
519
520
521
522 cfg16.u32 = 0;
523 cfg16.s.mltd = 1;
524 octeon_npi_write32(CVMX_NPI_PCI_CFG16, cfg16.u32);
525
526
527
528
529
530 cfg22.u32 = 0;
531
532 cfg22.s.mrv = 0xff;
533
534
535
536
537 cfg22.s.flush = 1;
538 octeon_npi_write32(CVMX_NPI_PCI_CFG22, cfg22.u32);
539
540
541
542
543
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546
547 cfg56.u32 = 0;
548 cfg56.s.pxcid = 7;
549 cfg56.s.ncp = 0xe8;
550 cfg56.s.dpere = 1;
551 cfg56.s.roe = 1;
552 cfg56.s.mmbc = 1;
553
554 cfg56.s.most = 3;
555
556
557 octeon_npi_write32(CVMX_NPI_PCI_CFG56, cfg56.u32);
558
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566
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568 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_6, 0x21);
569 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_C, 0x31);
570 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_E, 0x31);
571}
572
573
574
575
576
577static int __init octeon_pci_setup(void)
578{
579 union cvmx_npi_mem_access_subidx mem_access;
580 int index;
581
582
583 if (octeon_has_feature(OCTEON_FEATURE_PCIE))
584 return 0;
585
586
587 octeon_pcibios_map_irq = octeon_pci_pcibios_map_irq;
588
589
590 if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
591 OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
592 OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
593 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_SMALL;
594 else
595 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG;
596
597
598 set_io_port_base(OCTEON_PCI_IOSPACE_BASE);
599 ioport_resource.start = 0;
600 ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1;
601 if (!octeon_is_pci_host()) {
602 pr_notice("Not in host mode, PCI Controller not initialized\n");
603 return 0;
604 }
605
606 pr_notice("%s Octeon big bar support\n",
607 (octeon_dma_bar_type ==
608 OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling");
609
610 octeon_pci_initialize();
611
612 mem_access.u64 = 0;
613 mem_access.s.esr = 1;
614 mem_access.s.esw = 1;
615 mem_access.s.nsr = 0;
616 mem_access.s.nsw = 0;
617 mem_access.s.ror = 0;
618 mem_access.s.row = 0;
619 mem_access.s.ba = 0;
620 cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64);
621
622
623
624
625
626
627
628 octeon_npi_write32(CVMX_NPI_PCI_CFG08,
629 (u32)(OCTEON_BAR2_PCI_ADDRESS & 0xffffffffull));
630 octeon_npi_write32(CVMX_NPI_PCI_CFG09,
631 (u32)(OCTEON_BAR2_PCI_ADDRESS >> 32));
632
633 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
634
635 octeon_npi_write32(CVMX_NPI_PCI_CFG04, 0);
636 octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
637
638
639
640
641
642 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30);
643 octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
644
645
646 octeon_bar1_pci_phys = 0x80000000ull;
647 for (index = 0; index < 32; index++) {
648 union cvmx_pci_bar1_indexx bar1_index;
649
650 bar1_index.u32 = 0;
651
652 bar1_index.s.addr_idx =
653 (octeon_bar1_pci_phys >> 22) + index;
654
655 bar1_index.s.ca = 1;
656
657 bar1_index.s.end_swp = 1;
658
659 bar1_index.s.addr_v = 1;
660 octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
661 bar1_index.u32);
662 }
663
664
665 octeon_pci_mem_resource.start =
666 OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) -
667 (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
668 octeon_pci_mem_resource.end =
669 octeon_pci_mem_resource.start + (1ul << 30);
670 } else {
671
672 octeon_npi_write32(CVMX_NPI_PCI_CFG04, 128ul << 20);
673 octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
674
675
676 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0);
677 octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
678
679
680 octeon_bar1_pci_phys =
681 virt_to_phys(octeon_swiotlb) & ~((1ull << 22) - 1);
682
683 for (index = 0; index < 32; index++) {
684 union cvmx_pci_bar1_indexx bar1_index;
685
686 bar1_index.u32 = 0;
687
688 bar1_index.s.addr_idx =
689 (octeon_bar1_pci_phys >> 22) + index;
690
691 bar1_index.s.ca = 1;
692
693 bar1_index.s.end_swp = 1;
694
695 bar1_index.s.addr_v = 1;
696 octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
697 bar1_index.u32);
698 }
699
700
701 octeon_pci_mem_resource.start =
702 OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) +
703 (4ul << 10);
704 octeon_pci_mem_resource.end =
705 octeon_pci_mem_resource.start + (1ul << 30);
706 }
707
708 register_pci_controller(&octeon_pci_controller);
709
710
711
712
713
714 cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);
715
716 octeon_pci_dma_init();
717
718 return 0;
719}
720
721arch_initcall(octeon_pci_setup);
722