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27#include <linux/bcd.h>
28#include <linux/init.h>
29#include <linux/kernel.h>
30#include <linux/types.h>
31#include <linux/mm.h>
32#include <linux/bootmem.h>
33#include <linux/swap.h>
34#include <linux/ioport.h>
35#include <linux/sched.h>
36#include <linux/interrupt.h>
37#include <linux/timex.h>
38#include <linux/termios.h>
39#include <linux/tty.h>
40#include <linux/serial.h>
41#include <linux/serial_core.h>
42#include <linux/serial_8250.h>
43
44#include <asm/time.h>
45#include <asm/bootinfo.h>
46#include <asm/page.h>
47#include <asm/io.h>
48#include <asm/irq.h>
49#include <asm/processor.h>
50#include <asm/reboot.h>
51#include <asm/serial.h>
52#include <asm/titan_dep.h>
53#include <asm/m48t37.h>
54
55#include "setup.h"
56
57unsigned char titan_ge_mac_addr_base[6] = {
58
59 0x00, 0xe0, 0x04, 0x00, 0x00, 0x21
60};
61
62unsigned long cpu_clock_freq;
63unsigned long yosemite_base;
64
65static struct m48t37_rtc *m48t37_base;
66
67void __init bus_error_init(void)
68{
69
70}
71
72
73void read_persistent_clock(struct timespec *ts)
74{
75 unsigned int year, month, day, hour, min, sec;
76 unsigned long flags;
77
78 spin_lock_irqsave(&rtc_lock, flags);
79
80 m48t37_base->control = 0x40;
81
82 year = bcd2bin(m48t37_base->year);
83 year += bcd2bin(m48t37_base->century) * 100;
84
85 month = bcd2bin(m48t37_base->month);
86 day = bcd2bin(m48t37_base->date);
87 hour = bcd2bin(m48t37_base->hour);
88 min = bcd2bin(m48t37_base->min);
89 sec = bcd2bin(m48t37_base->sec);
90
91
92 m48t37_base->control = 0x00;
93 spin_unlock_irqrestore(&rtc_lock, flags);
94
95 ts->tv_sec = mktime(year, month, day, hour, min, sec);
96 ts->tv_nsec = 0;
97}
98
99int rtc_mips_set_time(unsigned long tim)
100{
101 struct rtc_time tm;
102 unsigned long flags;
103
104
105
106
107
108 rtc_time_to_tm(tim, &tm);
109 tm.tm_year += 1900;
110 tm.tm_mon += 1;
111
112 spin_lock_irqsave(&rtc_lock, flags);
113
114 m48t37_base->control = 0x80;
115
116
117 m48t37_base->year = bin2bcd(tm.tm_year % 100);
118 m48t37_base->century = bin2bcd(tm.tm_year / 100);
119
120
121 m48t37_base->month = bin2bcd(tm.tm_mon);
122
123
124 m48t37_base->date = bin2bcd(tm.tm_mday);
125
126
127 m48t37_base->hour = bin2bcd(tm.tm_hour);
128 m48t37_base->min = bin2bcd(tm.tm_min);
129 m48t37_base->sec = bin2bcd(tm.tm_sec);
130
131
132 m48t37_base->day = bin2bcd(tm.tm_wday + 1);
133
134
135 m48t37_base->control = 0x00;
136 spin_unlock_irqrestore(&rtc_lock, flags);
137
138 return 0;
139}
140
141void __init plat_time_init(void)
142{
143 mips_hpt_frequency = cpu_clock_freq / 2;
144mips_hpt_frequency = 33000000 * 3 * 5;
145}
146
147unsigned long ocd_base;
148
149EXPORT_SYMBOL(ocd_base);
150
151
152
153
154
155#define TITAN_UART_CLK 3686400
156#define TITAN_SERIAL_BASE_BAUD (TITAN_UART_CLK / 16)
157#define TITAN_SERIAL_IRQ 4
158#define TITAN_SERIAL_BASE 0xfd000008UL
159
160static void __init py_map_ocd(void)
161{
162 ocd_base = (unsigned long) ioremap(OCD_BASE, OCD_SIZE);
163 if (!ocd_base)
164 panic("Mapping OCD failed - game over. Your score is 0.");
165
166
167 OCD_WRITE(0x0710, 0x0ffff029);
168}
169
170static void __init py_uart_setup(void)
171{
172#ifdef CONFIG_SERIAL_8250
173 struct uart_port up;
174
175
176
177
178
179 memset(&up, 0, sizeof(up));
180 up.membase = (unsigned char *) ioremap(TITAN_SERIAL_BASE, 8);
181 up.irq = TITAN_SERIAL_IRQ;
182 up.uartclk = TITAN_UART_CLK;
183 up.regshift = 0;
184 up.iotype = UPIO_MEM;
185 up.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
186 up.line = 0;
187
188 if (early_serial_setup(&up))
189 printk(KERN_ERR "Early serial init of port 0 failed\n");
190#endif
191}
192
193static void __init py_rtc_setup(void)
194{
195 m48t37_base = ioremap(YOSEMITE_RTC_BASE, YOSEMITE_RTC_SIZE);
196 if (!m48t37_base)
197 printk(KERN_ERR "Mapping the RTC failed\n");
198}
199
200
201static void __init py_late_time_init(void)
202{
203 py_map_ocd();
204 py_uart_setup();
205 py_rtc_setup();
206}
207
208void __init plat_mem_setup(void)
209{
210 late_time_init = py_late_time_init;
211
212
213 add_memory_region(0x00000000, 0x10000000, BOOT_MEM_RAM);
214
215#if 0
216 OCD_WRITE(RM9000x2_OCD_HTSC,
217 OCD_READ(RM9000x2_OCD_HTSC) | HYPERTRANSPORT_ENABLE);
218
219
220 OCD_WRITE(RM9000x2_OCD_HTBAR0, HYPERTRANSPORT_BAR0_ADDR);
221 OCD_WRITE(RM9000x2_OCD_HTMASK0, HYPERTRANSPORT_SIZE0);
222#endif
223}
224