LXR linux/arch/mips/sgi-ip32/ip32-irq.c

   1/*
   2 * Code to handle IP32 IRQs
   3 *
   4 * This file is subject to the terms and conditions of the GNU General Public
   5 * License.  See the file "COPYING" in the main directory of this archive
   6 * for more details.
   7 *
   8 * Copyright (C) 2000 Harald Koerfgen
   9 * Copyright (C) 2001 Keith M Wesolowski
  10 */
  11#include <linux/init.h>
  12#include <linux/kernel_stat.h>
  13#include <linux/types.h>
  14#include <linux/interrupt.h>
  15#include <linux/irq.h>
  16#include <linux/bitops.h>
  17#include <linux/kernel.h>
  18#include <linux/mm.h>
  19#include <linux/random.h>
  20#include <linux/sched.h>
  21
  22#include <asm/irq_cpu.h>
  23#include <asm/mipsregs.h>
  24#include <asm/signal.h>
  25#include <asm/system.h>
  26#include <asm/time.h>
  27#include <asm/ip32/crime.h>
  28#include <asm/ip32/mace.h>
  29#include <asm/ip32/ip32_ints.h>
  30
  31/* issue a PIO read to make sure no PIO writes are pending */
  32static void inline flush_crime_bus(void)
  33{
  34        crime->control;
  35}
  36
  37static void inline flush_mace_bus(void)
  38{
  39        mace->perif.ctrl.misc;
  40}
  41
  42/*
  43 * O2 irq map
  44 *
  45 * IP0 -> software (ignored)
  46 * IP1 -> software (ignored)
  47 * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
  48 * IP3 -> (irq1) X unknown
  49 * IP4 -> (irq2) X unknown
  50 * IP5 -> (irq3) X unknown
  51 * IP6 -> (irq4) X unknown
  52 * IP7 -> (irq5) 7 CPU count/compare timer (system timer)
  53 *
  54 * crime: (C)
  55 *
  56 * CRIME_INT_STAT 31:0:
  57 *
  58 * 0  ->  8  Video in 1
  59 * 1  ->  9 Video in 2
  60 * 2  -> 10  Video out
  61 * 3  -> 11  Mace ethernet
  62 * 4  -> S  SuperIO sub-interrupt
  63 * 5  -> M  Miscellaneous sub-interrupt
  64 * 6  -> A  Audio sub-interrupt
  65 * 7  -> 15  PCI bridge errors
  66 * 8  -> 16  PCI SCSI aic7xxx 0
  67 * 9  -> 17 PCI SCSI aic7xxx 1
  68 * 10 -> 18 PCI slot 0
  69 * 11 -> 19 unused (PCI slot 1)
  70 * 12 -> 20 unused (PCI slot 2)
  71 * 13 -> 21 unused (PCI shared 0)
  72 * 14 -> 22 unused (PCI shared 1)
  73 * 15 -> 23 unused (PCI shared 2)
  74 * 16 -> 24 GBE0 (E)
  75 * 17 -> 25 GBE1 (E)
  76 * 18 -> 26 GBE2 (E)
  77 * 19 -> 27 GBE3 (E)
  78 * 20 -> 28 CPU errors
  79 * 21 -> 29 Memory errors
  80 * 22 -> 30 RE empty edge (E)
  81 * 23 -> 31 RE full edge (E)
  82 * 24 -> 32 RE idle edge (E)
  83 * 25 -> 33 RE empty level
  84 * 26 -> 34 RE full level
  85 * 27 -> 35 RE idle level
  86 * 28 -> 36 unused (software 0) (E)
  87 * 29 -> 37 unused (software 1) (E)
  88 * 30 -> 38 unused (software 2) - crime 1.5 CPU SysCorError (E)
  89 * 31 -> 39 VICE
  90 *
  91 * S, M, A: Use the MACE ISA interrupt register
  92 * MACE_ISA_INT_STAT 31:0
  93 *
  94 * 0-7 -> 40-47 Audio
  95 * 8 -> 48 RTC
  96 * 9 -> 49 Keyboard
  97 * 10 -> X Keyboard polled
  98 * 11 -> 51 Mouse
  99 * 12 -> X Mouse polled
 100 * 13-15 -> 53-55 Count/compare timers
 101 * 16-19 -> 56-59 Parallel (16 E)
 102 * 20-25 -> 60-62 Serial 1 (22 E)
 103 * 26-31 -> 66-71 Serial 2 (28 E)
 104 *
 105 * Note that this means IRQs 12-14, 50, and 52 do not exist.  This is a
 106 * different IRQ map than IRIX uses, but that's OK as Linux irq handling
 107 * is quite different anyway.
 108 */
 109
 110/* Some initial interrupts to set up */
 111extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
 112extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
 113
 114static struct irqaction memerr_irq = {
 115        .handler = crime_memerr_intr,
 116        .flags = IRQF_DISABLED,
 117        .name = "CRIME memory error",
 118};
 119
 120static struct irqaction cpuerr_irq = {
 121        .handler = crime_cpuerr_intr,
 122        .flags = IRQF_DISABLED,
 123        .name = "CRIME CPU error",
 124};
 125
 126/*
 127 * This is for pure CRIME interrupts - ie not MACE.  The advantage?
 128 * We get to split the register in half and do faster lookups.
 129 */
 130
 131static uint64_t crime_mask;
 132
 133static inline void crime_enable_irq(unsigned int irq)
 134{
 135        unsigned int bit = irq - CRIME_IRQ_BASE;
 136
 137        crime_mask |= 1 << bit;
 138        crime->imask = crime_mask;
 139}
 140
 141static inline void crime_disable_irq(unsigned int irq)
 142{
 143        unsigned int bit = irq - CRIME_IRQ_BASE;
 144
 145        crime_mask &= ~(1 << bit);
 146        crime->imask = crime_mask;
 147        flush_crime_bus();
 148}
 149
 150static void crime_level_mask_and_ack_irq(unsigned int irq)
 151{
 152        crime_disable_irq(irq);
 153}
 154
 155static void crime_level_end_irq(unsigned int irq)
 156{
 157        if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 158                crime_enable_irq(irq);
 159}
 160
 161static struct irq_chip crime_level_interrupt = {
 162        .name           = "IP32 CRIME",
 163        .ack            = crime_level_mask_and_ack_irq,
 164        .mask           = crime_disable_irq,
 165        .mask_ack       = crime_level_mask_and_ack_irq,
 166        .unmask         = crime_enable_irq,
 167        .end            = crime_level_end_irq,
 168};
 169
 170static void crime_edge_mask_and_ack_irq(unsigned int irq)
 171{
 172        unsigned int bit = irq - CRIME_IRQ_BASE;
 173        uint64_t crime_int;
 174
 175        /* Edge triggered interrupts must be cleared. */
 176
 177        crime_int = crime->hard_int;
 178        crime_int &= ~(1 << bit);
 179        crime->hard_int = crime_int;
 180
 181        crime_disable_irq(irq);
 182}
 183
 184static void crime_edge_end_irq(unsigned int irq)
 185{
 186        if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 187                crime_enable_irq(irq);
 188}
 189
 190static struct irq_chip crime_edge_interrupt = {
 191        .name           = "IP32 CRIME",
 192        .ack            = crime_edge_mask_and_ack_irq,
 193        .mask           = crime_disable_irq,
 194        .mask_ack       = crime_edge_mask_and_ack_irq,
 195        .unmask         = crime_enable_irq,
 196        .end            = crime_edge_end_irq,
 197};
 198
 199/*
 200 * This is for MACE PCI interrupts.  We can decrease bus traffic by masking
 201 * as close to the source as possible.  This also means we can take the
 202 * next chunk of the CRIME register in one piece.
 203 */
 204
 205static unsigned long macepci_mask;
 206
 207static void enable_macepci_irq(unsigned int irq)
 208{
 209        macepci_mask |= MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ);
 210        mace->pci.control = macepci_mask;
 211        crime_mask |= 1 << (irq - CRIME_IRQ_BASE);
 212        crime->imask = crime_mask;
 213}
 214
 215static void disable_macepci_irq(unsigned int irq)
 216{
 217        crime_mask &= ~(1 << (irq - CRIME_IRQ_BASE));
 218        crime->imask = crime_mask;
 219        flush_crime_bus();
 220        macepci_mask &= ~MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ);
 221        mace->pci.control = macepci_mask;
 222        flush_mace_bus();
 223}
 224
 225static void end_macepci_irq(unsigned int irq)
 226{
 227        if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 228                enable_macepci_irq(irq);
 229}
 230
 231static struct irq_chip ip32_macepci_interrupt = {
 232        .name = "IP32 MACE PCI",
 233        .ack = disable_macepci_irq,
 234        .mask = disable_macepci_irq,
 235        .mask_ack = disable_macepci_irq,
 236        .unmask = enable_macepci_irq,
 237        .end = end_macepci_irq,
 238};
 239
 240/* This is used for MACE ISA interrupts.  That means bits 4-6 in the
 241 * CRIME register.
 242 */
 243
 244#define MACEISA_AUDIO_INT       (MACEISA_AUDIO_SW_INT |         \
 245                                 MACEISA_AUDIO_SC_INT |         \
 246                                 MACEISA_AUDIO1_DMAT_INT |      \
 247                                 MACEISA_AUDIO1_OF_INT |        \
 248                                 MACEISA_AUDIO2_DMAT_INT |      \
 249                                 MACEISA_AUDIO2_MERR_INT |      \
 250                                 MACEISA_AUDIO3_DMAT_INT |      \
 251                                 MACEISA_AUDIO3_MERR_INT)
 252#define MACEISA_MISC_INT        (MACEISA_RTC_INT |              \
 253                                 MACEISA_KEYB_INT |             \
 254                                 MACEISA_KEYB_POLL_INT |        \
 255                                 MACEISA_MOUSE_INT |            \
 256                                 MACEISA_MOUSE_POLL_INT |       \
 257                                 MACEISA_TIMER0_INT |           \
 258                                 MACEISA_TIMER1_INT |           \
 259                                 MACEISA_TIMER2_INT)
 260#define MACEISA_SUPERIO_INT     (MACEISA_PARALLEL_INT |         \
 261                                 MACEISA_PAR_CTXA_INT |         \
 262                                 MACEISA_PAR_CTXB_INT |         \
 263                                 MACEISA_PAR_MERR_INT |         \
 264                                 MACEISA_SERIAL1_INT |          \
 265                                 MACEISA_SERIAL1_TDMAT_INT |    \
 266                                 MACEISA_SERIAL1_TDMAPR_INT |   \
 267                                 MACEISA_SERIAL1_TDMAME_INT |   \
 268                                 MACEISA_SERIAL1_RDMAT_INT |    \
 269                                 MACEISA_SERIAL1_RDMAOR_INT |   \
 270                                 MACEISA_SERIAL2_INT |          \
 271                                 MACEISA_SERIAL2_TDMAT_INT |    \
 272                                 MACEISA_SERIAL2_TDMAPR_INT |   \
 273                                 MACEISA_SERIAL2_TDMAME_INT |   \
 274                                 MACEISA_SERIAL2_RDMAT_INT |    \
 275                                 MACEISA_SERIAL2_RDMAOR_INT)
 276
 277static unsigned long maceisa_mask;
 278
 279static void enable_maceisa_irq(unsigned int irq)
 280{
 281        unsigned int crime_int = 0;
 282
 283        pr_debug("maceisa enable: %u\n", irq);
 284
 285        switch (irq) {
 286        case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
 287                crime_int = MACE_AUDIO_INT;
 288                break;
 289        case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ:
 290                crime_int = MACE_MISC_INT;
 291                break;
 292        case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ:
 293                crime_int = MACE_SUPERIO_INT;
 294                break;
 295        }
 296        pr_debug("crime_int %08x enabled\n", crime_int);
 297        crime_mask |= crime_int;
 298        crime->imask = crime_mask;
 299        maceisa_mask |= 1 << (irq - MACEISA_AUDIO_SW_IRQ);
 300        mace->perif.ctrl.imask = maceisa_mask;
 301}
 302
 303static void disable_maceisa_irq(unsigned int irq)
 304{
 305        unsigned int crime_int = 0;
 306
 307        maceisa_mask &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
 308        if (!(maceisa_mask & MACEISA_AUDIO_INT))
 309                crime_int |= MACE_AUDIO_INT;
 310        if (!(maceisa_mask & MACEISA_MISC_INT))
 311                crime_int |= MACE_MISC_INT;
 312        if (!(maceisa_mask & MACEISA_SUPERIO_INT))
 313                crime_int |= MACE_SUPERIO_INT;
 314        crime_mask &= ~crime_int;
 315        crime->imask = crime_mask;
 316        flush_crime_bus();
 317        mace->perif.ctrl.imask = maceisa_mask;
 318        flush_mace_bus();
 319}
 320
 321static void mask_and_ack_maceisa_irq(unsigned int irq)
 322{
 323        unsigned long mace_int;
 324
 325        /* edge triggered */
 326        mace_int = mace->perif.ctrl.istat;
 327        mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
 328        mace->perif.ctrl.istat = mace_int;
 329
 330        disable_maceisa_irq(irq);
 331}
 332
 333static void end_maceisa_irq(unsigned irq)
 334{
 335        if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 336                enable_maceisa_irq(irq);
 337}
 338
 339static struct irq_chip ip32_maceisa_level_interrupt = {
 340        .name           = "IP32 MACE ISA",
 341        .ack            = disable_maceisa_irq,
 342        .mask           = disable_maceisa_irq,
 343        .mask_ack       = disable_maceisa_irq,
 344        .unmask         = enable_maceisa_irq,
 345        .end            = end_maceisa_irq,
 346};
 347
 348static struct irq_chip ip32_maceisa_edge_interrupt = {
 349        .name           = "IP32 MACE ISA",
 350        .ack            = mask_and_ack_maceisa_irq,
 351        .mask           = disable_maceisa_irq,
 352        .mask_ack       = mask_and_ack_maceisa_irq,
 353        .unmask         = enable_maceisa_irq,
 354        .end            = end_maceisa_irq,
 355};
 356
 357/* This is used for regular non-ISA, non-PCI MACE interrupts.  That means
 358 * bits 0-3 and 7 in the CRIME register.
 359 */
 360
 361static void enable_mace_irq(unsigned int irq)
 362{
 363        unsigned int bit = irq - CRIME_IRQ_BASE;
 364
 365        crime_mask |= (1 << bit);
 366        crime->imask = crime_mask;
 367}
 368
 369static void disable_mace_irq(unsigned int irq)
 370{
 371        unsigned int bit = irq - CRIME_IRQ_BASE;
 372
 373        crime_mask &= ~(1 << bit);
 374        crime->imask = crime_mask;
 375        flush_crime_bus();
 376}
 377
 378static void end_mace_irq(unsigned int irq)
 379{
 380        if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 381                enable_mace_irq(irq);
 382}
 383
 384static struct irq_chip ip32_mace_interrupt = {
 385        .name = "IP32 MACE",
 386        .ack = disable_mace_irq,
 387        .mask = disable_mace_irq,
 388        .mask_ack = disable_mace_irq,
 389        .unmask = enable_mace_irq,
 390        .end = end_mace_irq,
 391};
 392
 393static void ip32_unknown_interrupt(void)
 394{
 395        printk("Unknown interrupt occurred!\n");
 396        printk("cp0_status: %08x\n", read_c0_status());
 397        printk("cp0_cause: %08x\n", read_c0_cause());
 398        printk("CRIME intr mask: %016lx\n", crime->imask);
 399        printk("CRIME intr status: %016lx\n", crime->istat);
 400        printk("CRIME hardware intr register: %016lx\n", crime->hard_int);
 401        printk("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
 402        printk("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
 403        printk("MACE PCI control register: %08x\n", mace->pci.control);
 404
 405        printk("Register dump:\n");
 406        show_regs(get_irq_regs());
 407
 408        printk("Please mail this report to linux-mips@linux-mips.org\n");
 409        printk("Spinning...");
 410        while(1) ;
 411}
 412
 413/* CRIME 1.1 appears to deliver all interrupts to this one pin. */
 414/* change this to loop over all edge-triggered irqs, exception masked out ones */
 415static void ip32_irq0(void)
 416{
 417        uint64_t crime_int;
 418        int irq = 0;
 419
 420        /*
 421         * Sanity check interrupt numbering enum.
 422         * MACE got 32 interrupts and there are 32 MACE ISA interrupts daisy
 423         * chained.
 424         */
 425        BUILD_BUG_ON(CRIME_VICE_IRQ - MACE_VID_IN1_IRQ != 31);
 426        BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31);
 427
 428        crime_int = crime->istat & crime_mask;
 429
 430        /* crime sometime delivers spurious interrupts, ignore them */
 431        if (unlikely(crime_int == 0))
 432                return;
 433
 434        irq = MACE_VID_IN1_IRQ + __ffs(crime_int);
 435
 436        if (crime_int & CRIME_MACEISA_INT_MASK) {
 437                unsigned long mace_int = mace->perif.ctrl.istat;
 438                irq = __ffs(mace_int & maceisa_mask) + MACEISA_AUDIO_SW_IRQ;
 439        }
 440
 441        pr_debug("*irq %u*\n", irq);
 442        do_IRQ(irq);
 443}
 444
 445static void ip32_irq1(void)
 446{
 447        ip32_unknown_interrupt();
 448}
 449
 450static void ip32_irq2(void)
 451{
 452        ip32_unknown_interrupt();
 453}
 454
 455static void ip32_irq3(void)
 456{
 457        ip32_unknown_interrupt();
 458}
 459
 460static void ip32_irq4(void)
 461{
 462        ip32_unknown_interrupt();
 463}
 464
 465static void ip32_irq5(void)
 466{
 467        do_IRQ(MIPS_CPU_IRQ_BASE + 7);
 468}
 469
 470asmlinkage void plat_irq_dispatch(void)
 471{
 472        unsigned int pending = read_c0_status() & read_c0_cause();
 473
 474        if (likely(pending & IE_IRQ0))
 475                ip32_irq0();
 476        else if (unlikely(pending & IE_IRQ1))
 477                ip32_irq1();
 478        else if (unlikely(pending & IE_IRQ2))
 479                ip32_irq2();
 480        else if (unlikely(pending & IE_IRQ3))
 481                ip32_irq3();
 482        else if (unlikely(pending & IE_IRQ4))
 483                ip32_irq4();
 484        else if (likely(pending & IE_IRQ5))
 485                ip32_irq5();
 486}
 487
 488void __init arch_init_irq(void)
 489{
 490        unsigned int irq;
 491
 492        /* Install our interrupt handler, then clear and disable all
 493         * CRIME and MACE interrupts. */
 494        crime->imask = 0;
 495        crime->hard_int = 0;
 496        crime->soft_int = 0;
 497        mace->perif.ctrl.istat = 0;
 498        mace->perif.ctrl.imask = 0;
 499
 500        mips_cpu_irq_init();
 501        for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
 502                switch (irq) {
 503                case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
 504                        set_irq_chip_and_handler_name(irq,&ip32_mace_interrupt,
 505                                handle_level_irq, "level");
 506                        break;
 507
 508                case MACEPCI_SCSI0_IRQ ...  MACEPCI_SHARED2_IRQ:
 509                        set_irq_chip_and_handler_name(irq,
 510                                &ip32_macepci_interrupt, handle_level_irq,
 511                                "level");
 512                        break;
 513
 514                case CRIME_CPUERR_IRQ:
 515                case CRIME_MEMERR_IRQ:
 516                        set_irq_chip_and_handler_name(irq,
 517                                &crime_level_interrupt, handle_level_irq,
 518                                "level");
 519                        break;
 520
 521                case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
 522                case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
 523                case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
 524                case CRIME_VICE_IRQ:
 525                        set_irq_chip_and_handler_name(irq,
 526                                &crime_edge_interrupt, handle_edge_irq, "edge");
 527                        break;
 528
 529                case MACEISA_PARALLEL_IRQ:
 530                case MACEISA_SERIAL1_TDMAPR_IRQ:
 531                case MACEISA_SERIAL2_TDMAPR_IRQ:
 532                        set_irq_chip_and_handler_name(irq,
 533                                &ip32_maceisa_edge_interrupt, handle_edge_irq,
 534                                "edge");
 535                        break;
 536
 537                default:
 538                        set_irq_chip_and_handler_name(irq,
 539                                &ip32_maceisa_level_interrupt, handle_level_irq,
 540                                "level");
 541                        break;
 542                }
 543        }
 544        setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
 545        setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
 546
 547#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
 548        change_c0_status(ST0_IM, ALLINTS);
 549}
 550