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19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/string.h>
22#include <linux/init.h>
23#include <linux/bootmem.h>
24#include <linux/of_address.h>
25#include <linux/mm.h>
26#include <linux/list.h>
27#include <linux/syscalls.h>
28#include <linux/irq.h>
29#include <linux/vmalloc.h>
30#include <linux/slab.h>
31
32#include <asm/processor.h>
33#include <asm/io.h>
34#include <asm/prom.h>
35#include <asm/pci-bridge.h>
36#include <asm/byteorder.h>
37#include <asm/machdep.h>
38#include <asm/ppc-pci.h>
39#include <asm/firmware.h>
40#include <asm/eeh.h>
41
42static DEFINE_SPINLOCK(hose_spinlock);
43LIST_HEAD(hose_list);
44
45
46static int global_phb_number;
47
48
49resource_size_t isa_mem_base;
50
51
52unsigned int ppc_pci_flags = 0;
53
54
55static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
56
57void set_pci_dma_ops(struct dma_map_ops *dma_ops)
58{
59 pci_dma_ops = dma_ops;
60}
61
62struct dma_map_ops *get_pci_dma_ops(void)
63{
64 return pci_dma_ops;
65}
66EXPORT_SYMBOL(get_pci_dma_ops);
67
68struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
69{
70 struct pci_controller *phb;
71
72 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
73 if (phb == NULL)
74 return NULL;
75 spin_lock(&hose_spinlock);
76 phb->global_number = global_phb_number++;
77 list_add_tail(&phb->list_node, &hose_list);
78 spin_unlock(&hose_spinlock);
79 phb->dn = dev;
80 phb->is_dynamic = mem_init_done;
81#ifdef CONFIG_PPC64
82 if (dev) {
83 int nid = of_node_to_nid(dev);
84
85 if (nid < 0 || !node_online(nid))
86 nid = -1;
87
88 PHB_SET_NODE(phb, nid);
89 }
90#endif
91 return phb;
92}
93
94void pcibios_free_controller(struct pci_controller *phb)
95{
96 spin_lock(&hose_spinlock);
97 list_del(&phb->list_node);
98 spin_unlock(&hose_spinlock);
99
100 if (phb->is_dynamic)
101 kfree(phb);
102}
103
104static resource_size_t pcibios_io_size(const struct pci_controller *hose)
105{
106#ifdef CONFIG_PPC64
107 return hose->pci_io_size;
108#else
109 return hose->io_resource.end - hose->io_resource.start + 1;
110#endif
111}
112
113int pcibios_vaddr_is_ioport(void __iomem *address)
114{
115 int ret = 0;
116 struct pci_controller *hose;
117 resource_size_t size;
118
119 spin_lock(&hose_spinlock);
120 list_for_each_entry(hose, &hose_list, list_node) {
121 size = pcibios_io_size(hose);
122 if (address >= hose->io_base_virt &&
123 address < (hose->io_base_virt + size)) {
124 ret = 1;
125 break;
126 }
127 }
128 spin_unlock(&hose_spinlock);
129 return ret;
130}
131
132unsigned long pci_address_to_pio(phys_addr_t address)
133{
134 struct pci_controller *hose;
135 resource_size_t size;
136 unsigned long ret = ~0;
137
138 spin_lock(&hose_spinlock);
139 list_for_each_entry(hose, &hose_list, list_node) {
140 size = pcibios_io_size(hose);
141 if (address >= hose->io_base_phys &&
142 address < (hose->io_base_phys + size)) {
143 unsigned long base =
144 (unsigned long)hose->io_base_virt - _IO_BASE;
145 ret = base + (address - hose->io_base_phys);
146 break;
147 }
148 }
149 spin_unlock(&hose_spinlock);
150
151 return ret;
152}
153EXPORT_SYMBOL_GPL(pci_address_to_pio);
154
155
156
157
158int pci_domain_nr(struct pci_bus *bus)
159{
160 struct pci_controller *hose = pci_bus_to_host(bus);
161
162 return hose->global_number;
163}
164EXPORT_SYMBOL(pci_domain_nr);
165
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167
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170
171
172
173struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
174{
175 while(node) {
176 struct pci_controller *hose, *tmp;
177 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
178 if (hose->dn == node)
179 return hose;
180 node = node->parent;
181 }
182 return NULL;
183}
184
185static ssize_t pci_show_devspec(struct device *dev,
186 struct device_attribute *attr, char *buf)
187{
188 struct pci_dev *pdev;
189 struct device_node *np;
190
191 pdev = to_pci_dev (dev);
192 np = pci_device_to_OF_node(pdev);
193 if (np == NULL || np->full_name == NULL)
194 return 0;
195 return sprintf(buf, "%s", np->full_name);
196}
197static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
198
199
200int pcibios_add_platform_entries(struct pci_dev *pdev)
201{
202 return device_create_file(&pdev->dev, &dev_attr_devspec);
203}
204
205char __devinit *pcibios_setup(char *str)
206{
207 return str;
208}
209
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213
214
215int pci_read_irq_line(struct pci_dev *pci_dev)
216{
217 struct of_irq oirq;
218 unsigned int virq;
219
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228
229#ifdef CONFIG_PPC_ISERIES
230 if (firmware_has_feature(FW_FEATURE_ISERIES))
231 return -1;
232#endif
233
234 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
235
236#ifdef DEBUG
237 memset(&oirq, 0xff, sizeof(oirq));
238#endif
239
240 if (of_irq_map_pci(pci_dev, &oirq)) {
241 u8 line, pin;
242
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249
250 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
251 return -1;
252 if (pin == 0)
253 return -1;
254 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
255 line == 0xff || line == 0) {
256 return -1;
257 }
258 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
259 line, pin);
260
261 virq = irq_create_mapping(NULL, line);
262 if (virq != NO_IRQ)
263 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
264 } else {
265 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
266 oirq.size, oirq.specifier[0], oirq.specifier[1],
267 oirq.controller ? oirq.controller->full_name :
268 "<default>");
269
270 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
271 oirq.size);
272 }
273 if(virq == NO_IRQ) {
274 pr_debug(" Failed to map !\n");
275 return -1;
276 }
277
278 pr_debug(" Mapped to linux irq %d\n", virq);
279
280 pci_dev->irq = virq;
281
282 return 0;
283}
284EXPORT_SYMBOL(pci_read_irq_line);
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302
303static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
304 resource_size_t *offset,
305 enum pci_mmap_state mmap_state)
306{
307 struct pci_controller *hose = pci_bus_to_host(dev->bus);
308 unsigned long io_offset = 0;
309 int i, res_bit;
310
311 if (hose == 0)
312 return NULL;
313
314
315 if (mmap_state == pci_mmap_mem) {
316#if 0
317 *offset += hose->pci_mem_offset;
318#endif
319 res_bit = IORESOURCE_MEM;
320 } else {
321 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
322 *offset += io_offset;
323 res_bit = IORESOURCE_IO;
324 }
325
326
327
328
329
330 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
331 struct resource *rp = &dev->resource[i];
332 int flags = rp->flags;
333
334
335 if (i == PCI_ROM_RESOURCE)
336 flags |= IORESOURCE_MEM;
337
338
339 if ((flags & res_bit) == 0)
340 continue;
341
342
343 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
344 continue;
345
346
347 if (mmap_state == pci_mmap_io)
348 *offset += hose->io_base_phys - io_offset;
349 return rp;
350 }
351
352 return NULL;
353}
354
355
356
357
358
359static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
360 pgprot_t protection,
361 enum pci_mmap_state mmap_state,
362 int write_combine)
363{
364 unsigned long prot = pgprot_val(protection);
365
366
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368
369
370
371
372 if (mmap_state != pci_mmap_mem)
373 write_combine = 0;
374 else if (write_combine == 0) {
375 if (rp->flags & IORESOURCE_PREFETCH)
376 write_combine = 1;
377 }
378
379
380 if (write_combine)
381 return pgprot_noncached_wc(prot);
382 else
383 return pgprot_noncached(prot);
384}
385
386
387
388
389
390
391pgprot_t pci_phys_mem_access_prot(struct file *file,
392 unsigned long pfn,
393 unsigned long size,
394 pgprot_t prot)
395{
396 struct pci_dev *pdev = NULL;
397 struct resource *found = NULL;
398 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
399 int i;
400
401 if (page_is_ram(pfn))
402 return prot;
403
404 prot = pgprot_noncached(prot);
405 for_each_pci_dev(pdev) {
406 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
407 struct resource *rp = &pdev->resource[i];
408 int flags = rp->flags;
409
410
411 if ((flags & IORESOURCE_MEM) == 0)
412 continue;
413
414 if (offset < (rp->start & PAGE_MASK) ||
415 offset > rp->end)
416 continue;
417 found = rp;
418 break;
419 }
420 if (found)
421 break;
422 }
423 if (found) {
424 if (found->flags & IORESOURCE_PREFETCH)
425 prot = pgprot_noncached_wc(prot);
426 pci_dev_put(pdev);
427 }
428
429 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
430 (unsigned long long)offset, pgprot_val(prot));
431
432 return prot;
433}
434
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445
446int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
447 enum pci_mmap_state mmap_state, int write_combine)
448{
449 resource_size_t offset =
450 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
451 struct resource *rp;
452 int ret;
453
454 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
455 if (rp == NULL)
456 return -EINVAL;
457
458 vma->vm_pgoff = offset >> PAGE_SHIFT;
459 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
460 vma->vm_page_prot,
461 mmap_state, write_combine);
462
463 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
464 vma->vm_end - vma->vm_start, vma->vm_page_prot);
465
466 return ret;
467}
468
469
470int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
471{
472 unsigned long offset;
473 struct pci_controller *hose = pci_bus_to_host(bus);
474 struct resource *rp = &hose->io_resource;
475 void __iomem *addr;
476
477
478
479
480
481
482 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
483 offset += port;
484
485 if (!(rp->flags & IORESOURCE_IO))
486 return -ENXIO;
487 if (offset < rp->start || (offset + size) > rp->end)
488 return -ENXIO;
489 addr = hose->io_base_virt + port;
490
491 switch(size) {
492 case 1:
493 *((u8 *)val) = in_8(addr);
494 return 1;
495 case 2:
496 if (port & 1)
497 return -EINVAL;
498 *((u16 *)val) = in_le16(addr);
499 return 2;
500 case 4:
501 if (port & 3)
502 return -EINVAL;
503 *((u32 *)val) = in_le32(addr);
504 return 4;
505 }
506 return -EINVAL;
507}
508
509
510int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
511{
512 unsigned long offset;
513 struct pci_controller *hose = pci_bus_to_host(bus);
514 struct resource *rp = &hose->io_resource;
515 void __iomem *addr;
516
517
518
519
520
521
522 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
523 offset += port;
524
525 if (!(rp->flags & IORESOURCE_IO))
526 return -ENXIO;
527 if (offset < rp->start || (offset + size) > rp->end)
528 return -ENXIO;
529 addr = hose->io_base_virt + port;
530
531
532
533
534
535
536 switch(size) {
537 case 1:
538 out_8(addr, val >> 24);
539 return 1;
540 case 2:
541 if (port & 1)
542 return -EINVAL;
543 out_le16(addr, val >> 16);
544 return 2;
545 case 4:
546 if (port & 3)
547 return -EINVAL;
548 out_le32(addr, val);
549 return 4;
550 }
551 return -EINVAL;
552}
553
554
555int pci_mmap_legacy_page_range(struct pci_bus *bus,
556 struct vm_area_struct *vma,
557 enum pci_mmap_state mmap_state)
558{
559 struct pci_controller *hose = pci_bus_to_host(bus);
560 resource_size_t offset =
561 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
562 resource_size_t size = vma->vm_end - vma->vm_start;
563 struct resource *rp;
564
565 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
566 pci_domain_nr(bus), bus->number,
567 mmap_state == pci_mmap_mem ? "MEM" : "IO",
568 (unsigned long long)offset,
569 (unsigned long long)(offset + size - 1));
570
571 if (mmap_state == pci_mmap_mem) {
572
573
574
575
576
577
578
579 if ((offset + size) > hose->isa_mem_size) {
580 printk(KERN_DEBUG
581 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
582 current->comm, current->pid, pci_domain_nr(bus), bus->number);
583 if (vma->vm_flags & VM_SHARED)
584 return shmem_zero_setup(vma);
585 return 0;
586 }
587 offset += hose->isa_mem_phys;
588 } else {
589 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
590 unsigned long roffset = offset + io_offset;
591 rp = &hose->io_resource;
592 if (!(rp->flags & IORESOURCE_IO))
593 return -ENXIO;
594 if (roffset < rp->start || (roffset + size) > rp->end)
595 return -ENXIO;
596 offset += hose->io_base_phys;
597 }
598 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
599
600 vma->vm_pgoff = offset >> PAGE_SHIFT;
601 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
602 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
603 vma->vm_end - vma->vm_start,
604 vma->vm_page_prot);
605}
606
607void pci_resource_to_user(const struct pci_dev *dev, int bar,
608 const struct resource *rsrc,
609 resource_size_t *start, resource_size_t *end)
610{
611 struct pci_controller *hose = pci_bus_to_host(dev->bus);
612 resource_size_t offset = 0;
613
614 if (hose == NULL)
615 return;
616
617 if (rsrc->flags & IORESOURCE_IO)
618 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
619
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636
637#if 0
638 else if (rsrc->flags & IORESOURCE_MEM)
639 offset = hose->pci_mem_offset;
640#endif
641
642 *start = rsrc->start - offset;
643 *end = rsrc->end - offset;
644}
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679void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
680 struct device_node *dev,
681 int primary)
682{
683 const u32 *ranges;
684 int rlen;
685 int pna = of_n_addr_cells(dev);
686 int np = pna + 5;
687 int memno = 0, isa_hole = -1;
688 u32 pci_space;
689 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
690 unsigned long long isa_mb = 0;
691 struct resource *res;
692
693 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
694 dev->full_name, primary ? "(primary)" : "");
695
696
697 ranges = of_get_property(dev, "ranges", &rlen);
698 if (ranges == NULL)
699 return;
700
701
702 while ((rlen -= np * 4) >= 0) {
703
704 pci_space = ranges[0];
705 pci_addr = of_read_number(ranges + 1, 2);
706 cpu_addr = of_translate_address(dev, ranges + 3);
707 size = of_read_number(ranges + pna + 3, 2);
708 ranges += np;
709
710
711
712
713
714
715 if (cpu_addr == OF_BAD_ADDR || size == 0)
716 continue;
717
718
719 for (; rlen >= np * sizeof(u32);
720 ranges += np, rlen -= np * 4) {
721 if (ranges[0] != pci_space)
722 break;
723 pci_next = of_read_number(ranges + 1, 2);
724 cpu_next = of_translate_address(dev, ranges + 3);
725 if (pci_next != pci_addr + size ||
726 cpu_next != cpu_addr + size)
727 break;
728 size += of_read_number(ranges + pna + 3, 2);
729 }
730
731
732 res = NULL;
733 switch ((pci_space >> 24) & 0x3) {
734 case 1:
735 printk(KERN_INFO
736 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
737 cpu_addr, cpu_addr + size - 1, pci_addr);
738
739
740 if (hose->pci_io_size) {
741 printk(KERN_INFO
742 " \\--> Skipped (too many) !\n");
743 continue;
744 }
745#ifdef CONFIG_PPC32
746
747 if (size > 0x01000000)
748 size = 0x01000000;
749
750
751 hose->io_base_virt = ioremap(cpu_addr, size);
752
753
754 if (primary)
755 isa_io_base =
756 (unsigned long)hose->io_base_virt;
757#endif
758
759
760
761 hose->pci_io_size = pci_addr + size;
762 hose->io_base_phys = cpu_addr - pci_addr;
763
764
765 res = &hose->io_resource;
766 res->flags = IORESOURCE_IO;
767 res->start = pci_addr;
768 break;
769 case 2:
770 case 3:
771 printk(KERN_INFO
772 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
773 cpu_addr, cpu_addr + size - 1, pci_addr,
774 (pci_space & 0x40000000) ? "Prefetch" : "");
775
776
777 if (memno >= 3) {
778 printk(KERN_INFO
779 " \\--> Skipped (too many) !\n");
780 continue;
781 }
782
783 if (pci_addr == 0) {
784 isa_mb = cpu_addr;
785 isa_hole = memno;
786 if (primary || isa_mem_base == 0)
787 isa_mem_base = cpu_addr;
788 hose->isa_mem_phys = cpu_addr;
789 hose->isa_mem_size = size;
790 }
791
792
793
794
795
796 if (memno == 0 ||
797 (isa_hole >= 0 && pci_addr != 0 &&
798 hose->pci_mem_offset == isa_mb))
799 hose->pci_mem_offset = cpu_addr - pci_addr;
800 else if (pci_addr != 0 &&
801 hose->pci_mem_offset != cpu_addr - pci_addr) {
802 printk(KERN_INFO
803 " \\--> Skipped (offset mismatch) !\n");
804 continue;
805 }
806
807
808 res = &hose->mem_resources[memno++];
809 res->flags = IORESOURCE_MEM;
810 if (pci_space & 0x40000000)
811 res->flags |= IORESOURCE_PREFETCH;
812 res->start = cpu_addr;
813 break;
814 }
815 if (res != NULL) {
816 res->name = dev->full_name;
817 res->end = res->start + size - 1;
818 res->parent = NULL;
819 res->sibling = NULL;
820 res->child = NULL;
821 }
822 }
823
824
825
826
827
828 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
829 unsigned int next = isa_hole + 1;
830 printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb);
831 if (next < memno)
832 memmove(&hose->mem_resources[isa_hole],
833 &hose->mem_resources[next],
834 sizeof(struct resource) * (memno - next));
835 hose->mem_resources[--memno].flags = 0;
836 }
837}
838
839
840int pci_proc_domain(struct pci_bus *bus)
841{
842 struct pci_controller *hose = pci_bus_to_host(bus);
843
844 if (!(ppc_pci_flags & PPC_PCI_ENABLE_PROC_DOMAINS))
845 return 0;
846 if (ppc_pci_flags & PPC_PCI_COMPAT_DOMAIN_0)
847 return hose->global_number != 0;
848 return 1;
849}
850
851void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
852 struct resource *res)
853{
854 resource_size_t offset = 0, mask = (resource_size_t)-1;
855 struct pci_controller *hose = pci_bus_to_host(dev->bus);
856
857 if (!hose)
858 return;
859 if (res->flags & IORESOURCE_IO) {
860 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
861 mask = 0xffffffffu;
862 } else if (res->flags & IORESOURCE_MEM)
863 offset = hose->pci_mem_offset;
864
865 region->start = (res->start - offset) & mask;
866 region->end = (res->end - offset) & mask;
867}
868EXPORT_SYMBOL(pcibios_resource_to_bus);
869
870void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
871 struct pci_bus_region *region)
872{
873 resource_size_t offset = 0, mask = (resource_size_t)-1;
874 struct pci_controller *hose = pci_bus_to_host(dev->bus);
875
876 if (!hose)
877 return;
878 if (res->flags & IORESOURCE_IO) {
879 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
880 mask = 0xffffffffu;
881 } else if (res->flags & IORESOURCE_MEM)
882 offset = hose->pci_mem_offset;
883 res->start = (region->start + offset) & mask;
884 res->end = (region->end + offset) & mask;
885}
886EXPORT_SYMBOL(pcibios_bus_to_resource);
887
888
889static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
890{
891 struct pci_controller *hose = pci_bus_to_host(dev->bus);
892 resource_size_t offset = 0, mask = (resource_size_t)-1;
893
894 if (res->flags & IORESOURCE_IO) {
895 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
896 mask = 0xffffffffu;
897 } else if (res->flags & IORESOURCE_MEM)
898 offset = hose->pci_mem_offset;
899
900 res->start = (res->start + offset) & mask;
901 res->end = (res->end + offset) & mask;
902}
903
904
905
906
907
908static void __devinit pcibios_fixup_resources(struct pci_dev *dev)
909{
910 struct pci_controller *hose = pci_bus_to_host(dev->bus);
911 int i;
912
913 if (!hose) {
914 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
915 pci_name(dev));
916 return;
917 }
918 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
919 struct resource *res = dev->resource + i;
920 if (!res->flags)
921 continue;
922
923
924
925
926
927
928 if (res->start == 0 && !(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) {
929 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n",
930 pci_name(dev), i,
931 (unsigned long long)res->start,
932 (unsigned long long)res->end,
933 (unsigned int)res->flags);
934 res->end -= res->start;
935 res->start = 0;
936 res->flags |= IORESOURCE_UNSET;
937 continue;
938 }
939
940 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
941 pci_name(dev), i,
942 (unsigned long long)res->start,\
943 (unsigned long long)res->end,
944 (unsigned int)res->flags);
945
946 fixup_resource(res, dev);
947
948 pr_debug("PCI:%s %016llx-%016llx\n",
949 pci_name(dev),
950 (unsigned long long)res->start,
951 (unsigned long long)res->end);
952 }
953
954
955 if (ppc_md.pcibios_fixup_resources)
956 ppc_md.pcibios_fixup_resources(dev);
957}
958DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
959
960
961
962
963
964
965static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
966 struct resource *res)
967{
968 struct pci_controller *hose = pci_bus_to_host(bus);
969 struct pci_dev *dev = bus->self;
970 resource_size_t offset;
971 u16 command;
972 int i;
973
974
975 if (ppc_pci_flags & PPC_PCI_PROBE_ONLY)
976 return 0;
977
978
979 if (res->flags & IORESOURCE_MEM) {
980
981
982
983 if (res->start != hose->pci_mem_offset)
984 return 0;
985
986
987
988
989 pci_read_config_word(dev, PCI_COMMAND, &command);
990 if ((command & PCI_COMMAND_MEMORY) == 0)
991 return 1;
992
993
994
995
996
997 for (i = 0; i < 3; i++) {
998 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
999 hose->mem_resources[i].start == hose->pci_mem_offset)
1000 return 0;
1001 }
1002
1003
1004
1005
1006 return 1;
1007 } else {
1008
1009 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1010 if (((res->start - offset) & 0xfffffffful) != 0)
1011 return 0;
1012
1013
1014
1015
1016
1017
1018 pci_read_config_word(dev, PCI_COMMAND, &command);
1019 if (command & PCI_COMMAND_IO)
1020 return 0;
1021
1022
1023
1024
1025 return 1;
1026 }
1027}
1028
1029
1030static void __devinit pcibios_fixup_bridge(struct pci_bus *bus)
1031{
1032 struct resource *res;
1033 int i;
1034
1035 struct pci_dev *dev = bus->self;
1036
1037 pci_bus_for_each_resource(bus, res, i) {
1038 if (!res || !res->flags)
1039 continue;
1040 if (i >= 3 && bus->self->transparent)
1041 continue;
1042
1043 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
1044 pci_name(dev), i,
1045 (unsigned long long)res->start,\
1046 (unsigned long long)res->end,
1047 (unsigned int)res->flags);
1048
1049
1050 fixup_resource(res, dev);
1051
1052
1053
1054
1055 if (pcibios_uninitialized_bridge_resource(bus, res)) {
1056 res->flags = 0;
1057 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
1058 } else {
1059
1060 pr_debug("PCI:%s %016llx-%016llx\n",
1061 pci_name(dev),
1062 (unsigned long long)res->start,
1063 (unsigned long long)res->end);
1064 }
1065 }
1066}
1067
1068void __devinit pcibios_setup_bus_self(struct pci_bus *bus)
1069{
1070
1071 if (bus->self != NULL)
1072 pcibios_fixup_bridge(bus);
1073
1074
1075
1076
1077 if (ppc_md.pcibios_fixup_bus)
1078 ppc_md.pcibios_fixup_bus(bus);
1079
1080
1081 if (ppc_md.pci_dma_bus_setup)
1082 ppc_md.pci_dma_bus_setup(bus);
1083}
1084
1085void __devinit pcibios_setup_bus_devices(struct pci_bus *bus)
1086{
1087 struct pci_dev *dev;
1088
1089 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1090 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1091
1092 list_for_each_entry(dev, &bus->devices, bus_list) {
1093
1094
1095
1096 if (dev->is_added)
1097 continue;
1098
1099
1100 dev->dev.of_node = pci_device_to_OF_node(dev);
1101
1102
1103
1104
1105 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1106
1107
1108 set_dma_ops(&dev->dev, pci_dma_ops);
1109 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
1110
1111
1112 if (ppc_md.pci_dma_dev_setup)
1113 ppc_md.pci_dma_dev_setup(dev);
1114
1115
1116 pci_read_irq_line(dev);
1117 if (ppc_md.pci_irq_fixup)
1118 ppc_md.pci_irq_fixup(dev);
1119 }
1120}
1121
1122void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1123{
1124
1125
1126
1127
1128 if (bus->self != NULL)
1129 pci_read_bridge_bases(bus);
1130
1131
1132 pcibios_setup_bus_self(bus);
1133
1134
1135 pcibios_setup_bus_devices(bus);
1136}
1137EXPORT_SYMBOL(pcibios_fixup_bus);
1138
1139void __devinit pci_fixup_cardbus(struct pci_bus *bus)
1140{
1141
1142 pcibios_setup_bus_devices(bus);
1143}
1144
1145
1146static int skip_isa_ioresource_align(struct pci_dev *dev)
1147{
1148 if ((ppc_pci_flags & PPC_PCI_CAN_SKIP_ISA_ALIGN) &&
1149 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1150 return 1;
1151 return 0;
1152}
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1168 resource_size_t size, resource_size_t align)
1169{
1170 struct pci_dev *dev = data;
1171 resource_size_t start = res->start;
1172
1173 if (res->flags & IORESOURCE_IO) {
1174 if (skip_isa_ioresource_align(dev))
1175 return start;
1176 if (start & 0x300)
1177 start = (start + 0x3ff) & ~0x3ff;
1178 }
1179
1180 return start;
1181}
1182EXPORT_SYMBOL(pcibios_align_resource);
1183
1184
1185
1186
1187
1188static int reparent_resources(struct resource *parent,
1189 struct resource *res)
1190{
1191 struct resource *p, **pp;
1192 struct resource **firstpp = NULL;
1193
1194 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1195 if (p->end < res->start)
1196 continue;
1197 if (res->end < p->start)
1198 break;
1199 if (p->start < res->start || p->end > res->end)
1200 return -1;
1201 if (firstpp == NULL)
1202 firstpp = pp;
1203 }
1204 if (firstpp == NULL)
1205 return -1;
1206 res->parent = parent;
1207 res->child = *firstpp;
1208 res->sibling = *pp;
1209 *firstpp = res;
1210 *pp = NULL;
1211 for (p = res->child; p != NULL; p = p->sibling) {
1212 p->parent = res;
1213 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1214 p->name,
1215 (unsigned long long)p->start,
1216 (unsigned long long)p->end, res->name);
1217 }
1218 return 0;
1219}
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254void pcibios_allocate_bus_resources(struct pci_bus *bus)
1255{
1256 struct pci_bus *b;
1257 int i;
1258 struct resource *res, *pr;
1259
1260 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1261 pci_domain_nr(bus), bus->number);
1262
1263 pci_bus_for_each_resource(bus, res, i) {
1264 if (!res || !res->flags || res->start > res->end || res->parent)
1265 continue;
1266 if (bus->parent == NULL)
1267 pr = (res->flags & IORESOURCE_IO) ?
1268 &ioport_resource : &iomem_resource;
1269 else {
1270
1271
1272
1273
1274
1275
1276 if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)
1277 goto clear_resource;
1278 pr = pci_find_parent_resource(bus->self, res);
1279 if (pr == res) {
1280
1281
1282
1283
1284 continue;
1285 }
1286 }
1287
1288 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1289 "[0x%x], parent %p (%s)\n",
1290 bus->self ? pci_name(bus->self) : "PHB",
1291 bus->number, i,
1292 (unsigned long long)res->start,
1293 (unsigned long long)res->end,
1294 (unsigned int)res->flags,
1295 pr, (pr && pr->name) ? pr->name : "nil");
1296
1297 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1298 if (request_resource(pr, res) == 0)
1299 continue;
1300
1301
1302
1303
1304
1305 if (reparent_resources(pr, res) == 0)
1306 continue;
1307 }
1308 printk(KERN_WARNING "PCI: Cannot allocate resource region "
1309 "%d of PCI bridge %d, will remap\n", i, bus->number);
1310clear_resource:
1311 res->start = res->end = 0;
1312 res->flags = 0;
1313 }
1314
1315 list_for_each_entry(b, &bus->children, node)
1316 pcibios_allocate_bus_resources(b);
1317}
1318
1319static inline void __devinit alloc_resource(struct pci_dev *dev, int idx)
1320{
1321 struct resource *pr, *r = &dev->resource[idx];
1322
1323 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1324 pci_name(dev), idx,
1325 (unsigned long long)r->start,
1326 (unsigned long long)r->end,
1327 (unsigned int)r->flags);
1328
1329 pr = pci_find_parent_resource(dev, r);
1330 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1331 request_resource(pr, r) < 0) {
1332 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1333 " of device %s, will remap\n", idx, pci_name(dev));
1334 if (pr)
1335 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1336 pr,
1337 (unsigned long long)pr->start,
1338 (unsigned long long)pr->end,
1339 (unsigned int)pr->flags);
1340
1341 r->flags |= IORESOURCE_UNSET;
1342 r->end -= r->start;
1343 r->start = 0;
1344 }
1345}
1346
1347static void __init pcibios_allocate_resources(int pass)
1348{
1349 struct pci_dev *dev = NULL;
1350 int idx, disabled;
1351 u16 command;
1352 struct resource *r;
1353
1354 for_each_pci_dev(dev) {
1355 pci_read_config_word(dev, PCI_COMMAND, &command);
1356 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1357 r = &dev->resource[idx];
1358 if (r->parent)
1359 continue;
1360 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1361 continue;
1362
1363
1364
1365 if (idx == PCI_ROM_RESOURCE )
1366 disabled = 1;
1367 if (r->flags & IORESOURCE_IO)
1368 disabled = !(command & PCI_COMMAND_IO);
1369 else
1370 disabled = !(command & PCI_COMMAND_MEMORY);
1371 if (pass == disabled)
1372 alloc_resource(dev, idx);
1373 }
1374 if (pass)
1375 continue;
1376 r = &dev->resource[PCI_ROM_RESOURCE];
1377 if (r->flags) {
1378
1379
1380
1381 u32 reg;
1382 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1383 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1384 pr_debug("PCI: Switching off ROM of %s\n",
1385 pci_name(dev));
1386 r->flags &= ~IORESOURCE_ROM_ENABLE;
1387 pci_write_config_dword(dev, dev->rom_base_reg,
1388 reg & ~PCI_ROM_ADDRESS_ENABLE);
1389 }
1390 }
1391 }
1392}
1393
1394static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1395{
1396 struct pci_controller *hose = pci_bus_to_host(bus);
1397 resource_size_t offset;
1398 struct resource *res, *pres;
1399 int i;
1400
1401 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1402
1403
1404 if (!(hose->io_resource.flags & IORESOURCE_IO))
1405 goto no_io;
1406 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1407 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1408 BUG_ON(res == NULL);
1409 res->name = "Legacy IO";
1410 res->flags = IORESOURCE_IO;
1411 res->start = offset;
1412 res->end = (offset + 0xfff) & 0xfffffffful;
1413 pr_debug("Candidate legacy IO: %pR\n", res);
1414 if (request_resource(&hose->io_resource, res)) {
1415 printk(KERN_DEBUG
1416 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1417 pci_domain_nr(bus), bus->number, res);
1418 kfree(res);
1419 }
1420
1421 no_io:
1422
1423 offset = hose->pci_mem_offset;
1424 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
1425 for (i = 0; i < 3; i++) {
1426 pres = &hose->mem_resources[i];
1427 if (!(pres->flags & IORESOURCE_MEM))
1428 continue;
1429 pr_debug("hose mem res: %pR\n", pres);
1430 if ((pres->start - offset) <= 0xa0000 &&
1431 (pres->end - offset) >= 0xbffff)
1432 break;
1433 }
1434 if (i >= 3)
1435 return;
1436 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1437 BUG_ON(res == NULL);
1438 res->name = "Legacy VGA memory";
1439 res->flags = IORESOURCE_MEM;
1440 res->start = 0xa0000 + offset;
1441 res->end = 0xbffff + offset;
1442 pr_debug("Candidate VGA memory: %pR\n", res);
1443 if (request_resource(pres, res)) {
1444 printk(KERN_DEBUG
1445 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1446 pci_domain_nr(bus), bus->number, res);
1447 kfree(res);
1448 }
1449}
1450
1451void __init pcibios_resource_survey(void)
1452{
1453 struct pci_bus *b;
1454
1455
1456
1457
1458 list_for_each_entry(b, &pci_root_buses, node)
1459 pcibios_allocate_bus_resources(b);
1460
1461 if (!(ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)) {
1462 pcibios_allocate_resources(0);
1463 pcibios_allocate_resources(1);
1464 }
1465
1466
1467
1468
1469
1470 if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) {
1471 list_for_each_entry(b, &pci_root_buses, node)
1472 pcibios_reserve_legacy_regions(b);
1473 }
1474
1475
1476
1477
1478 if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) {
1479 pr_debug("PCI: Assigning unassigned resources...\n");
1480 pci_assign_unassigned_resources();
1481 }
1482
1483
1484 if (ppc_md.pcibios_fixup)
1485 ppc_md.pcibios_fixup();
1486}
1487
1488#ifdef CONFIG_HOTPLUG
1489
1490
1491
1492
1493
1494
1495void pcibios_claim_one_bus(struct pci_bus *bus)
1496{
1497 struct pci_dev *dev;
1498 struct pci_bus *child_bus;
1499
1500 list_for_each_entry(dev, &bus->devices, bus_list) {
1501 int i;
1502
1503 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1504 struct resource *r = &dev->resource[i];
1505
1506 if (r->parent || !r->start || !r->flags)
1507 continue;
1508
1509 pr_debug("PCI: Claiming %s: "
1510 "Resource %d: %016llx..%016llx [%x]\n",
1511 pci_name(dev), i,
1512 (unsigned long long)r->start,
1513 (unsigned long long)r->end,
1514 (unsigned int)r->flags);
1515
1516 pci_claim_resource(dev, i);
1517 }
1518 }
1519
1520 list_for_each_entry(child_bus, &bus->children, node)
1521 pcibios_claim_one_bus(child_bus);
1522}
1523
1524
1525
1526
1527
1528
1529
1530
1531void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1532{
1533 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1534 pci_domain_nr(bus), bus->number);
1535
1536
1537 pcibios_allocate_bus_resources(bus);
1538 pcibios_claim_one_bus(bus);
1539
1540
1541 pci_bus_add_devices(bus);
1542
1543
1544 eeh_add_device_tree_late(bus);
1545}
1546EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1547
1548#endif
1549
1550int pcibios_enable_device(struct pci_dev *dev, int mask)
1551{
1552 if (ppc_md.pcibios_enable_device_hook)
1553 if (ppc_md.pcibios_enable_device_hook(dev))
1554 return -EINVAL;
1555
1556 return pci_enable_resources(dev, mask);
1557}
1558
1559void __devinit pcibios_setup_phb_resources(struct pci_controller *hose)
1560{
1561 struct pci_bus *bus = hose->bus;
1562 struct resource *res;
1563 int i;
1564
1565
1566 bus->resource[0] = res = &hose->io_resource;
1567
1568 if (!res->flags) {
1569 printk(KERN_WARNING "PCI: I/O resource not set for host"
1570 " bridge %s (domain %d)\n",
1571 hose->dn->full_name, hose->global_number);
1572#ifdef CONFIG_PPC32
1573
1574 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1575 res->end = res->start + IO_SPACE_LIMIT;
1576 res->flags = IORESOURCE_IO;
1577#endif
1578 }
1579
1580 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1581 (unsigned long long)res->start,
1582 (unsigned long long)res->end,
1583 (unsigned long)res->flags);
1584
1585
1586 for (i = 0; i < 3; ++i) {
1587 res = &hose->mem_resources[i];
1588 if (!res->flags) {
1589 if (i > 0)
1590 continue;
1591 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1592 "host bridge %s (domain %d)\n",
1593 hose->dn->full_name, hose->global_number);
1594#ifdef CONFIG_PPC32
1595
1596 res->start = hose->pci_mem_offset;
1597 res->end = (resource_size_t)-1LL;
1598 res->flags = IORESOURCE_MEM;
1599#endif
1600 }
1601 bus->resource[i+1] = res;
1602
1603 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i,
1604 (unsigned long long)res->start,
1605 (unsigned long long)res->end,
1606 (unsigned long)res->flags);
1607 }
1608
1609 pr_debug("PCI: PHB MEM offset = %016llx\n",
1610 (unsigned long long)hose->pci_mem_offset);
1611 pr_debug("PCI: PHB IO offset = %08lx\n",
1612 (unsigned long)hose->io_base_virt - _IO_BASE);
1613
1614}
1615
1616
1617
1618
1619
1620#define NULL_PCI_OP(rw, size, type) \
1621static int \
1622null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1623{ \
1624 return PCIBIOS_DEVICE_NOT_FOUND; \
1625}
1626
1627static int
1628null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1629 int len, u32 *val)
1630{
1631 return PCIBIOS_DEVICE_NOT_FOUND;
1632}
1633
1634static int
1635null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1636 int len, u32 val)
1637{
1638 return PCIBIOS_DEVICE_NOT_FOUND;
1639}
1640
1641static struct pci_ops null_pci_ops =
1642{
1643 .read = null_read_config,
1644 .write = null_write_config,
1645};
1646
1647
1648
1649
1650
1651static struct pci_bus *
1652fake_pci_bus(struct pci_controller *hose, int busnr)
1653{
1654 static struct pci_bus bus;
1655
1656 if (hose == 0) {
1657 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1658 }
1659 bus.number = busnr;
1660 bus.sysdata = hose;
1661 bus.ops = hose? hose->ops: &null_pci_ops;
1662 return &bus;
1663}
1664
1665#define EARLY_PCI_OP(rw, size, type) \
1666int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1667 int devfn, int offset, type value) \
1668{ \
1669 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1670 devfn, offset, value); \
1671}
1672
1673EARLY_PCI_OP(read, byte, u8 *)
1674EARLY_PCI_OP(read, word, u16 *)
1675EARLY_PCI_OP(read, dword, u32 *)
1676EARLY_PCI_OP(write, byte, u8)
1677EARLY_PCI_OP(write, word, u16)
1678EARLY_PCI_OP(write, dword, u32)
1679
1680extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
1681int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1682 int cap)
1683{
1684 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1685}
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696void __devinit pcibios_scan_phb(struct pci_controller *hose, void *sysdata)
1697{
1698 struct pci_bus *bus;
1699 struct device_node *node = hose->dn;
1700 int mode;
1701
1702 pr_debug("PCI: Scanning PHB %s\n",
1703 node ? node->full_name : "<NO NAME>");
1704
1705
1706 bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops,
1707 sysdata);
1708 if (bus == NULL) {
1709 pr_err("Failed to create bus for PCI domain %04x\n",
1710 hose->global_number);
1711 return;
1712 }
1713 bus->secondary = hose->first_busno;
1714 hose->bus = bus;
1715
1716
1717 pcibios_setup_phb_io_space(hose);
1718
1719
1720 pcibios_setup_phb_resources(hose);
1721
1722
1723 mode = PCI_PROBE_NORMAL;
1724 if (node && ppc_md.pci_probe_mode)
1725 mode = ppc_md.pci_probe_mode(bus);
1726 pr_debug(" probe mode: %d\n", mode);
1727 if (mode == PCI_PROBE_DEVTREE) {
1728 bus->subordinate = hose->last_busno;
1729 of_scan_bus(node, bus);
1730 }
1731
1732 if (mode == PCI_PROBE_NORMAL)
1733 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
1734}
1735