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9#include <asm/processor.h>
10#include <asm/ppc_asm.h>
11#include <asm/asm-offsets.h>
12
13 .section ".toc","aw"
14PPC64_CACHES:
15 .tc ppc64_caches[TC],ppc64_caches
16 .section ".text"
17
18
19_GLOBAL(copy_4K_page)
20 li r5,4096
21BEGIN_FTR_SECTION
22 ld r10,PPC64_CACHES@toc(r2)
23 lwz r11,DCACHEL1LOGLINESIZE(r10)
24 lwz r12,DCACHEL1LINESIZE(r10)
25 li r9,0
26 srd r8,r5,r11
27
28 mtctr r8
29.Lsetup:
30 dcbt r9,r4
31 dcbz r9,r3
32 add r9,r9,r12
33 bdnz .Lsetup
34END_FTR_SECTION_IFSET(CPU_FTR_CP_USE_DCBTZ)
35 addi r3,r3,-8
36 srdi r8,r5,7
37 addi r8,r8,-1
38
39 mtctr r8
40
41 ld r5,0(r4)
42 ld r6,8(r4)
43 ld r7,16(r4)
44 ldu r8,24(r4)
451: std r5,8(r3)
46 std r6,16(r3)
47 ld r9,8(r4)
48 ld r10,16(r4)
49 std r7,24(r3)
50 std r8,32(r3)
51 ld r11,24(r4)
52 ld r12,32(r4)
53 std r9,40(r3)
54 std r10,48(r3)
55 ld r5,40(r4)
56 ld r6,48(r4)
57 std r11,56(r3)
58 std r12,64(r3)
59 ld r7,56(r4)
60 ld r8,64(r4)
61 std r5,72(r3)
62 std r6,80(r3)
63 ld r9,72(r4)
64 ld r10,80(r4)
65 std r7,88(r3)
66 std r8,96(r3)
67 ld r11,88(r4)
68 ld r12,96(r4)
69 std r9,104(r3)
70 std r10,112(r3)
71 ld r5,104(r4)
72 ld r6,112(r4)
73 std r11,120(r3)
74 stdu r12,128(r3)
75 ld r7,120(r4)
76 ldu r8,128(r4)
77 bdnz 1b
78
79 std r5,8(r3)
80 std r6,16(r3)
81 ld r9,8(r4)
82 ld r10,16(r4)
83 std r7,24(r3)
84 std r8,32(r3)
85 ld r11,24(r4)
86 ld r12,32(r4)
87 std r9,40(r3)
88 std r10,48(r3)
89 ld r5,40(r4)
90 ld r6,48(r4)
91 std r11,56(r3)
92 std r12,64(r3)
93 ld r7,56(r4)
94 ld r8,64(r4)
95 std r5,72(r3)
96 std r6,80(r3)
97 ld r9,72(r4)
98 ld r10,80(r4)
99 std r7,88(r3)
100 std r8,96(r3)
101 ld r11,88(r4)
102 ld r12,96(r4)
103 std r9,104(r3)
104 std r10,112(r3)
105 std r11,120(r3)
106 std r12,128(r3)
107 blr
108