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21#undef DEBUG
22#undef DEBUG_LOW
23
24#include <linux/spinlock.h>
25#include <linux/errno.h>
26#include <linux/sched.h>
27#include <linux/proc_fs.h>
28#include <linux/stat.h>
29#include <linux/sysctl.h>
30#include <linux/ctype.h>
31#include <linux/cache.h>
32#include <linux/init.h>
33#include <linux/signal.h>
34#include <linux/memblock.h>
35
36#include <asm/processor.h>
37#include <asm/pgtable.h>
38#include <asm/mmu.h>
39#include <asm/mmu_context.h>
40#include <asm/page.h>
41#include <asm/types.h>
42#include <asm/system.h>
43#include <asm/uaccess.h>
44#include <asm/machdep.h>
45#include <asm/prom.h>
46#include <asm/abs_addr.h>
47#include <asm/tlbflush.h>
48#include <asm/io.h>
49#include <asm/eeh.h>
50#include <asm/tlb.h>
51#include <asm/cacheflush.h>
52#include <asm/cputable.h>
53#include <asm/sections.h>
54#include <asm/spu.h>
55#include <asm/udbg.h>
56
57#ifdef DEBUG
58#define DBG(fmt...) udbg_printf(fmt)
59#else
60#define DBG(fmt...)
61#endif
62
63#ifdef DEBUG_LOW
64#define DBG_LOW(fmt...) udbg_printf(fmt)
65#else
66#define DBG_LOW(fmt...)
67#endif
68
69#define KB (1024)
70#define MB (1024*KB)
71#define GB (1024L*MB)
72
73
74
75
76
77
78
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82
83
84
85#ifdef CONFIG_U3_DART
86extern unsigned long dart_tablebase;
87#endif
88
89static unsigned long _SDR1;
90struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
91
92struct hash_pte *htab_address;
93unsigned long htab_size_bytes;
94unsigned long htab_hash_mask;
95EXPORT_SYMBOL_GPL(htab_hash_mask);
96int mmu_linear_psize = MMU_PAGE_4K;
97int mmu_virtual_psize = MMU_PAGE_4K;
98int mmu_vmalloc_psize = MMU_PAGE_4K;
99#ifdef CONFIG_SPARSEMEM_VMEMMAP
100int mmu_vmemmap_psize = MMU_PAGE_4K;
101#endif
102int mmu_io_psize = MMU_PAGE_4K;
103int mmu_kernel_ssize = MMU_SEGSIZE_256M;
104int mmu_highuser_ssize = MMU_SEGSIZE_256M;
105u16 mmu_slb_size = 64;
106EXPORT_SYMBOL_GPL(mmu_slb_size);
107#ifdef CONFIG_HUGETLB_PAGE
108unsigned int HPAGE_SHIFT;
109#endif
110#ifdef CONFIG_PPC_64K_PAGES
111int mmu_ci_restrictions;
112#endif
113#ifdef CONFIG_DEBUG_PAGEALLOC
114static u8 *linear_map_hash_slots;
115static unsigned long linear_map_hash_count;
116static DEFINE_SPINLOCK(linear_map_hash_lock);
117#endif
118
119
120
121
122
123
124
125static struct mmu_psize_def mmu_psize_defaults_old[] = {
126 [MMU_PAGE_4K] = {
127 .shift = 12,
128 .sllp = 0,
129 .penc = 0,
130 .avpnm = 0,
131 .tlbiel = 0,
132 },
133};
134
135
136
137
138
139static struct mmu_psize_def mmu_psize_defaults_gp[] = {
140 [MMU_PAGE_4K] = {
141 .shift = 12,
142 .sllp = 0,
143 .penc = 0,
144 .avpnm = 0,
145 .tlbiel = 1,
146 },
147 [MMU_PAGE_16M] = {
148 .shift = 24,
149 .sllp = SLB_VSID_L,
150 .penc = 0,
151 .avpnm = 0x1UL,
152 .tlbiel = 0,
153 },
154};
155
156static unsigned long htab_convert_pte_flags(unsigned long pteflags)
157{
158 unsigned long rflags = pteflags & 0x1fa;
159
160
161 if ((pteflags & _PAGE_EXEC) == 0)
162 rflags |= HPTE_R_N;
163
164
165
166
167 if ((pteflags & _PAGE_USER) && !((pteflags & _PAGE_RW) &&
168 (pteflags & _PAGE_DIRTY)))
169 rflags |= 1;
170
171
172 return rflags | HPTE_R_C;
173}
174
175int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
176 unsigned long pstart, unsigned long prot,
177 int psize, int ssize)
178{
179 unsigned long vaddr, paddr;
180 unsigned int step, shift;
181 int ret = 0;
182
183 shift = mmu_psize_defs[psize].shift;
184 step = 1 << shift;
185
186 prot = htab_convert_pte_flags(prot);
187
188 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
189 vstart, vend, pstart, prot, psize, ssize);
190
191 for (vaddr = vstart, paddr = pstart; vaddr < vend;
192 vaddr += step, paddr += step) {
193 unsigned long hash, hpteg;
194 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
195 unsigned long va = hpt_va(vaddr, vsid, ssize);
196 unsigned long tprot = prot;
197
198
199 if (overlaps_kernel_text(vaddr, vaddr + step))
200 tprot &= ~HPTE_R_N;
201
202 hash = hpt_hash(va, shift, ssize);
203 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
204
205 BUG_ON(!ppc_md.hpte_insert);
206 ret = ppc_md.hpte_insert(hpteg, va, paddr, tprot,
207 HPTE_V_BOLTED, psize, ssize);
208
209 if (ret < 0)
210 break;
211#ifdef CONFIG_DEBUG_PAGEALLOC
212 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
213 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
214#endif
215 }
216 return ret < 0 ? ret : 0;
217}
218
219#ifdef CONFIG_MEMORY_HOTPLUG
220static int htab_remove_mapping(unsigned long vstart, unsigned long vend,
221 int psize, int ssize)
222{
223 unsigned long vaddr;
224 unsigned int step, shift;
225
226 shift = mmu_psize_defs[psize].shift;
227 step = 1 << shift;
228
229 if (!ppc_md.hpte_removebolted) {
230 printk(KERN_WARNING "Platform doesn't implement "
231 "hpte_removebolted\n");
232 return -EINVAL;
233 }
234
235 for (vaddr = vstart; vaddr < vend; vaddr += step)
236 ppc_md.hpte_removebolted(vaddr, psize, ssize);
237
238 return 0;
239}
240#endif
241
242static int __init htab_dt_scan_seg_sizes(unsigned long node,
243 const char *uname, int depth,
244 void *data)
245{
246 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
247 u32 *prop;
248 unsigned long size = 0;
249
250
251 if (type == NULL || strcmp(type, "cpu") != 0)
252 return 0;
253
254 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes",
255 &size);
256 if (prop == NULL)
257 return 0;
258 for (; size >= 4; size -= 4, ++prop) {
259 if (prop[0] == 40) {
260 DBG("1T segment support detected\n");
261 cur_cpu_spec->cpu_features |= CPU_FTR_1T_SEGMENT;
262 return 1;
263 }
264 }
265 cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B;
266 return 0;
267}
268
269static void __init htab_init_seg_sizes(void)
270{
271 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
272}
273
274static int __init htab_dt_scan_page_sizes(unsigned long node,
275 const char *uname, int depth,
276 void *data)
277{
278 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
279 u32 *prop;
280 unsigned long size = 0;
281
282
283 if (type == NULL || strcmp(type, "cpu") != 0)
284 return 0;
285
286 prop = (u32 *)of_get_flat_dt_prop(node,
287 "ibm,segment-page-sizes", &size);
288 if (prop != NULL) {
289 DBG("Page sizes from device-tree:\n");
290 size /= 4;
291 cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE);
292 while(size > 0) {
293 unsigned int shift = prop[0];
294 unsigned int slbenc = prop[1];
295 unsigned int lpnum = prop[2];
296 unsigned int lpenc = 0;
297 struct mmu_psize_def *def;
298 int idx = -1;
299
300 size -= 3; prop += 3;
301 while(size > 0 && lpnum) {
302 if (prop[0] == shift)
303 lpenc = prop[1];
304 prop += 2; size -= 2;
305 lpnum--;
306 }
307 switch(shift) {
308 case 0xc:
309 idx = MMU_PAGE_4K;
310 break;
311 case 0x10:
312 idx = MMU_PAGE_64K;
313 break;
314 case 0x14:
315 idx = MMU_PAGE_1M;
316 break;
317 case 0x18:
318 idx = MMU_PAGE_16M;
319 cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE;
320 break;
321 case 0x22:
322 idx = MMU_PAGE_16G;
323 break;
324 }
325 if (idx < 0)
326 continue;
327 def = &mmu_psize_defs[idx];
328 def->shift = shift;
329 if (shift <= 23)
330 def->avpnm = 0;
331 else
332 def->avpnm = (1 << (shift - 23)) - 1;
333 def->sllp = slbenc;
334 def->penc = lpenc;
335
336
337
338 if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
339 def->tlbiel = 1;
340 else
341 def->tlbiel = 0;
342
343 DBG(" %d: shift=%02x, sllp=%04lx, avpnm=%08lx, "
344 "tlbiel=%d, penc=%d\n",
345 idx, shift, def->sllp, def->avpnm, def->tlbiel,
346 def->penc);
347 }
348 return 1;
349 }
350 return 0;
351}
352
353#ifdef CONFIG_HUGETLB_PAGE
354
355
356
357static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
358 const char *uname, int depth,
359 void *data) {
360 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
361 unsigned long *addr_prop;
362 u32 *page_count_prop;
363 unsigned int expected_pages;
364 long unsigned int phys_addr;
365 long unsigned int block_size;
366
367
368 if (type == NULL || strcmp(type, "memory") != 0)
369 return 0;
370
371
372
373 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
374 if (page_count_prop == NULL)
375 return 0;
376 expected_pages = (1 << page_count_prop[0]);
377 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
378 if (addr_prop == NULL)
379 return 0;
380 phys_addr = addr_prop[0];
381 block_size = addr_prop[1];
382 if (block_size != (16 * GB))
383 return 0;
384 printk(KERN_INFO "Huge page(16GB) memory: "
385 "addr = 0x%lX size = 0x%lX pages = %d\n",
386 phys_addr, block_size, expected_pages);
387 if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) {
388 memblock_reserve(phys_addr, block_size * expected_pages);
389 add_gpage(phys_addr, block_size, expected_pages);
390 }
391 return 0;
392}
393#endif
394
395static void __init htab_init_page_sizes(void)
396{
397 int rc;
398
399
400 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
401 sizeof(mmu_psize_defaults_old));
402
403
404
405
406 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
407 if (rc != 0)
408 goto found;
409
410
411
412
413
414 if (cpu_has_feature(CPU_FTR_16M_PAGE))
415 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
416 sizeof(mmu_psize_defaults_gp));
417 found:
418#ifndef CONFIG_DEBUG_PAGEALLOC
419
420
421
422
423 if (mmu_psize_defs[MMU_PAGE_16M].shift)
424 mmu_linear_psize = MMU_PAGE_16M;
425 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
426 mmu_linear_psize = MMU_PAGE_1M;
427#endif
428
429#ifdef CONFIG_PPC_64K_PAGES
430
431
432
433
434
435
436
437
438
439 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
440 mmu_virtual_psize = MMU_PAGE_64K;
441 mmu_vmalloc_psize = MMU_PAGE_64K;
442 if (mmu_linear_psize == MMU_PAGE_4K)
443 mmu_linear_psize = MMU_PAGE_64K;
444 if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE)) {
445
446
447
448
449 if (!machine_is(pseries))
450 mmu_io_psize = MMU_PAGE_64K;
451 } else
452 mmu_ci_restrictions = 1;
453 }
454#endif
455
456#ifdef CONFIG_SPARSEMEM_VMEMMAP
457
458
459
460 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
461 memblock_phys_mem_size() >= 0x40000000)
462 mmu_vmemmap_psize = MMU_PAGE_16M;
463 else if (mmu_psize_defs[MMU_PAGE_64K].shift)
464 mmu_vmemmap_psize = MMU_PAGE_64K;
465 else
466 mmu_vmemmap_psize = MMU_PAGE_4K;
467#endif
468
469 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
470 "virtual = %d, io = %d"
471#ifdef CONFIG_SPARSEMEM_VMEMMAP
472 ", vmemmap = %d"
473#endif
474 "\n",
475 mmu_psize_defs[mmu_linear_psize].shift,
476 mmu_psize_defs[mmu_virtual_psize].shift,
477 mmu_psize_defs[mmu_io_psize].shift
478#ifdef CONFIG_SPARSEMEM_VMEMMAP
479 ,mmu_psize_defs[mmu_vmemmap_psize].shift
480#endif
481 );
482
483#ifdef CONFIG_HUGETLB_PAGE
484
485 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
486#endif
487}
488
489static int __init htab_dt_scan_pftsize(unsigned long node,
490 const char *uname, int depth,
491 void *data)
492{
493 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
494 u32 *prop;
495
496
497 if (type == NULL || strcmp(type, "cpu") != 0)
498 return 0;
499
500 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
501 if (prop != NULL) {
502
503 ppc64_pft_size = prop[1];
504 return 1;
505 }
506 return 0;
507}
508
509static unsigned long __init htab_get_table_size(void)
510{
511 unsigned long mem_size, rnd_mem_size, pteg_count, psize;
512
513
514
515
516
517 if (ppc64_pft_size == 0)
518 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
519 if (ppc64_pft_size)
520 return 1UL << ppc64_pft_size;
521
522
523 mem_size = memblock_phys_mem_size();
524 rnd_mem_size = 1UL << __ilog2(mem_size);
525 if (rnd_mem_size < mem_size)
526 rnd_mem_size <<= 1;
527
528
529 psize = mmu_psize_defs[mmu_virtual_psize].shift;
530 pteg_count = max(rnd_mem_size >> (psize + 1), 1UL << 11);
531
532 return pteg_count << 7;
533}
534
535#ifdef CONFIG_MEMORY_HOTPLUG
536void create_section_mapping(unsigned long start, unsigned long end)
537{
538 BUG_ON(htab_bolt_mapping(start, end, __pa(start),
539 pgprot_val(PAGE_KERNEL), mmu_linear_psize,
540 mmu_kernel_ssize));
541}
542
543int remove_section_mapping(unsigned long start, unsigned long end)
544{
545 return htab_remove_mapping(start, end, mmu_linear_psize,
546 mmu_kernel_ssize);
547}
548#endif
549
550static inline void make_bl(unsigned int *insn_addr, void *func)
551{
552 unsigned long funcp = *((unsigned long *)func);
553 int offset = funcp - (unsigned long)insn_addr;
554
555 *insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc));
556 flush_icache_range((unsigned long)insn_addr, 4+
557 (unsigned long)insn_addr);
558}
559
560static void __init htab_finish_init(void)
561{
562 extern unsigned int *htab_call_hpte_insert1;
563 extern unsigned int *htab_call_hpte_insert2;
564 extern unsigned int *htab_call_hpte_remove;
565 extern unsigned int *htab_call_hpte_updatepp;
566
567#ifdef CONFIG_PPC_HAS_HASH_64K
568 extern unsigned int *ht64_call_hpte_insert1;
569 extern unsigned int *ht64_call_hpte_insert2;
570 extern unsigned int *ht64_call_hpte_remove;
571 extern unsigned int *ht64_call_hpte_updatepp;
572
573 make_bl(ht64_call_hpte_insert1, ppc_md.hpte_insert);
574 make_bl(ht64_call_hpte_insert2, ppc_md.hpte_insert);
575 make_bl(ht64_call_hpte_remove, ppc_md.hpte_remove);
576 make_bl(ht64_call_hpte_updatepp, ppc_md.hpte_updatepp);
577#endif
578
579 make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert);
580 make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert);
581 make_bl(htab_call_hpte_remove, ppc_md.hpte_remove);
582 make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp);
583}
584
585static void __init htab_initialize(void)
586{
587 unsigned long table;
588 unsigned long pteg_count;
589 unsigned long prot;
590 unsigned long base = 0, size = 0, limit;
591 struct memblock_region *reg;
592
593 DBG(" -> htab_initialize()\n");
594
595
596 htab_init_seg_sizes();
597
598
599 htab_init_page_sizes();
600
601 if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) {
602 mmu_kernel_ssize = MMU_SEGSIZE_1T;
603 mmu_highuser_ssize = MMU_SEGSIZE_1T;
604 printk(KERN_INFO "Using 1TB segments\n");
605 }
606
607
608
609
610
611 htab_size_bytes = htab_get_table_size();
612 pteg_count = htab_size_bytes >> 7;
613
614 htab_hash_mask = pteg_count - 1;
615
616 if (firmware_has_feature(FW_FEATURE_LPAR)) {
617
618 htab_address = NULL;
619 _SDR1 = 0;
620 } else {
621
622
623
624
625 if (machine_is(cell))
626 limit = 0x80000000;
627 else
628 limit = MEMBLOCK_ALLOC_ANYWHERE;
629
630 table = memblock_alloc_base(htab_size_bytes, htab_size_bytes, limit);
631
632 DBG("Hash table allocated at %lx, size: %lx\n", table,
633 htab_size_bytes);
634
635 htab_address = abs_to_virt(table);
636
637
638 _SDR1 = table + __ilog2(pteg_count) - 11;
639
640
641 memset((void *)table, 0, htab_size_bytes);
642
643
644 mtspr(SPRN_SDR1, _SDR1);
645 }
646
647 prot = pgprot_val(PAGE_KERNEL);
648
649#ifdef CONFIG_DEBUG_PAGEALLOC
650 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
651 linear_map_hash_slots = __va(memblock_alloc_base(linear_map_hash_count,
652 1, ppc64_rma_size));
653 memset(linear_map_hash_slots, 0, linear_map_hash_count);
654#endif
655
656
657
658
659
660
661
662 for_each_memblock(memory, reg) {
663 base = (unsigned long)__va(reg->base);
664 size = reg->size;
665
666 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
667 base, size, prot);
668
669#ifdef CONFIG_U3_DART
670
671
672
673
674
675
676
677 DBG("DART base: %lx\n", dart_tablebase);
678
679 if (dart_tablebase != 0 && dart_tablebase >= base
680 && dart_tablebase < (base + size)) {
681 unsigned long dart_table_end = dart_tablebase + 16 * MB;
682 if (base != dart_tablebase)
683 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
684 __pa(base), prot,
685 mmu_linear_psize,
686 mmu_kernel_ssize));
687 if ((base + size) > dart_table_end)
688 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
689 base + size,
690 __pa(dart_table_end),
691 prot,
692 mmu_linear_psize,
693 mmu_kernel_ssize));
694 continue;
695 }
696#endif
697 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
698 prot, mmu_linear_psize, mmu_kernel_ssize));
699 }
700 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
701
702
703
704
705
706
707
708
709 if (tce_alloc_start) {
710 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
711 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
712
713 if (base + size >= tce_alloc_start)
714 tce_alloc_start = base + size + 1;
715
716 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
717 __pa(tce_alloc_start), prot,
718 mmu_linear_psize, mmu_kernel_ssize));
719 }
720
721 htab_finish_init();
722
723 DBG(" <- htab_initialize()\n");
724}
725#undef KB
726#undef MB
727
728void __init early_init_mmu(void)
729{
730
731 get_paca()->stab_real = __pa((u64)&initial_stab);
732 get_paca()->stab_addr = (u64)&initial_stab;
733
734
735
736
737
738 htab_initialize();
739
740
741
742 if (cpu_has_feature(CPU_FTR_SLB))
743 slb_initialize();
744 else if (!firmware_has_feature(FW_FEATURE_ISERIES))
745 stab_initialize(get_paca()->stab_real);
746}
747
748#ifdef CONFIG_SMP
749void __cpuinit early_init_mmu_secondary(void)
750{
751
752 if (!firmware_has_feature(FW_FEATURE_LPAR))
753 mtspr(SPRN_SDR1, _SDR1);
754
755
756
757
758
759 if (cpu_has_feature(CPU_FTR_SLB))
760 slb_initialize();
761 else
762 stab_initialize(get_paca()->stab_addr);
763}
764#endif
765
766
767
768
769unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
770{
771 struct page *page;
772
773 if (!pfn_valid(pte_pfn(pte)))
774 return pp;
775
776 page = pte_page(pte);
777
778
779 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
780 if (trap == 0x400) {
781 flush_dcache_icache_page(page);
782 set_bit(PG_arch_1, &page->flags);
783 } else
784 pp |= HPTE_R_N;
785 }
786 return pp;
787}
788
789#ifdef CONFIG_PPC_MM_SLICES
790unsigned int get_paca_psize(unsigned long addr)
791{
792 unsigned long index, slices;
793
794 if (addr < SLICE_LOW_TOP) {
795 slices = get_paca()->context.low_slices_psize;
796 index = GET_LOW_SLICE_INDEX(addr);
797 } else {
798 slices = get_paca()->context.high_slices_psize;
799 index = GET_HIGH_SLICE_INDEX(addr);
800 }
801 return (slices >> (index * 4)) & 0xF;
802}
803
804#else
805unsigned int get_paca_psize(unsigned long addr)
806{
807 return get_paca()->context.user_psize;
808}
809#endif
810
811
812
813
814
815#ifdef CONFIG_PPC_64K_PAGES
816void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
817{
818 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
819 return;
820 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
821#ifdef CONFIG_SPU_BASE
822 spu_flush_all_slbs(mm);
823#endif
824 if (get_paca_psize(addr) != MMU_PAGE_4K) {
825 get_paca()->context = mm->context;
826 slb_flush_and_rebolt();
827 }
828}
829#endif
830
831#ifdef CONFIG_PPC_SUBPAGE_PROT
832
833
834
835
836
837
838
839static int subpage_protection(struct mm_struct *mm, unsigned long ea)
840{
841 struct subpage_prot_table *spt = &mm->context.spt;
842 u32 spp = 0;
843 u32 **sbpm, *sbpp;
844
845 if (ea >= spt->maxaddr)
846 return 0;
847 if (ea < 0x100000000) {
848
849 sbpm = spt->low_prot;
850 } else {
851 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
852 if (!sbpm)
853 return 0;
854 }
855 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
856 if (!sbpp)
857 return 0;
858 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
859
860
861 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
862
863
864 spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0);
865 return spp;
866}
867
868#else
869static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
870{
871 return 0;
872}
873#endif
874
875void hash_failure_debug(unsigned long ea, unsigned long access,
876 unsigned long vsid, unsigned long trap,
877 int ssize, int psize, unsigned long pte)
878{
879 if (!printk_ratelimit())
880 return;
881 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
882 ea, access, current->comm);
883 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d psize=%d pte=0x%lx\n",
884 trap, vsid, ssize, psize, pte);
885}
886
887
888
889
890
891
892
893int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
894{
895 pgd_t *pgdir;
896 unsigned long vsid;
897 struct mm_struct *mm;
898 pte_t *ptep;
899 unsigned hugeshift;
900 const struct cpumask *tmp;
901 int rc, user_region = 0, local = 0;
902 int psize, ssize;
903
904 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
905 ea, access, trap);
906
907 if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) {
908 DBG_LOW(" out of pgtable range !\n");
909 return 1;
910 }
911
912
913 switch (REGION_ID(ea)) {
914 case USER_REGION_ID:
915 user_region = 1;
916 mm = current->mm;
917 if (! mm) {
918 DBG_LOW(" user region with no mm !\n");
919 return 1;
920 }
921 psize = get_slice_psize(mm, ea);
922 ssize = user_segment_size(ea);
923 vsid = get_vsid(mm->context.id, ea, ssize);
924 break;
925 case VMALLOC_REGION_ID:
926 mm = &init_mm;
927 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
928 if (ea < VMALLOC_END)
929 psize = mmu_vmalloc_psize;
930 else
931 psize = mmu_io_psize;
932 ssize = mmu_kernel_ssize;
933 break;
934 default:
935
936
937
938 return 1;
939 }
940 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
941
942
943 pgdir = mm->pgd;
944 if (pgdir == NULL)
945 return 1;
946
947
948 tmp = cpumask_of(smp_processor_id());
949 if (user_region && cpumask_equal(mm_cpumask(mm), tmp))
950 local = 1;
951
952#ifndef CONFIG_PPC_64K_PAGES
953
954
955
956
957
958
959
960 if (psize != MMU_PAGE_4K)
961 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
962#endif
963
964
965 ptep = find_linux_pte_or_hugepte(pgdir, ea, &hugeshift);
966 if (ptep == NULL || !pte_present(*ptep)) {
967 DBG_LOW(" no PTE !\n");
968 return 1;
969 }
970
971
972 access |= _PAGE_PRESENT;
973
974
975
976
977 if (access & ~pte_val(*ptep)) {
978 DBG_LOW(" no access !\n");
979 return 1;
980 }
981
982#ifdef CONFIG_HUGETLB_PAGE
983 if (hugeshift)
984 return __hash_page_huge(ea, access, vsid, ptep, trap, local,
985 ssize, hugeshift, psize);
986#endif
987
988#ifndef CONFIG_PPC_64K_PAGES
989 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
990#else
991 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
992 pte_val(*(ptep + PTRS_PER_PTE)));
993#endif
994
995#ifdef CONFIG_PPC_64K_PAGES
996
997 if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
998 demote_segment_4k(mm, ea);
999 psize = MMU_PAGE_4K;
1000 }
1001
1002
1003
1004
1005 if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
1006 (pte_val(*ptep) & _PAGE_NO_CACHE)) {
1007 if (user_region) {
1008 demote_segment_4k(mm, ea);
1009 psize = MMU_PAGE_4K;
1010 } else if (ea < VMALLOC_END) {
1011
1012
1013
1014
1015
1016 printk(KERN_ALERT "Reducing vmalloc segment "
1017 "to 4kB pages because of "
1018 "non-cacheable mapping\n");
1019 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1020#ifdef CONFIG_SPU_BASE
1021 spu_flush_all_slbs(mm);
1022#endif
1023 }
1024 }
1025 if (user_region) {
1026 if (psize != get_paca_psize(ea)) {
1027 get_paca()->context = mm->context;
1028 slb_flush_and_rebolt();
1029 }
1030 } else if (get_paca()->vmalloc_sllp !=
1031 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1032 get_paca()->vmalloc_sllp =
1033 mmu_psize_defs[mmu_vmalloc_psize].sllp;
1034 slb_vmalloc_update();
1035 }
1036#endif
1037
1038#ifdef CONFIG_PPC_HAS_HASH_64K
1039 if (psize == MMU_PAGE_64K)
1040 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1041 else
1042#endif
1043 {
1044 int spp = subpage_protection(mm, ea);
1045 if (access & spp)
1046 rc = -2;
1047 else
1048 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1049 local, ssize, spp);
1050 }
1051
1052
1053
1054
1055 if (rc == -1)
1056 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1057 pte_val(*ptep));
1058#ifndef CONFIG_PPC_64K_PAGES
1059 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1060#else
1061 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1062 pte_val(*(ptep + PTRS_PER_PTE)));
1063#endif
1064 DBG_LOW(" -> rc=%d\n", rc);
1065 return rc;
1066}
1067EXPORT_SYMBOL_GPL(hash_page);
1068
1069void hash_preload(struct mm_struct *mm, unsigned long ea,
1070 unsigned long access, unsigned long trap)
1071{
1072 unsigned long vsid;
1073 pgd_t *pgdir;
1074 pte_t *ptep;
1075 unsigned long flags;
1076 int rc, ssize, local = 0;
1077
1078 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1079
1080#ifdef CONFIG_PPC_MM_SLICES
1081
1082 if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
1083 return;
1084#endif
1085
1086 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1087 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1088
1089
1090 pgdir = mm->pgd;
1091 if (pgdir == NULL)
1092 return;
1093 ptep = find_linux_pte(pgdir, ea);
1094 if (!ptep)
1095 return;
1096
1097#ifdef CONFIG_PPC_64K_PAGES
1098
1099
1100
1101
1102
1103
1104 if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
1105 return;
1106#endif
1107
1108
1109 ssize = user_segment_size(ea);
1110 vsid = get_vsid(mm->context.id, ea, ssize);
1111
1112
1113 local_irq_save(flags);
1114
1115
1116 if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1117 local = 1;
1118
1119
1120#ifdef CONFIG_PPC_HAS_HASH_64K
1121 if (mm->context.user_psize == MMU_PAGE_64K)
1122 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1123 else
1124#endif
1125 rc = __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
1126 subpage_protection(mm, ea));
1127
1128
1129
1130
1131 if (rc == -1)
1132 hash_failure_debug(ea, access, vsid, trap, ssize,
1133 mm->context.user_psize, pte_val(*ptep));
1134
1135 local_irq_restore(flags);
1136}
1137
1138
1139
1140
1141void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
1142 int local)
1143{
1144 unsigned long hash, index, shift, hidx, slot;
1145
1146 DBG_LOW("flush_hash_page(va=%016lx)\n", va);
1147 pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
1148 hash = hpt_hash(va, shift, ssize);
1149 hidx = __rpte_to_hidx(pte, index);
1150 if (hidx & _PTEIDX_SECONDARY)
1151 hash = ~hash;
1152 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1153 slot += hidx & _PTEIDX_GROUP_IX;
1154 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
1155 ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
1156 } pte_iterate_hashed_end();
1157}
1158
1159void flush_hash_range(unsigned long number, int local)
1160{
1161 if (ppc_md.flush_hash_range)
1162 ppc_md.flush_hash_range(number, local);
1163 else {
1164 int i;
1165 struct ppc64_tlb_batch *batch =
1166 &__get_cpu_var(ppc64_tlb_batch);
1167
1168 for (i = 0; i < number; i++)
1169 flush_hash_page(batch->vaddr[i], batch->pte[i],
1170 batch->psize, batch->ssize, local);
1171 }
1172}
1173
1174
1175
1176
1177
1178void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1179{
1180 if (user_mode(regs)) {
1181#ifdef CONFIG_PPC_SUBPAGE_PROT
1182 if (rc == -2)
1183 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1184 else
1185#endif
1186 _exception(SIGBUS, regs, BUS_ADRERR, address);
1187 } else
1188 bad_page_fault(regs, address, SIGBUS);
1189}
1190
1191#ifdef CONFIG_DEBUG_PAGEALLOC
1192static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1193{
1194 unsigned long hash, hpteg;
1195 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1196 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1197 unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL);
1198 int ret;
1199
1200 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1201 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
1202
1203 ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr),
1204 mode, HPTE_V_BOLTED,
1205 mmu_linear_psize, mmu_kernel_ssize);
1206 BUG_ON (ret < 0);
1207 spin_lock(&linear_map_hash_lock);
1208 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1209 linear_map_hash_slots[lmi] = ret | 0x80;
1210 spin_unlock(&linear_map_hash_lock);
1211}
1212
1213static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1214{
1215 unsigned long hash, hidx, slot;
1216 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1217 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1218
1219 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1220 spin_lock(&linear_map_hash_lock);
1221 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1222 hidx = linear_map_hash_slots[lmi] & 0x7f;
1223 linear_map_hash_slots[lmi] = 0;
1224 spin_unlock(&linear_map_hash_lock);
1225 if (hidx & _PTEIDX_SECONDARY)
1226 hash = ~hash;
1227 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1228 slot += hidx & _PTEIDX_GROUP_IX;
1229 ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0);
1230}
1231
1232void kernel_map_pages(struct page *page, int numpages, int enable)
1233{
1234 unsigned long flags, vaddr, lmi;
1235 int i;
1236
1237 local_irq_save(flags);
1238 for (i = 0; i < numpages; i++, page++) {
1239 vaddr = (unsigned long)page_address(page);
1240 lmi = __pa(vaddr) >> PAGE_SHIFT;
1241 if (lmi >= linear_map_hash_count)
1242 continue;
1243 if (enable)
1244 kernel_map_linear_page(vaddr, lmi);
1245 else
1246 kernel_unmap_linear_page(vaddr, lmi);
1247 }
1248 local_irq_restore(flags);
1249}
1250#endif
1251
1252void setup_initial_memory_limit(phys_addr_t first_memblock_base,
1253 phys_addr_t first_memblock_size)
1254{
1255
1256
1257
1258 BUG_ON(first_memblock_base != 0);
1259
1260
1261
1262
1263
1264
1265
1266 ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
1267
1268
1269 memblock_set_current_limit(ppc64_rma_size);
1270}
1271