LXR linux/arch/sh/mm/Makefile

   1#
   2# Makefile for the Linux SuperH-specific parts of the memory manager.
   3#
   4
   5obj-y                   := alignment.o cache.o init.o consistent.o mmap.o
   6
   7cacheops-$(CONFIG_CPU_SH2)              := cache-sh2.o
   8cacheops-$(CONFIG_CPU_SH2A)             := cache-sh2a.o
   9cacheops-$(CONFIG_CPU_SH3)              := cache-sh3.o
  10cacheops-$(CONFIG_CPU_SH4)              := cache-sh4.o flush-sh4.o
  11cacheops-$(CONFIG_CPU_SH5)              := cache-sh5.o flush-sh4.o
  12cacheops-$(CONFIG_SH7705_CACHE_32KB)    += cache-sh7705.o
  13cacheops-$(CONFIG_CPU_SHX3)             += cache-shx3.o
  14
  15obj-y                   += $(cacheops-y)
  16
  17mmu-y                   := nommu.o extable_32.o
  18mmu-$(CONFIG_MMU)       := extable_$(BITS).o fault_$(BITS).o gup.o \
  19                           ioremap.o kmap.o pgtable.o tlbflush_$(BITS).o
  20
  21obj-y                   += $(mmu-y)
  22
  23debugfs-y                       := asids-debugfs.o
  24ifndef CONFIG_CACHE_OFF
  25debugfs-$(CONFIG_CPU_SH4)       += cache-debugfs.o
  26endif
  27
  28ifdef CONFIG_MMU
  29debugfs-$(CONFIG_CPU_SH4)       += tlb-debugfs.o
  30tlb-$(CONFIG_CPU_SH3)           := tlb-sh3.o
  31tlb-$(CONFIG_CPU_SH4)           := tlb-sh4.o tlb-urb.o
  32tlb-$(CONFIG_CPU_SH5)           := tlb-sh5.o
  33tlb-$(CONFIG_CPU_HAS_PTEAEX)    := tlb-pteaex.o tlb-urb.o
  34obj-y                           += $(tlb-y)
  35endif
  36
  37obj-$(CONFIG_DEBUG_FS)          += $(debugfs-y)
  38obj-$(CONFIG_HUGETLB_PAGE)      += hugetlbpage.o
  39obj-$(CONFIG_PMB)               += pmb.o
  40obj-$(CONFIG_NUMA)              += numa.o
  41obj-$(CONFIG_IOREMAP_FIXED)     += ioremap_fixed.o
  42obj-$(CONFIG_UNCACHED_MAPPING)  += uncached.o
  43obj-$(CONFIG_HAVE_SRAM_POOL)    += sram.o
  44
  45# Special flags for fault_64.o.  This puts restrictions on the number of
  46# caller-save registers that the compiler can target when building this file.
  47# This is required because the code is called from a context in entry.S where
  48# very few registers have been saved in the exception handler (for speed
  49# reasons).
  50# The caller save registers that have been saved and which can be used are
  51# r2,r3,r4,r5 : argument passing
  52# r15, r18 : SP and LINK
  53# tr0-4 : allow all caller-save TR's.  The compiler seems to be able to make
  54#         use of them, so it's probably beneficial to performance to save them
  55#         and have them available for it.
  56#
  57# The resources not listed below are callee save, i.e. the compiler is free to
  58# use any of them and will spill them to the stack itself.
  59
  60CFLAGS_fault_64.o += -ffixed-r7 \
  61        -ffixed-r8 -ffixed-r9 -ffixed-r10 -ffixed-r11 -ffixed-r12 \
  62        -ffixed-r13 -ffixed-r14 -ffixed-r16 -ffixed-r17 -ffixed-r19 \
  63        -ffixed-r20 -ffixed-r21 -ffixed-r22 -ffixed-r23 \
  64        -ffixed-r24 -ffixed-r25 -ffixed-r26 -ffixed-r27 \
  65        -ffixed-r36 -ffixed-r37 -ffixed-r38 -ffixed-r39 -ffixed-r40 \
  66        -ffixed-r41 -ffixed-r42 -ffixed-r43  \
  67        -ffixed-r60 -ffixed-r61 -ffixed-r62 \
  68        -fomit-frame-pointer
  69
  70ccflags-y := -Werror
  71