1#ifndef _ASM_X86_APIC_H
2#define _ASM_X86_APIC_H
3
4#include <linux/cpumask.h>
5#include <linux/delay.h>
6#include <linux/pm.h>
7
8#include <asm/alternative.h>
9#include <asm/cpufeature.h>
10#include <asm/processor.h>
11#include <asm/apicdef.h>
12#include <asm/atomic.h>
13#include <asm/fixmap.h>
14#include <asm/mpspec.h>
15#include <asm/system.h>
16#include <asm/msr.h>
17
18#define ARCH_APICTIMER_STOPS_ON_C3 1
19
20
21
22
23#define APIC_QUIET 0
24#define APIC_VERBOSE 1
25#define APIC_DEBUG 2
26
27
28
29
30
31
32
33#define apic_printk(v, s, a...) do { \
34 if ((v) <= apic_verbosity) \
35 printk(s, ##a); \
36 } while (0)
37
38
39#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
40extern void generic_apic_probe(void);
41#else
42static inline void generic_apic_probe(void)
43{
44}
45#endif
46
47#ifdef CONFIG_X86_LOCAL_APIC
48
49extern unsigned int apic_verbosity;
50extern int local_apic_timer_c2_ok;
51
52extern int disable_apic;
53
54#ifdef CONFIG_SMP
55extern void __inquire_remote_apic(int apicid);
56#else
57static inline void __inquire_remote_apic(int apicid)
58{
59}
60#endif
61
62static inline void default_inquire_remote_apic(int apicid)
63{
64 if (apic_verbosity >= APIC_DEBUG)
65 __inquire_remote_apic(apicid);
66}
67
68
69
70
71
72
73
74
75
76static inline bool apic_from_smp_config(void)
77{
78 return smp_found_config && !disable_apic;
79}
80
81
82
83
84#ifdef CONFIG_PARAVIRT
85#include <asm/paravirt.h>
86#endif
87
88#ifdef CONFIG_X86_64
89extern int is_vsmp_box(void);
90#else
91static inline int is_vsmp_box(void)
92{
93 return 0;
94}
95#endif
96extern void xapic_wait_icr_idle(void);
97extern u32 safe_xapic_wait_icr_idle(void);
98extern void xapic_icr_write(u32, u32);
99extern int setup_profiling_timer(unsigned int);
100
101static inline void native_apic_mem_write(u32 reg, u32 v)
102{
103 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
104
105 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
106 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
107 ASM_OUTPUT2("0" (v), "m" (*addr)));
108}
109
110static inline u32 native_apic_mem_read(u32 reg)
111{
112 return *((volatile u32 *)(APIC_BASE + reg));
113}
114
115extern void native_apic_wait_icr_idle(void);
116extern u32 native_safe_apic_wait_icr_idle(void);
117extern void native_apic_icr_write(u32 low, u32 id);
118extern u64 native_apic_icr_read(void);
119
120extern int x2apic_mode;
121
122#ifdef CONFIG_X86_X2APIC
123
124
125
126
127
128static inline void x2apic_wrmsr_fence(void)
129{
130 asm volatile("mfence" : : : "memory");
131}
132
133static inline void native_apic_msr_write(u32 reg, u32 v)
134{
135 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
136 reg == APIC_LVR)
137 return;
138
139 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
140}
141
142static inline u32 native_apic_msr_read(u32 reg)
143{
144 u64 msr;
145
146 if (reg == APIC_DFR)
147 return -1;
148
149 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
150 return (u32)msr;
151}
152
153static inline void native_x2apic_wait_icr_idle(void)
154{
155
156 return;
157}
158
159static inline u32 native_safe_x2apic_wait_icr_idle(void)
160{
161
162 return 0;
163}
164
165static inline void native_x2apic_icr_write(u32 low, u32 id)
166{
167 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
168}
169
170static inline u64 native_x2apic_icr_read(void)
171{
172 unsigned long val;
173
174 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
175 return val;
176}
177
178extern int x2apic_phys;
179extern void check_x2apic(void);
180extern void enable_x2apic(void);
181extern void x2apic_icr_write(u32 low, u32 id);
182static inline int x2apic_enabled(void)
183{
184 u64 msr;
185
186 if (!cpu_has_x2apic)
187 return 0;
188
189 rdmsrl(MSR_IA32_APICBASE, msr);
190 if (msr & X2APIC_ENABLE)
191 return 1;
192 return 0;
193}
194
195#define x2apic_supported() (cpu_has_x2apic)
196static inline void x2apic_force_phys(void)
197{
198 x2apic_phys = 1;
199}
200#else
201static inline void check_x2apic(void)
202{
203}
204static inline void enable_x2apic(void)
205{
206}
207static inline int x2apic_enabled(void)
208{
209 return 0;
210}
211static inline void x2apic_force_phys(void)
212{
213}
214
215#define x2apic_preenabled 0
216#define x2apic_supported() 0
217#endif
218
219extern void enable_IR_x2apic(void);
220
221extern int get_physical_broadcast(void);
222
223extern void apic_disable(void);
224extern int lapic_get_maxlvt(void);
225extern void clear_local_APIC(void);
226extern void connect_bsp_APIC(void);
227extern void disconnect_bsp_APIC(int virt_wire_setup);
228extern void disable_local_APIC(void);
229extern void lapic_shutdown(void);
230extern int verify_local_APIC(void);
231extern void cache_APIC_registers(void);
232extern void sync_Arb_IDs(void);
233extern void init_bsp_APIC(void);
234extern void setup_local_APIC(void);
235extern void end_local_APIC_setup(void);
236extern void bsp_end_local_APIC_setup(void);
237extern void init_apic_mappings(void);
238void register_lapic_address(unsigned long address);
239extern void setup_boot_APIC_clock(void);
240extern void setup_secondary_APIC_clock(void);
241extern int APIC_init_uniprocessor(void);
242extern void enable_NMI_through_LVT0(void);
243extern int apic_force_enable(void);
244
245
246
247
248#ifdef CONFIG_X86_64
249extern int apic_is_clustered_box(void);
250#else
251static inline int apic_is_clustered_box(void)
252{
253 return 0;
254}
255#endif
256
257extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
258
259#else
260static inline void lapic_shutdown(void) { }
261#define local_apic_timer_c2_ok 1
262static inline void init_apic_mappings(void) { }
263static inline void disable_local_APIC(void) { }
264static inline void apic_disable(void) { }
265# define setup_boot_APIC_clock x86_init_noop
266# define setup_secondary_APIC_clock x86_init_noop
267#endif
268
269#ifdef CONFIG_X86_64
270#define SET_APIC_ID(x) (apic->set_apic_id(x))
271#else
272
273#endif
274
275
276
277
278
279
280
281
282
283
284
285struct apic {
286 char *name;
287
288 int (*probe)(void);
289 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
290 int (*apic_id_registered)(void);
291
292 u32 irq_delivery_mode;
293 u32 irq_dest_mode;
294
295 const struct cpumask *(*target_cpus)(void);
296
297 int disable_esr;
298
299 int dest_logical;
300 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
301 unsigned long (*check_apicid_present)(int apicid);
302
303 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
304 void (*init_apic_ldr)(void);
305
306 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
307
308 void (*setup_apic_routing)(void);
309 int (*multi_timer_check)(int apic, int irq);
310 int (*apicid_to_node)(int logical_apicid);
311 int (*cpu_to_logical_apicid)(int cpu);
312 int (*cpu_present_to_apicid)(int mps_cpu);
313 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
314 void (*setup_portio_remap)(void);
315 int (*check_phys_apicid_present)(int phys_apicid);
316 void (*enable_apic_mode)(void);
317 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
318
319
320
321
322
323
324 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
325
326 unsigned int (*get_apic_id)(unsigned long x);
327 unsigned long (*set_apic_id)(unsigned int id);
328 unsigned long apic_id_mask;
329
330 unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask);
331 unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
332 const struct cpumask *andmask);
333
334
335 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
336 void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
337 int vector);
338 void (*send_IPI_allbutself)(int vector);
339 void (*send_IPI_all)(int vector);
340 void (*send_IPI_self)(int vector);
341
342
343 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
344
345 int trampoline_phys_low;
346 int trampoline_phys_high;
347
348 void (*wait_for_init_deassert)(atomic_t *deassert);
349 void (*smp_callin_clear_local_apic)(void);
350 void (*inquire_remote_apic)(int apicid);
351
352
353 u32 (*read)(u32 reg);
354 void (*write)(u32 reg, u32 v);
355 u64 (*icr_read)(void);
356 void (*icr_write)(u32 low, u32 high);
357 void (*wait_icr_idle)(void);
358 u32 (*safe_wait_icr_idle)(void);
359};
360
361
362
363
364
365
366extern struct apic *apic;
367
368
369
370
371#ifdef CONFIG_SMP
372extern atomic_t init_deasserted;
373extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
374#endif
375
376#ifdef CONFIG_X86_LOCAL_APIC
377static inline u32 apic_read(u32 reg)
378{
379 return apic->read(reg);
380}
381
382static inline void apic_write(u32 reg, u32 val)
383{
384 apic->write(reg, val);
385}
386
387static inline u64 apic_icr_read(void)
388{
389 return apic->icr_read();
390}
391
392static inline void apic_icr_write(u32 low, u32 high)
393{
394 apic->icr_write(low, high);
395}
396
397static inline void apic_wait_icr_idle(void)
398{
399 apic->wait_icr_idle();
400}
401
402static inline u32 safe_apic_wait_icr_idle(void)
403{
404 return apic->safe_wait_icr_idle();
405}
406
407#else
408
409static inline u32 apic_read(u32 reg) { return 0; }
410static inline void apic_write(u32 reg, u32 val) { }
411static inline u64 apic_icr_read(void) { return 0; }
412static inline void apic_icr_write(u32 low, u32 high) { }
413static inline void apic_wait_icr_idle(void) { }
414static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
415
416#endif
417
418static inline void ack_APIC_irq(void)
419{
420
421
422
423
424
425
426 apic_write(APIC_EOI, 0);
427}
428
429static inline unsigned default_get_apic_id(unsigned long x)
430{
431 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
432
433 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
434 return (x >> 24) & 0xFF;
435 else
436 return (x >> 24) & 0x0F;
437}
438
439
440
441
442#define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467
443#define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469
444
445#ifdef CONFIG_X86_64
446extern struct apic apic_flat;
447extern struct apic apic_physflat;
448extern struct apic apic_x2apic_cluster;
449extern struct apic apic_x2apic_phys;
450extern int default_acpi_madt_oem_check(char *, char *);
451
452extern void apic_send_IPI_self(int vector);
453
454extern struct apic apic_x2apic_uv_x;
455DECLARE_PER_CPU(int, x2apic_extra_bits);
456
457extern int default_cpu_present_to_apicid(int mps_cpu);
458extern int default_check_phys_apicid_present(int phys_apicid);
459#endif
460
461static inline void default_wait_for_init_deassert(atomic_t *deassert)
462{
463 while (!atomic_read(deassert))
464 cpu_relax();
465 return;
466}
467
468extern void generic_bigsmp_probe(void);
469
470
471#ifdef CONFIG_X86_LOCAL_APIC
472
473#include <asm/smp.h>
474
475#define APIC_DFR_VALUE (APIC_DFR_FLAT)
476
477static inline const struct cpumask *default_target_cpus(void)
478{
479#ifdef CONFIG_SMP
480 return cpu_online_mask;
481#else
482 return cpumask_of(0);
483#endif
484}
485
486DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
487
488
489static inline unsigned int read_apic_id(void)
490{
491 unsigned int reg;
492
493 reg = apic_read(APIC_ID);
494
495 return apic->get_apic_id(reg);
496}
497
498extern void default_setup_apic_routing(void);
499
500extern struct apic apic_noop;
501
502#ifdef CONFIG_X86_32
503
504extern struct apic apic_default;
505
506
507
508
509
510
511
512
513extern void default_init_apic_ldr(void);
514
515static inline int default_apic_id_registered(void)
516{
517 return physid_isset(read_apic_id(), phys_cpu_present_map);
518}
519
520static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
521{
522 return cpuid_apic >> index_msb;
523}
524
525extern int default_apicid_to_node(int logical_apicid);
526
527#endif
528
529static inline unsigned int
530default_cpu_mask_to_apicid(const struct cpumask *cpumask)
531{
532 return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS;
533}
534
535static inline unsigned int
536default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
537 const struct cpumask *andmask)
538{
539 unsigned long mask1 = cpumask_bits(cpumask)[0];
540 unsigned long mask2 = cpumask_bits(andmask)[0];
541 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
542
543 return (unsigned int)(mask1 & mask2 & mask3);
544}
545
546static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
547{
548 return physid_isset(apicid, *map);
549}
550
551static inline unsigned long default_check_apicid_present(int bit)
552{
553 return physid_isset(bit, phys_cpu_present_map);
554}
555
556static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
557{
558 *retmap = *phys_map;
559}
560
561
562static inline int default_cpu_to_logical_apicid(int cpu)
563{
564 return 1 << cpu;
565}
566
567static inline int __default_cpu_present_to_apicid(int mps_cpu)
568{
569 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
570 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
571 else
572 return BAD_APICID;
573}
574
575static inline int
576__default_check_phys_apicid_present(int phys_apicid)
577{
578 return physid_isset(phys_apicid, phys_cpu_present_map);
579}
580
581#ifdef CONFIG_X86_32
582static inline int default_cpu_present_to_apicid(int mps_cpu)
583{
584 return __default_cpu_present_to_apicid(mps_cpu);
585}
586
587static inline int
588default_check_phys_apicid_present(int phys_apicid)
589{
590 return __default_check_phys_apicid_present(phys_apicid);
591}
592#else
593extern int default_cpu_present_to_apicid(int mps_cpu);
594extern int default_check_phys_apicid_present(int phys_apicid);
595#endif
596
597#endif
598
599#ifdef CONFIG_X86_32
600extern u8 cpu_2_logical_apicid[NR_CPUS];
601#endif
602
603#endif
604