1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV MMR definitions 7 * 8 * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved. 9 */ 10 11#ifndef _ASM_X86_UV_UV_MMRS_H 12#define _ASM_X86_UV_UV_MMRS_H 13 14#define UV_MMR_ENABLE (1UL << 63) 15 16/* ========================================================================= */ 17/* UVH_BAU_DATA_BROADCAST */ 18/* ========================================================================= */ 19#define UVH_BAU_DATA_BROADCAST 0x61688UL 20#define UVH_BAU_DATA_BROADCAST_32 0x0440 21 22#define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0 23#define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL 24 25union uvh_bau_data_broadcast_u { 26 unsigned long v; 27 struct uvh_bau_data_broadcast_s { 28 unsigned long enable : 1; /* RW */ 29 unsigned long rsvd_1_63: 63; /* */ 30 } s; 31}; 32 33/* ========================================================================= */ 34/* UVH_BAU_DATA_CONFIG */ 35/* ========================================================================= */ 36#define UVH_BAU_DATA_CONFIG 0x61680UL 37#define UVH_BAU_DATA_CONFIG_32 0x0438 38 39#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0 40#define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL 41#define UVH_BAU_DATA_CONFIG_DM_SHFT 8 42#define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL 43#define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11 44#define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL 45#define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12 46#define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL 47#define UVH_BAU_DATA_CONFIG_P_SHFT 13 48#define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL 49#define UVH_BAU_DATA_CONFIG_T_SHFT 15 50#define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL 51#define UVH_BAU_DATA_CONFIG_M_SHFT 16 52#define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL 53#define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32 54#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 55 56union uvh_bau_data_config_u { 57 unsigned long v; 58 struct uvh_bau_data_config_s { 59 unsigned long vector_ : 8; /* RW */ 60 unsigned long dm : 3; /* RW */ 61 unsigned long destmode : 1; /* RW */ 62 unsigned long status : 1; /* RO */ 63 unsigned long p : 1; /* RO */ 64 unsigned long rsvd_14 : 1; /* */ 65 unsigned long t : 1; /* RO */ 66 unsigned long m : 1; /* RW */ 67 unsigned long rsvd_17_31: 15; /* */ 68 unsigned long apic_id : 32; /* RW */ 69 } s; 70}; 71 72/* ========================================================================= */ 73/* UVH_EVENT_OCCURRED0 */ 74/* ========================================================================= */ 75#define UVH_EVENT_OCCURRED0 0x70000UL 76#define UVH_EVENT_OCCURRED0_32 0x005e8 77 78#define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0 79#define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL 80#define UVH_EVENT_OCCURRED0_GR0_HCERR_SHFT 1 81#define UVH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL 82#define UVH_EVENT_OCCURRED0_GR1_HCERR_SHFT 2 83#define UVH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL 84#define UVH_EVENT_OCCURRED0_LH_HCERR_SHFT 3 85#define UVH_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL 86#define UVH_EVENT_OCCURRED0_RH_HCERR_SHFT 4 87#define UVH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL 88#define UVH_EVENT_OCCURRED0_XN_HCERR_SHFT 5 89#define UVH_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL 90#define UVH_EVENT_OCCURRED0_SI_HCERR_SHFT 6 91#define UVH_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL 92#define UVH_EVENT_OCCURRED0_LB_AOERR0_SHFT 7 93#define UVH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL 94#define UVH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8 95#define UVH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL 96#define UVH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9 97#define UVH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL 98#define UVH_EVENT_OCCURRED0_LH_AOERR0_SHFT 10 99#define UVH_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL 100#define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11 101#define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL 102#define UVH_EVENT_OCCURRED0_XN_AOERR0_SHFT 12 103#define UVH_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL 104#define UVH_EVENT_OCCURRED0_SI_AOERR0_SHFT 13 105#define UVH_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL 106#define UVH_EVENT_OCCURRED0_LB_AOERR1_SHFT 14 107#define UVH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL 108#define UVH_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15 109#define UVH_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL 110#define UVH_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16 111#define UVH_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL 112#define UVH_EVENT_OCCURRED0_LH_AOERR1_SHFT 17 113#define UVH_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL 114#define UVH_EVENT_OCCURRED0_RH_AOERR1_SHFT 18 115#define UVH_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL 116#define UVH_EVENT_OCCURRED0_XN_AOERR1_SHFT 19 117#define UVH_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL 118#define UVH_EVENT_OCCURRED0_SI_AOERR1_SHFT 20 119#define UVH_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL 120#define UVH_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21 121#define UVH_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL 122#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22 123#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL 124#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23 125#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL 126#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24 127#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL 128#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25 129#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL 130#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26 131#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL 132#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27 133#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL 134#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28 135#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL 136#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29 137#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL 138#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30 139#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL 140#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31 141#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL 142#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32 143#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL 144#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33 145#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL 146#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34 147#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL 148#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35 149#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL 150#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36 151#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL 152#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37 153#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL 154#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38 155#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL 156#define UVH_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39 157#define UVH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL 158#define UVH_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40 159#define UVH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL 160#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41 161#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL 162#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42 163#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL 164#define UVH_EVENT_OCCURRED0_LTC_INT_SHFT 43 165#define UVH_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL 166#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44 167#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL 168#define UVH_EVENT_OCCURRED0_IPI_INT_SHFT 45 169#define UVH_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL 170#define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46 171#define UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL 172#define UVH_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47 173#define UVH_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL 174#define UVH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48 175#define UVH_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL 176#define UVH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49 177#define UVH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL 178#define UVH_EVENT_OCCURRED0_PROFILE_INT_SHFT 50 179#define UVH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL 180#define UVH_EVENT_OCCURRED0_RTC0_SHFT 51 181#define UVH_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL 182#define UVH_EVENT_OCCURRED0_RTC1_SHFT 52 183#define UVH_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL 184#define UVH_EVENT_OCCURRED0_RTC2_SHFT 53 185#define UVH_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL 186#define UVH_EVENT_OCCURRED0_RTC3_SHFT 54 187#define UVH_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL 188#define UVH_EVENT_OCCURRED0_BAU_DATA_SHFT 55 189#define UVH_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL 190#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56 191#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL 192union uvh_event_occurred0_u { 193 unsigned long v; 194 struct uvh_event_occurred0_s { 195 unsigned long lb_hcerr : 1; /* RW, W1C */ 196 unsigned long gr0_hcerr : 1; /* RW, W1C */ 197 unsigned long gr1_hcerr : 1; /* RW, W1C */ 198 unsigned long lh_hcerr : 1; /* RW, W1C */ 199 unsigned long rh_hcerr : 1; /* RW, W1C */ 200 unsigned long xn_hcerr : 1; /* RW, W1C */ 201 unsigned long si_hcerr : 1; /* RW, W1C */ 202 unsigned long lb_aoerr0 : 1; /* RW, W1C */ 203 unsigned long gr0_aoerr0 : 1; /* RW, W1C */ 204 unsigned long gr1_aoerr0 : 1; /* RW, W1C */ 205 unsigned long lh_aoerr0 : 1; /* RW, W1C */ 206 unsigned long rh_aoerr0 : 1; /* RW, W1C */ 207 unsigned long xn_aoerr0 : 1; /* RW, W1C */ 208 unsigned long si_aoerr0 : 1; /* RW, W1C */ 209 unsigned long lb_aoerr1 : 1; /* RW, W1C */ 210 unsigned long gr0_aoerr1 : 1; /* RW, W1C */ 211 unsigned long gr1_aoerr1 : 1; /* RW, W1C */ 212 unsigned long lh_aoerr1 : 1; /* RW, W1C */ 213 unsigned long rh_aoerr1 : 1; /* RW, W1C */ 214 unsigned long xn_aoerr1 : 1; /* RW, W1C */ 215 unsigned long si_aoerr1 : 1; /* RW, W1C */ 216 unsigned long rh_vpi_int : 1; /* RW, W1C */ 217 unsigned long system_shutdown_int : 1; /* RW, W1C */ 218 unsigned long lb_irq_int_0 : 1; /* RW, W1C */ 219 unsigned long lb_irq_int_1 : 1; /* RW, W1C */ 220 unsigned long lb_irq_int_2 : 1; /* RW, W1C */ 221 unsigned long lb_irq_int_3 : 1; /* RW, W1C */ 222 unsigned long lb_irq_int_4 : 1; /* RW, W1C */ 223 unsigned long lb_irq_int_5 : 1; /* RW, W1C */ 224 unsigned long lb_irq_int_6 : 1; /* RW, W1C */ 225 unsigned long lb_irq_int_7 : 1; /* RW, W1C */ 226 unsigned long lb_irq_int_8 : 1; /* RW, W1C */ 227 unsigned long lb_irq_int_9 : 1; /* RW, W1C */ 228 unsigned long lb_irq_int_10 : 1; /* RW, W1C */ 229 unsigned long lb_irq_int_11 : 1; /* RW, W1C */ 230 unsigned long lb_irq_int_12 : 1; /* RW, W1C */ 231 unsigned long lb_irq_int_13 : 1; /* RW, W1C */ 232 unsigned long lb_irq_int_14 : 1; /* RW, W1C */ 233 unsigned long lb_irq_int_15 : 1; /* RW, W1C */ 234 unsigned long l1_nmi_int : 1; /* RW, W1C */ 235 unsigned long stop_clock : 1; /* RW, W1C */ 236 unsigned long asic_to_l1 : 1; /* RW, W1C */ 237 unsigned long l1_to_asic : 1; /* RW, W1C */ 238 unsigned long ltc_int : 1; /* RW, W1C */ 239 unsigned long la_seq_trigger : 1; /* RW, W1C */ 240 unsigned long ipi_int : 1; /* RW, W1C */ 241 unsigned long extio_int0 : 1; /* RW, W1C */ 242 unsigned long extio_int1 : 1; /* RW, W1C */ 243 unsigned long extio_int2 : 1; /* RW, W1C */ 244 unsigned long extio_int3 : 1; /* RW, W1C */ 245 unsigned long profile_int : 1; /* RW, W1C */ 246 unsigned long rtc0 : 1; /* RW, W1C */ 247 unsigned long rtc1 : 1; /* RW, W1C */ 248 unsigned long rtc2 : 1; /* RW, W1C */ 249 unsigned long rtc3 : 1; /* RW, W1C */ 250 unsigned long bau_data : 1; /* RW, W1C */ 251 unsigned long power_management_req : 1; /* RW, W1C */ 252 unsigned long rsvd_57_63 : 7; /* */ 253 } s; 254}; 255 256/* ========================================================================= */ 257/* UVH_EVENT_OCCURRED0_ALIAS */ 258/* ========================================================================= */ 259#define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL 260#define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0 261 262/* ========================================================================= */ 263/* UVH_GR0_TLB_INT0_CONFIG */ 264/* ========================================================================= */ 265#define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL 266 267#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0 268#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL 269#define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8 270#define UVH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL 271#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11 272#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL 273#define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12 274#define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL 275#define UVH_GR0_TLB_INT0_CONFIG_P_SHFT 13 276#define UVH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL 277#define UVH_GR0_TLB_INT0_CONFIG_T_SHFT 15 278#define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL 279#define UVH_GR0_TLB_INT0_CONFIG_M_SHFT 16 280#define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL 281#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32 282#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 283 284union uvh_gr0_tlb_int0_config_u { 285 unsigned long v; 286 struct uvh_gr0_tlb_int0_config_s { 287 unsigned long vector_ : 8; /* RW */ 288 unsigned long dm : 3; /* RW */ 289 unsigned long destmode : 1; /* RW */ 290 unsigned long status : 1; /* RO */ 291 unsigned long p : 1; /* RO */ 292 unsigned long rsvd_14 : 1; /* */ 293 unsigned long t : 1; /* RO */ 294 unsigned long m : 1; /* RW */ 295 unsigned long rsvd_17_31: 15; /* */ 296 unsigned long apic_id : 32; /* RW */ 297 } s; 298}; 299 300/* ========================================================================= */ 301/* UVH_GR0_TLB_INT1_CONFIG */ 302/* ========================================================================= */ 303#define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL 304 305#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0 306#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL 307#define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8 308#define UVH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL 309#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11 310#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL 311#define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12 312#define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL 313#define UVH_GR0_TLB_INT1_CONFIG_P_SHFT 13 314#define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL 315#define UVH_GR0_TLB_INT1_CONFIG_T_SHFT 15 316#define UVH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL 317#define UVH_GR0_TLB_INT1_CONFIG_M_SHFT 16 318#define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL 319#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32 320#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 321 322union uvh_gr0_tlb_int1_config_u { 323 unsigned long v; 324 struct uvh_gr0_tlb_int1_config_s { 325 unsigned long vector_ : 8; /* RW */ 326 unsigned long dm : 3; /* RW */ 327 unsigned long destmode : 1; /* RW */ 328 unsigned long status : 1; /* RO */ 329 unsigned long p : 1; /* RO */ 330 unsigned long rsvd_14 : 1; /* */ 331 unsigned long t : 1; /* RO */ 332 unsigned long m : 1; /* RW */ 333 unsigned long rsvd_17_31: 15; /* */ 334 unsigned long apic_id : 32; /* RW */ 335 } s; 336}; 337 338/* ========================================================================= */ 339/* UVH_GR1_TLB_INT0_CONFIG */ 340/* ========================================================================= */ 341#define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL 342 343#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0 344#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL 345#define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8 346#define UVH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL 347#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11 348#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL 349#define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12 350#define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL 351#define UVH_GR1_TLB_INT0_CONFIG_P_SHFT 13 352#define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL 353#define UVH_GR1_TLB_INT0_CONFIG_T_SHFT 15 354#define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL 355#define UVH_GR1_TLB_INT0_CONFIG_M_SHFT 16 356#define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL 357#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32 358#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 359 360union uvh_gr1_tlb_int0_config_u { 361 unsigned long v; 362 struct uvh_gr1_tlb_int0_config_s { 363 unsigned long vector_ : 8; /* RW */ 364 unsigned long dm : 3; /* RW */ 365 unsigned long destmode : 1; /* RW */ 366 unsigned long status : 1; /* RO */ 367 unsigned long p : 1; /* RO */ 368 unsigned long rsvd_14 : 1; /* */ 369 unsigned long t : 1; /* RO */ 370 unsigned long m : 1; /* RW */ 371 unsigned long rsvd_17_31: 15; /* */ 372 unsigned long apic_id : 32; /* RW */ 373 } s; 374}; 375 376/* ========================================================================= */ 377/* UVH_GR1_TLB_INT1_CONFIG */ 378/* ========================================================================= */ 379#define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL 380 381#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0 382#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL 383#define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8 384#define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL 385#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11 386#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL 387#define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12 388#define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL 389#define UVH_GR1_TLB_INT1_CONFIG_P_SHFT 13 390#define UVH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL 391#define UVH_GR1_TLB_INT1_CONFIG_T_SHFT 15 392#define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL 393#define UVH_GR1_TLB_INT1_CONFIG_M_SHFT 16 394#define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL 395#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32 396#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 397 398union uvh_gr1_tlb_int1_config_u { 399 unsigned long v; 400 struct uvh_gr1_tlb_int1_config_s { 401 unsigned long vector_ : 8; /* RW */ 402 unsigned long dm : 3; /* RW */ 403 unsigned long destmode : 1; /* RW */ 404 unsigned long status : 1; /* RO */ 405 unsigned long p : 1; /* RO */ 406 unsigned long rsvd_14 : 1; /* */ 407 unsigned long t : 1; /* RO */ 408 unsigned long m : 1; /* RW */ 409 unsigned long rsvd_17_31: 15; /* */ 410 unsigned long apic_id : 32; /* RW */ 411 } s; 412}; 413 414/* ========================================================================= */ 415/* UVH_INT_CMPB */ 416/* ========================================================================= */ 417#define UVH_INT_CMPB 0x22080UL 418 419#define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 420#define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL 421 422union uvh_int_cmpb_u { 423 unsigned long v; 424 struct uvh_int_cmpb_s { 425 unsigned long real_time_cmpb : 56; /* RW */ 426 unsigned long rsvd_56_63 : 8; /* */ 427 } s; 428}; 429 430/* ========================================================================= */ 431/* UVH_INT_CMPC */ 432/* ========================================================================= */ 433#define UVH_INT_CMPC 0x22100UL 434 435#define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT 0 436#define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL 437 438union uvh_int_cmpc_u { 439 unsigned long v; 440 struct uvh_int_cmpc_s { 441 unsigned long real_time_cmpc : 56; /* RW */ 442 unsigned long rsvd_56_63 : 8; /* */ 443 } s; 444}; 445 446/* ========================================================================= */ 447/* UVH_INT_CMPD */ 448/* ========================================================================= */ 449#define UVH_INT_CMPD 0x22180UL 450 451#define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT 0 452#define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL 453 454union uvh_int_cmpd_u { 455 unsigned long v; 456 struct uvh_int_cmpd_s { 457 unsigned long real_time_cmpd : 56; /* RW */ 458 unsigned long rsvd_56_63 : 8; /* */ 459 } s; 460}; 461 462/* ========================================================================= */ 463/* UVH_IPI_INT */ 464/* ========================================================================= */ 465#define UVH_IPI_INT 0x60500UL 466#define UVH_IPI_INT_32 0x0348 467 468#define UVH_IPI_INT_VECTOR_SHFT 0 469#define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL 470#define UVH_IPI_INT_DELIVERY_MODE_SHFT 8 471#define UVH_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL 472#define UVH_IPI_INT_DESTMODE_SHFT 11 473#define UVH_IPI_INT_DESTMODE_MASK 0x0000000000000800UL 474#define UVH_IPI_INT_APIC_ID_SHFT 16 475#define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL 476#define UVH_IPI_INT_SEND_SHFT 63 477#define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL 478 479union uvh_ipi_int_u { 480 unsigned long v; 481 struct uvh_ipi_int_s { 482 unsigned long vector_ : 8; /* RW */ 483 unsigned long delivery_mode : 3; /* RW */ 484 unsigned long destmode : 1; /* RW */ 485 unsigned long rsvd_12_15 : 4; /* */ 486 unsigned long apic_id : 32; /* RW */ 487 unsigned long rsvd_48_62 : 15; /* */ 488 unsigned long send : 1; /* WP */ 489 } s; 490}; 491 492/* ========================================================================= */ 493/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */ 494/* ========================================================================= */ 495#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL 496#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x009c0 497 498#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 499#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL 500#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 501#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL 502 503union uvh_lb_bau_intd_payload_queue_first_u { 504 unsigned long v; 505 struct uvh_lb_bau_intd_payload_queue_first_s { 506 unsigned long rsvd_0_3: 4; /* */ 507 unsigned long address : 39; /* RW */ 508 unsigned long rsvd_43_48: 6; /* */ 509 unsigned long node_id : 14; /* RW */ 510 unsigned long rsvd_63 : 1; /* */ 511 } s; 512}; 513 514/* ========================================================================= */ 515/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */ 516/* ========================================================================= */ 517#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL 518#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x009c8 519 520#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 521#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL 522 523union uvh_lb_bau_intd_payload_queue_last_u { 524 unsigned long v; 525 struct uvh_lb_bau_intd_payload_queue_last_s { 526 unsigned long rsvd_0_3: 4; /* */ 527 unsigned long address : 39; /* RW */ 528 unsigned long rsvd_43_63: 21; /* */ 529 } s; 530}; 531 532/* ========================================================================= */ 533/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */ 534/* ========================================================================= */ 535#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL 536#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x009d0 537 538#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 539#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL 540 541union uvh_lb_bau_intd_payload_queue_tail_u { 542 unsigned long v; 543 struct uvh_lb_bau_intd_payload_queue_tail_s { 544 unsigned long rsvd_0_3: 4; /* */ 545 unsigned long address : 39; /* RW */ 546 unsigned long rsvd_43_63: 21; /* */ 547 } s; 548}; 549 550/* ========================================================================= */ 551/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */ 552/* ========================================================================= */ 553#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL 554#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0x0a68 555 556#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 557#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL 558#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 559#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL 560#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2 561#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL 562#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3 563#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL 564#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4 565#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL 566#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5 567#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL 568#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6 569#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL 570#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7 571#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL 572#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8 573#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL 574#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9 575#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL 576#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10 577#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL 578#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11 579#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL 580#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12 581#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL 582#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13 583#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL 584#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14 585#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL 586#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15 587#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL 588union uvh_lb_bau_intd_software_acknowledge_u { 589 unsigned long v; 590 struct uvh_lb_bau_intd_software_acknowledge_s { 591 unsigned long pending_0 : 1; /* RW, W1C */ 592 unsigned long pending_1 : 1; /* RW, W1C */ 593 unsigned long pending_2 : 1; /* RW, W1C */ 594 unsigned long pending_3 : 1; /* RW, W1C */ 595 unsigned long pending_4 : 1; /* RW, W1C */ 596 unsigned long pending_5 : 1; /* RW, W1C */ 597 unsigned long pending_6 : 1; /* RW, W1C */ 598 unsigned long pending_7 : 1; /* RW, W1C */ 599 unsigned long timeout_0 : 1; /* RW, W1C */ 600 unsigned long timeout_1 : 1; /* RW, W1C */ 601 unsigned long timeout_2 : 1; /* RW, W1C */ 602 unsigned long timeout_3 : 1; /* RW, W1C */ 603 unsigned long timeout_4 : 1; /* RW, W1C */ 604 unsigned long timeout_5 : 1; /* RW, W1C */ 605 unsigned long timeout_6 : 1; /* RW, W1C */ 606 unsigned long timeout_7 : 1; /* RW, W1C */ 607 unsigned long rsvd_16_63: 48; /* */ 608 } s; 609}; 610 611/* ========================================================================= */ 612/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */ 613/* ========================================================================= */ 614#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL 615#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0x0a70 616 617/* ========================================================================= */ 618/* UVH_LB_BAU_MISC_CONTROL */ 619/* ========================================================================= */ 620#define UVH_LB_BAU_MISC_CONTROL 0x320170UL 621#define UVH_LB_BAU_MISC_CONTROL_32 0x00a10 622 623#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 624#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 625#define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 626#define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 627#define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 628#define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 629#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 630#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 631#define UVH_LB_BAU_MISC_CONTROL_CSI_AGENT_PRESENCE_VECTOR_SHFT 11 632#define UVH_LB_BAU_MISC_CONTROL_CSI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 633#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 634#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 635#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 636#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL 637#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 638#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL 639#define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 640#define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 641#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 642#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 643#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 644#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 645#define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 646#define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 647#define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 648#define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 649#define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 650#define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 651#define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 652#define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 653#define UVH_LB_BAU_MISC_CONTROL_FUN_SHFT 48 654#define UVH_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 655 656union uvh_lb_bau_misc_control_u { 657 unsigned long v; 658 struct uvh_lb_bau_misc_control_s { 659 unsigned long rejection_delay : 8; /* RW */ 660 unsigned long apic_mode : 1; /* RW */ 661 unsigned long force_broadcast : 1; /* RW */ 662 unsigned long force_lock_nop : 1; /* RW */ 663 unsigned long csi_agent_presence_vector : 3; /* RW */ 664 unsigned long descriptor_fetch_mode : 1; /* RW */ 665 unsigned long enable_intd_soft_ack_mode : 1; /* RW */ 666 unsigned long intd_soft_ack_timeout_period : 4; /* RW */ 667 unsigned long enable_dual_mapping_mode : 1; /* RW */ 668 unsigned long vga_io_port_decode_enable : 1; /* RW */ 669 unsigned long vga_io_port_16_bit_decode : 1; /* RW */ 670 unsigned long suppress_dest_registration : 1; /* RW */ 671 unsigned long programmed_initial_priority : 3; /* RW */ 672 unsigned long use_incoming_priority : 1; /* RW */ 673 unsigned long enable_programmed_initial_priority : 1; /* RW */ 674 unsigned long rsvd_29_47 : 19; /* */ 675 unsigned long fun : 16; /* RW */ 676 } s; 677}; 678 679/* ========================================================================= */ 680/* UVH_LB_BAU_SB_ACTIVATION_CONTROL */ 681/* ========================================================================= */ 682#define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL 683#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x009a8 684 685#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0 686#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL 687#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62 688#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL 689#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63 690#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL 691 692union uvh_lb_bau_sb_activation_control_u { 693 unsigned long v; 694 struct uvh_lb_bau_sb_activation_control_s { 695 unsigned long index : 6; /* RW */ 696 unsigned long rsvd_6_61: 56; /* */ 697 unsigned long push : 1; /* WP */ 698 unsigned long init : 1; /* WP */ 699 } s; 700}; 701 702/* ========================================================================= */ 703/* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */ 704/* ========================================================================= */ 705#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL 706#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x009b0 707 708#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0 709#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL 710 711union uvh_lb_bau_sb_activation_status_0_u { 712 unsigned long v; 713 struct uvh_lb_bau_sb_activation_status_0_s { 714 unsigned long status : 64; /* RW */ 715 } s; 716}; 717 718/* ========================================================================= */ 719/* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */ 720/* ========================================================================= */ 721#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL 722#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x009b8 723 724#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0 725#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL 726 727union uvh_lb_bau_sb_activation_status_1_u { 728 unsigned long v; 729 struct uvh_lb_bau_sb_activation_status_1_s { 730 unsigned long status : 64; /* RW */ 731 } s; 732}; 733 734/* ========================================================================= */ 735/* UVH_LB_BAU_SB_DESCRIPTOR_BASE */ 736/* ========================================================================= */ 737#define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL 738#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x009a0 739 740#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12 741#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL 742#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49 743#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL 744 745union uvh_lb_bau_sb_descriptor_base_u { 746 unsigned long v; 747 struct uvh_lb_bau_sb_descriptor_base_s { 748 unsigned long rsvd_0_11 : 12; /* */ 749 unsigned long page_address : 31; /* RW */ 750 unsigned long rsvd_43_48 : 6; /* */ 751 unsigned long node_id : 14; /* RW */ 752 unsigned long rsvd_63 : 1; /* */ 753 } s; 754}; 755 756/* ========================================================================= */ 757/* UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK */ 758/* ========================================================================= */ 759#define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK 0x320130UL 760#define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK_32 0x009f0 761 762#define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0 763#define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL 764 765union uvh_lb_target_physical_apic_id_mask_u { 766 unsigned long v; 767 struct uvh_lb_target_physical_apic_id_mask_s { 768 unsigned long bit_enables : 32; /* RW */ 769 unsigned long rsvd_32_63 : 32; /* */ 770 } s; 771}; 772 773/* ========================================================================= */ 774/* UVH_NODE_ID */ 775/* ========================================================================= */ 776#define UVH_NODE_ID 0x0UL 777 778#define UVH_NODE_ID_FORCE1_SHFT 0 779#define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL 780#define UVH_NODE_ID_MANUFACTURER_SHFT 1 781#define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 782#define UVH_NODE_ID_PART_NUMBER_SHFT 12 783#define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 784#define UVH_NODE_ID_REVISION_SHFT 28 785#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL 786#define UVH_NODE_ID_NODE_ID_SHFT 32 787#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 788#define UVH_NODE_ID_NODES_PER_BIT_SHFT 48 789#define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL 790#define UVH_NODE_ID_NI_PORT_SHFT 56 791#define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL 792 793union uvh_node_id_u { 794 unsigned long v; 795 struct uvh_node_id_s { 796 unsigned long force1 : 1; /* RO */ 797 unsigned long manufacturer : 11; /* RO */ 798 unsigned long part_number : 16; /* RO */ 799 unsigned long revision : 4; /* RO */ 800 unsigned long node_id : 15; /* RW */ 801 unsigned long rsvd_47 : 1; /* */ 802 unsigned long nodes_per_bit : 7; /* RW */ 803 unsigned long rsvd_55 : 1; /* */ 804 unsigned long ni_port : 4; /* RO */ 805 unsigned long rsvd_60_63 : 4; /* */ 806 } s; 807}; 808 809/* ========================================================================= */ 810/* UVH_NODE_PRESENT_TABLE */ 811/* ========================================================================= */ 812#define UVH_NODE_PRESENT_TABLE 0x1400UL 813#define UVH_NODE_PRESENT_TABLE_DEPTH 16 814 815#define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0 816#define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL 817 818union uvh_node_present_table_u { 819 unsigned long v; 820 struct uvh_node_present_table_s { 821 unsigned long nodes : 64; /* RW */ 822 } s; 823}; 824 825/* ========================================================================= */ 826/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR */ 827/* ========================================================================= */ 828#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL 829 830#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 831#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL 832#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 833#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL 834#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63 835#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL 836 837union uvh_rh_gam_alias210_overlay_config_0_mmr_u { 838 unsigned long v; 839 struct uvh_rh_gam_alias210_overlay_config_0_mmr_s { 840 unsigned long rsvd_0_23: 24; /* */ 841 unsigned long base : 8; /* RW */ 842 unsigned long rsvd_32_47: 16; /* */ 843 unsigned long m_alias : 5; /* RW */ 844 unsigned long rsvd_53_62: 10; /* */ 845 unsigned long enable : 1; /* RW */ 846 } s; 847}; 848 849/* ========================================================================= */ 850/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR */ 851/* ========================================================================= */ 852#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL 853 854#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 855#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL 856#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 857#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL 858#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63 859#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL 860 861union uvh_rh_gam_alias210_overlay_config_1_mmr_u { 862 unsigned long v; 863 struct uvh_rh_gam_alias210_overlay_config_1_mmr_s { 864 unsigned long rsvd_0_23: 24; /* */ 865 unsigned long base : 8; /* RW */ 866 unsigned long rsvd_32_47: 16; /* */ 867 unsigned long m_alias : 5; /* RW */ 868 unsigned long rsvd_53_62: 10; /* */ 869 unsigned long enable : 1; /* RW */ 870 } s; 871}; 872 873/* ========================================================================= */ 874/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR */ 875/* ========================================================================= */ 876#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL 877 878#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 879#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL 880#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 881#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL 882#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63 883#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL 884 885union uvh_rh_gam_alias210_overlay_config_2_mmr_u { 886 unsigned long v; 887 struct uvh_rh_gam_alias210_overlay_config_2_mmr_s { 888 unsigned long rsvd_0_23: 24; /* */ 889 unsigned long base : 8; /* RW */ 890 unsigned long rsvd_32_47: 16; /* */ 891 unsigned long m_alias : 5; /* RW */ 892 unsigned long rsvd_53_62: 10; /* */ 893 unsigned long enable : 1; /* RW */ 894 } s; 895}; 896 897/* ========================================================================= */ 898/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */ 899/* ========================================================================= */ 900#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL 901 902#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 903#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL 904 905union uvh_rh_gam_alias210_redirect_config_0_mmr_u { 906 unsigned long v; 907 struct uvh_rh_gam_alias210_redirect_config_0_mmr_s { 908 unsigned long rsvd_0_23 : 24; /* */ 909 unsigned long dest_base : 22; /* RW */ 910 unsigned long rsvd_46_63: 18; /* */ 911 } s; 912}; 913 914/* ========================================================================= */ 915/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */ 916/* ========================================================================= */ 917#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL 918 919#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 920#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL 921 922union uvh_rh_gam_alias210_redirect_config_1_mmr_u { 923 unsigned long v; 924 struct uvh_rh_gam_alias210_redirect_config_1_mmr_s { 925 unsigned long rsvd_0_23 : 24; /* */ 926 unsigned long dest_base : 22; /* RW */ 927 unsigned long rsvd_46_63: 18; /* */ 928 } s; 929}; 930 931/* ========================================================================= */ 932/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */ 933/* ========================================================================= */ 934#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL 935 936#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 937#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL 938 939union uvh_rh_gam_alias210_redirect_config_2_mmr_u { 940 unsigned long v; 941 struct uvh_rh_gam_alias210_redirect_config_2_mmr_s { 942 unsigned long rsvd_0_23 : 24; /* */ 943 unsigned long dest_base : 22; /* RW */ 944 unsigned long rsvd_46_63: 18; /* */ 945 } s; 946}; 947 948/* ========================================================================= */ 949/* UVH_RH_GAM_CONFIG_MMR */ 950/* ========================================================================= */ 951#define UVH_RH_GAM_CONFIG_MMR 0x1600000UL 952 953#define UVH_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 954#define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 955#define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 956#define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 957#define UVH_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT 12 958#define UVH_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL 959 960union uvh_rh_gam_config_mmr_u { 961 unsigned long v; 962 struct uvh_rh_gam_config_mmr_s { 963 unsigned long m_skt : 6; /* RW */ 964 unsigned long n_skt : 4; /* RW */ 965 unsigned long rsvd_10_11: 2; /* */ 966 unsigned long mmiol_cfg : 1; /* RW */ 967 unsigned long rsvd_13_63: 51; /* */ 968 } s; 969}; 970 971/* ========================================================================= */ 972/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */ 973/* ========================================================================= */ 974#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL 975 976#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 977#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 978#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48 979#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL 980#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 981#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 982#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 983#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 984 985union uvh_rh_gam_gru_overlay_config_mmr_u { 986 unsigned long v; 987 struct uvh_rh_gam_gru_overlay_config_mmr_s { 988 unsigned long rsvd_0_27: 28; /* */ 989 unsigned long base : 18; /* RW */ 990 unsigned long rsvd_46_47: 2; /* */ 991 unsigned long gr4 : 1; /* RW */ 992 unsigned long rsvd_49_51: 3; /* */ 993 unsigned long n_gru : 4; /* RW */ 994 unsigned long rsvd_56_62: 7; /* */ 995 unsigned long enable : 1; /* RW */ 996 } s; 997}; 998 999/* ========================================================================= */ 1000/* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR */
1001/* ========================================================================= */ 1002#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL 1003 1004#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30 1005#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL 1006#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 1007#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL 1008#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52 1009#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL 1010#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 1011#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 1012 1013union uvh_rh_gam_mmioh_overlay_config_mmr_u { 1014 unsigned long v; 1015 struct uvh_rh_gam_mmioh_overlay_config_mmr_s { 1016 unsigned long rsvd_0_29: 30; /* */ 1017 unsigned long base : 16; /* RW */ 1018 unsigned long m_io : 6; /* RW */ 1019 unsigned long n_io : 4; /* RW */ 1020 unsigned long rsvd_56_62: 7; /* */ 1021 unsigned long enable : 1; /* RW */ 1022 } s; 1023}; 1024 1025/* ========================================================================= */ 1026/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */ 1027/* ========================================================================= */ 1028#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL 1029 1030#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 1031#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 1032#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46 1033#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL 1034#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 1035#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 1036 1037union uvh_rh_gam_mmr_overlay_config_mmr_u { 1038 unsigned long v; 1039 struct uvh_rh_gam_mmr_overlay_config_mmr_s { 1040 unsigned long rsvd_0_25: 26; /* */ 1041 unsigned long base : 20; /* RW */ 1042 unsigned long dual_hub : 1; /* RW */ 1043 unsigned long rsvd_47_62: 16; /* */ 1044 unsigned long enable : 1; /* RW */ 1045 } s; 1046}; 1047 1048/* ========================================================================= */ 1049/* UVH_RTC */ 1050/* ========================================================================= */ 1051#define UVH_RTC 0x340000UL 1052 1053#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0 1054#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL 1055 1056union uvh_rtc_u { 1057 unsigned long v; 1058 struct uvh_rtc_s { 1059 unsigned long real_time_clock : 56; /* RW */ 1060 unsigned long rsvd_56_63 : 8; /* */ 1061 } s; 1062}; 1063 1064/* ========================================================================= */ 1065/* UVH_RTC1_INT_CONFIG */ 1066/* ========================================================================= */ 1067#define UVH_RTC1_INT_CONFIG 0x615c0UL 1068 1069#define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0 1070#define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL 1071#define UVH_RTC1_INT_CONFIG_DM_SHFT 8 1072#define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL 1073#define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11 1074#define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL 1075#define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12 1076#define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL 1077#define UVH_RTC1_INT_CONFIG_P_SHFT 13 1078#define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL 1079#define UVH_RTC1_INT_CONFIG_T_SHFT 15 1080#define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL 1081#define UVH_RTC1_INT_CONFIG_M_SHFT 16 1082#define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL 1083#define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32 1084#define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 1085 1086union uvh_rtc1_int_config_u { 1087 unsigned long v; 1088 struct uvh_rtc1_int_config_s { 1089 unsigned long vector_ : 8; /* RW */ 1090 unsigned long dm : 3; /* RW */ 1091 unsigned long destmode : 1; /* RW */ 1092 unsigned long status : 1; /* RO */ 1093 unsigned long p : 1; /* RO */ 1094 unsigned long rsvd_14 : 1; /* */ 1095 unsigned long t : 1; /* RO */ 1096 unsigned long m : 1; /* RW */ 1097 unsigned long rsvd_17_31: 15; /* */ 1098 unsigned long apic_id : 32; /* RW */ 1099 } s; 1100}; 1101 1102 1103#endif /* __ASM_UV_MMRS_X86_H__ */ 1104