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35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/dma-mapping.h>
43#include <linux/device.h>
44#include <linux/dmi.h>
45#include <linux/gfp.h>
46#include <scsi/scsi_host.h>
47#include <scsi/scsi_cmnd.h>
48#include <linux/libata.h>
49#include "ahci.h"
50
51#define DRV_NAME "ahci"
52#define DRV_VERSION "3.0"
53
54enum {
55 AHCI_PCI_BAR = 5,
56};
57
58enum board_ids {
59
60 board_ahci,
61 board_ahci_ign_iferr,
62 board_ahci_nosntf,
63 board_ahci_yes_fbs,
64
65
66 board_ahci_mcp65,
67 board_ahci_mcp77,
68 board_ahci_mcp89,
69 board_ahci_mv,
70 board_ahci_sb600,
71 board_ahci_sb700,
72 board_ahci_vt8251,
73
74
75 board_ahci_mcp_linux = board_ahci_mcp65,
76 board_ahci_mcp67 = board_ahci_mcp65,
77 board_ahci_mcp73 = board_ahci_mcp65,
78 board_ahci_mcp79 = board_ahci_mcp77,
79};
80
81static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
82static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
83 unsigned long deadline);
84static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88#ifdef CONFIG_PM
89static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90static int ahci_pci_device_resume(struct pci_dev *pdev);
91#endif
92
93static struct scsi_host_template ahci_sht = {
94 AHCI_SHT("ahci"),
95};
96
97static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
99 .hardreset = ahci_vt8251_hardreset,
100};
101
102static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
104 .hardreset = ahci_p5wdh_hardreset,
105};
106
107static struct ata_port_operations ahci_sb600_ops = {
108 .inherits = &ahci_ops,
109 .softreset = ahci_sb600_softreset,
110 .pmp_softreset = ahci_sb600_softreset,
111};
112
113#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
114
115static const struct ata_port_info ahci_port_info[] = {
116
117 [board_ahci] =
118 {
119 .flags = AHCI_FLAG_COMMON,
120 .pio_mask = ATA_PIO4,
121 .udma_mask = ATA_UDMA6,
122 .port_ops = &ahci_ops,
123 },
124 [board_ahci_ign_iferr] =
125 {
126 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
131 },
132 [board_ahci_nosntf] =
133 {
134 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
135 .flags = AHCI_FLAG_COMMON,
136 .pio_mask = ATA_PIO4,
137 .udma_mask = ATA_UDMA6,
138 .port_ops = &ahci_ops,
139 },
140 [board_ahci_yes_fbs] =
141 {
142 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
143 .flags = AHCI_FLAG_COMMON,
144 .pio_mask = ATA_PIO4,
145 .udma_mask = ATA_UDMA6,
146 .port_ops = &ahci_ops,
147 },
148
149 [board_ahci_mcp65] =
150 {
151 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
152 AHCI_HFLAG_YES_NCQ),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
158 [board_ahci_mcp77] =
159 {
160 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
165 },
166 [board_ahci_mcp89] =
167 {
168 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
169 .flags = AHCI_FLAG_COMMON,
170 .pio_mask = ATA_PIO4,
171 .udma_mask = ATA_UDMA6,
172 .port_ops = &ahci_ops,
173 },
174 [board_ahci_mv] =
175 {
176 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
177 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
178 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
179 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
180 .pio_mask = ATA_PIO4,
181 .udma_mask = ATA_UDMA6,
182 .port_ops = &ahci_ops,
183 },
184 [board_ahci_sb600] =
185 {
186 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
187 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
188 AHCI_HFLAG_32BIT_ONLY),
189 .flags = AHCI_FLAG_COMMON,
190 .pio_mask = ATA_PIO4,
191 .udma_mask = ATA_UDMA6,
192 .port_ops = &ahci_sb600_ops,
193 },
194 [board_ahci_sb700] =
195 {
196 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
197 .flags = AHCI_FLAG_COMMON,
198 .pio_mask = ATA_PIO4,
199 .udma_mask = ATA_UDMA6,
200 .port_ops = &ahci_sb600_ops,
201 },
202 [board_ahci_vt8251] =
203 {
204 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
205 .flags = AHCI_FLAG_COMMON,
206 .pio_mask = ATA_PIO4,
207 .udma_mask = ATA_UDMA6,
208 .port_ops = &ahci_vt8251_ops,
209 },
210};
211
212static const struct pci_device_id ahci_pci_tbl[] = {
213
214 { PCI_VDEVICE(INTEL, 0x2652), board_ahci },
215 { PCI_VDEVICE(INTEL, 0x2653), board_ahci },
216 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci },
217 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci },
218 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci },
219 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr },
220 { PCI_VDEVICE(INTEL, 0x2681), board_ahci },
221 { PCI_VDEVICE(INTEL, 0x2682), board_ahci },
222 { PCI_VDEVICE(INTEL, 0x2683), board_ahci },
223 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci },
224 { PCI_VDEVICE(INTEL, 0x2821), board_ahci },
225 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf },
226 { PCI_VDEVICE(INTEL, 0x2824), board_ahci },
227 { PCI_VDEVICE(INTEL, 0x2829), board_ahci },
228 { PCI_VDEVICE(INTEL, 0x282a), board_ahci },
229 { PCI_VDEVICE(INTEL, 0x2922), board_ahci },
230 { PCI_VDEVICE(INTEL, 0x2923), board_ahci },
231 { PCI_VDEVICE(INTEL, 0x2924), board_ahci },
232 { PCI_VDEVICE(INTEL, 0x2925), board_ahci },
233 { PCI_VDEVICE(INTEL, 0x2927), board_ahci },
234 { PCI_VDEVICE(INTEL, 0x2929), board_ahci },
235 { PCI_VDEVICE(INTEL, 0x292a), board_ahci },
236 { PCI_VDEVICE(INTEL, 0x292b), board_ahci },
237 { PCI_VDEVICE(INTEL, 0x292c), board_ahci },
238 { PCI_VDEVICE(INTEL, 0x292f), board_ahci },
239 { PCI_VDEVICE(INTEL, 0x294d), board_ahci },
240 { PCI_VDEVICE(INTEL, 0x294e), board_ahci },
241 { PCI_VDEVICE(INTEL, 0x502a), board_ahci },
242 { PCI_VDEVICE(INTEL, 0x502b), board_ahci },
243 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci },
244 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci },
245 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci },
246 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci },
247 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci },
248 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci },
249 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci },
250 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci },
251 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci },
252 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci },
253 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci },
254 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci },
255 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci },
256 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci },
257 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci },
258 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci },
259 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci },
260 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci },
261 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci },
262 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci },
263 { PCI_VDEVICE(INTEL, 0x2323), board_ahci },
264
265
266 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
267 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
268
269
270 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 },
271 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 },
272 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 },
273 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 },
274 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 },
275 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 },
276 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 },
277
278
279 { PCI_VDEVICE(AMD, 0x7800), board_ahci },
280
281 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
282 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
283
284
285 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 },
286 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 },
287
288
289 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 },
290 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 },
291 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 },
292 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 },
293 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 },
294 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 },
295 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 },
296 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 },
297 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 },
298 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 },
299 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 },
300 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 },
301 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 },
302 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 },
303 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 },
304 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 },
305 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 },
306 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 },
307 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 },
308 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 },
309 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux },
310 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux },
311 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux },
312 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux },
313 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux },
314 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux },
315 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux },
316 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux },
317 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux },
318 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux },
319 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux },
320 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux },
321 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux },
322 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux },
323 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux },
324 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux },
325 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 },
326 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 },
327 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 },
328 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 },
329 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 },
330 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 },
331 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 },
332 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 },
333 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 },
334 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 },
335 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 },
336 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 },
337 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 },
338 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 },
339 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 },
340 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 },
341 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 },
342 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 },
343 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 },
344 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 },
345 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 },
346 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 },
347 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 },
348 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 },
349 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 },
350 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 },
351 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 },
352 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 },
353 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 },
354 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 },
355 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 },
356 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 },
357 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 },
358 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 },
359 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 },
360 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 },
361 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 },
362 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 },
363 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 },
364 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 },
365 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 },
366 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 },
367 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 },
368 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 },
369 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 },
370 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 },
371 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 },
372 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 },
373
374
375 { PCI_VDEVICE(SI, 0x1184), board_ahci },
376 { PCI_VDEVICE(SI, 0x1185), board_ahci },
377 { PCI_VDEVICE(SI, 0x0186), board_ahci },
378
379
380 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },
381 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv },
382 { PCI_DEVICE(0x1b4b, 0x9123),
383 .class = PCI_CLASS_STORAGE_SATA_AHCI,
384 .class_mask = 0xffffff,
385 .driver_data = board_ahci_yes_fbs },
386
387
388 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci },
389
390
391 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
392 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
393
394 { }
395};
396
397
398static struct pci_driver ahci_pci_driver = {
399 .name = DRV_NAME,
400 .id_table = ahci_pci_tbl,
401 .probe = ahci_init_one,
402 .remove = ata_pci_remove_one,
403#ifdef CONFIG_PM
404 .suspend = ahci_pci_device_suspend,
405 .resume = ahci_pci_device_resume,
406#endif
407};
408
409#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
410static int marvell_enable;
411#else
412static int marvell_enable = 1;
413#endif
414module_param(marvell_enable, int, 0644);
415MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
416
417
418static void ahci_pci_save_initial_config(struct pci_dev *pdev,
419 struct ahci_host_priv *hpriv)
420{
421 unsigned int force_port_map = 0;
422 unsigned int mask_port_map = 0;
423
424 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
425 dev_info(&pdev->dev, "JMB361 has only one port\n");
426 force_port_map = 1;
427 }
428
429
430
431
432
433
434 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
435 if (pdev->device == 0x6121)
436 mask_port_map = 0x3;
437 else
438 mask_port_map = 0xf;
439 dev_info(&pdev->dev,
440 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
441 }
442
443 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
444 mask_port_map);
445}
446
447static int ahci_pci_reset_controller(struct ata_host *host)
448{
449 struct pci_dev *pdev = to_pci_dev(host->dev);
450
451 ahci_reset_controller(host);
452
453 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
454 struct ahci_host_priv *hpriv = host->private_data;
455 u16 tmp16;
456
457
458 pci_read_config_word(pdev, 0x92, &tmp16);
459 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
460 tmp16 |= hpriv->port_map;
461 pci_write_config_word(pdev, 0x92, tmp16);
462 }
463 }
464
465 return 0;
466}
467
468static void ahci_pci_init_controller(struct ata_host *host)
469{
470 struct ahci_host_priv *hpriv = host->private_data;
471 struct pci_dev *pdev = to_pci_dev(host->dev);
472 void __iomem *port_mmio;
473 u32 tmp;
474 int mv;
475
476 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
477 if (pdev->device == 0x6121)
478 mv = 2;
479 else
480 mv = 4;
481 port_mmio = __ahci_port_base(host, mv);
482
483 writel(0, port_mmio + PORT_IRQ_MASK);
484
485
486 tmp = readl(port_mmio + PORT_IRQ_STAT);
487 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
488 if (tmp)
489 writel(tmp, port_mmio + PORT_IRQ_STAT);
490 }
491
492 ahci_init_controller(host);
493}
494
495static int ahci_sb600_check_ready(struct ata_link *link)
496{
497 void __iomem *port_mmio = ahci_port_base(link->ap);
498 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
499 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
500
501
502
503
504
505 if (irq_status & PORT_IRQ_BAD_PMP)
506 return -EIO;
507
508 return ata_check_ready(status);
509}
510
511static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
512 unsigned long deadline)
513{
514 struct ata_port *ap = link->ap;
515 void __iomem *port_mmio = ahci_port_base(ap);
516 int pmp = sata_srst_pmp(link);
517 int rc;
518 u32 irq_sts;
519
520 DPRINTK("ENTER\n");
521
522 rc = ahci_do_softreset(link, class, pmp, deadline,
523 ahci_sb600_check_ready);
524
525
526
527
528
529
530 if (rc == -EIO) {
531 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
532 if (irq_sts & PORT_IRQ_BAD_PMP) {
533 ata_link_printk(link, KERN_WARNING,
534 "applying SB600 PMP SRST workaround "
535 "and retrying\n");
536 rc = ahci_do_softreset(link, class, 0, deadline,
537 ahci_check_ready);
538 }
539 }
540
541 return rc;
542}
543
544static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
545 unsigned long deadline)
546{
547 struct ata_port *ap = link->ap;
548 bool online;
549 int rc;
550
551 DPRINTK("ENTER\n");
552
553 ahci_stop_engine(ap);
554
555 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
556 deadline, &online, NULL);
557
558 ahci_start_engine(ap);
559
560 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
561
562
563
564
565 return online ? -EAGAIN : rc;
566}
567
568static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
569 unsigned long deadline)
570{
571 struct ata_port *ap = link->ap;
572 struct ahci_port_priv *pp = ap->private_data;
573 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
574 struct ata_taskfile tf;
575 bool online;
576 int rc;
577
578 ahci_stop_engine(ap);
579
580
581 ata_tf_init(link->device, &tf);
582 tf.command = 0x80;
583 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
584
585 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
586 deadline, &online, NULL);
587
588 ahci_start_engine(ap);
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603 if (online) {
604 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
605 ahci_check_ready);
606 if (rc)
607 ahci_kick_engine(ap);
608 }
609 return rc;
610}
611
612#ifdef CONFIG_PM
613static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
614{
615 struct ata_host *host = dev_get_drvdata(&pdev->dev);
616 struct ahci_host_priv *hpriv = host->private_data;
617 void __iomem *mmio = hpriv->mmio;
618 u32 ctl;
619
620 if (mesg.event & PM_EVENT_SUSPEND &&
621 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
622 dev_printk(KERN_ERR, &pdev->dev,
623 "BIOS update required for suspend/resume\n");
624 return -EIO;
625 }
626
627 if (mesg.event & PM_EVENT_SLEEP) {
628
629
630
631
632 ctl = readl(mmio + HOST_CTL);
633 ctl &= ~HOST_IRQ_EN;
634 writel(ctl, mmio + HOST_CTL);
635 readl(mmio + HOST_CTL);
636 }
637
638 return ata_pci_device_suspend(pdev, mesg);
639}
640
641static int ahci_pci_device_resume(struct pci_dev *pdev)
642{
643 struct ata_host *host = dev_get_drvdata(&pdev->dev);
644 int rc;
645
646 rc = ata_pci_device_do_resume(pdev);
647 if (rc)
648 return rc;
649
650 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
651 rc = ahci_pci_reset_controller(host);
652 if (rc)
653 return rc;
654
655 ahci_pci_init_controller(host);
656 }
657
658 ata_host_resume(host);
659
660 return 0;
661}
662#endif
663
664static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
665{
666 int rc;
667
668 if (using_dac &&
669 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
670 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
671 if (rc) {
672 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
673 if (rc) {
674 dev_printk(KERN_ERR, &pdev->dev,
675 "64-bit DMA enable failed\n");
676 return rc;
677 }
678 }
679 } else {
680 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
681 if (rc) {
682 dev_printk(KERN_ERR, &pdev->dev,
683 "32-bit DMA enable failed\n");
684 return rc;
685 }
686 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
687 if (rc) {
688 dev_printk(KERN_ERR, &pdev->dev,
689 "32-bit consistent DMA enable failed\n");
690 return rc;
691 }
692 }
693 return 0;
694}
695
696static void ahci_pci_print_info(struct ata_host *host)
697{
698 struct pci_dev *pdev = to_pci_dev(host->dev);
699 u16 cc;
700 const char *scc_s;
701
702 pci_read_config_word(pdev, 0x0a, &cc);
703 if (cc == PCI_CLASS_STORAGE_IDE)
704 scc_s = "IDE";
705 else if (cc == PCI_CLASS_STORAGE_SATA)
706 scc_s = "SATA";
707 else if (cc == PCI_CLASS_STORAGE_RAID)
708 scc_s = "RAID";
709 else
710 scc_s = "unknown";
711
712 ahci_print_info(host, scc_s);
713}
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733static void ahci_p5wdh_workaround(struct ata_host *host)
734{
735 static struct dmi_system_id sysids[] = {
736 {
737 .ident = "P5W DH Deluxe",
738 .matches = {
739 DMI_MATCH(DMI_SYS_VENDOR,
740 "ASUSTEK COMPUTER INC"),
741 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
742 },
743 },
744 { }
745 };
746 struct pci_dev *pdev = to_pci_dev(host->dev);
747
748 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
749 dmi_check_system(sysids)) {
750 struct ata_port *ap = host->ports[1];
751
752 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
753 "Deluxe on-board SIMG4726 workaround\n");
754
755 ap->ops = &ahci_p5wdh_ops;
756 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
757 }
758}
759
760
761static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
762{
763 static const struct dmi_system_id sysids[] = {
764
765
766
767
768
769
770
771 {
772 .ident = "ASUS M2A-VM",
773 .matches = {
774 DMI_MATCH(DMI_BOARD_VENDOR,
775 "ASUSTeK Computer INC."),
776 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
777 },
778 .driver_data = "20071026",
779 },
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796 {
797 .ident = "MSI K9A2 Platinum",
798 .matches = {
799 DMI_MATCH(DMI_BOARD_VENDOR,
800 "MICRO-STAR INTER"),
801 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
802 },
803 },
804 { }
805 };
806 const struct dmi_system_id *match;
807 int year, month, date;
808 char buf[9];
809
810 match = dmi_first_match(sysids);
811 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
812 !match)
813 return false;
814
815 if (!match->driver_data)
816 goto enable_64bit;
817
818 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
819 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
820
821 if (strcmp(buf, match->driver_data) >= 0)
822 goto enable_64bit;
823 else {
824 dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
825 "forcing 32bit DMA, update BIOS\n", match->ident);
826 return false;
827 }
828
829enable_64bit:
830 dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
831 match->ident);
832 return true;
833}
834
835static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
836{
837 static const struct dmi_system_id broken_systems[] = {
838 {
839 .ident = "HP Compaq nx6310",
840 .matches = {
841 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
842 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
843 },
844
845 .driver_data = (void *)0x1FUL,
846 },
847 {
848 .ident = "HP Compaq 6720s",
849 .matches = {
850 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
851 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
852 },
853
854 .driver_data = (void *)0x1FUL,
855 },
856
857 { }
858 };
859 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
860
861 if (dmi) {
862 unsigned long slot = (unsigned long)dmi->driver_data;
863
864 return slot == PCI_SLOT(pdev->devfn);
865 }
866
867 return false;
868}
869
870static bool ahci_broken_suspend(struct pci_dev *pdev)
871{
872 static const struct dmi_system_id sysids[] = {
873
874
875
876
877
878
879
880
881
882
883
884
885
886 {
887 .ident = "dv4",
888 .matches = {
889 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
890 DMI_MATCH(DMI_PRODUCT_NAME,
891 "HP Pavilion dv4 Notebook PC"),
892 },
893 .driver_data = "20090105",
894 },
895 {
896 .ident = "dv5",
897 .matches = {
898 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
899 DMI_MATCH(DMI_PRODUCT_NAME,
900 "HP Pavilion dv5 Notebook PC"),
901 },
902 .driver_data = "20090506",
903 },
904 {
905 .ident = "dv6",
906 .matches = {
907 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
908 DMI_MATCH(DMI_PRODUCT_NAME,
909 "HP Pavilion dv6 Notebook PC"),
910 },
911 .driver_data = "20090423",
912 },
913 {
914 .ident = "HDX18",
915 .matches = {
916 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
917 DMI_MATCH(DMI_PRODUCT_NAME,
918 "HP HDX18 Notebook PC"),
919 },
920 .driver_data = "20090430",
921 },
922
923
924
925
926
927
928
929
930
931 {
932 .ident = "G725",
933 .matches = {
934 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
935 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
936 },
937 .driver_data = "20091216",
938 },
939 { }
940 };
941 const struct dmi_system_id *dmi = dmi_first_match(sysids);
942 int year, month, date;
943 char buf[9];
944
945 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
946 return false;
947
948 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
949 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
950
951 return strcmp(buf, dmi->driver_data) < 0;
952}
953
954static bool ahci_broken_online(struct pci_dev *pdev)
955{
956#define ENCODE_BUSDEVFN(bus, slot, func) \
957 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
958 static const struct dmi_system_id sysids[] = {
959
960
961
962
963
964
965
966
967
968
969
970
971
972 {
973 .ident = "EP45-DQ6",
974 .matches = {
975 DMI_MATCH(DMI_BOARD_VENDOR,
976 "Gigabyte Technology Co., Ltd."),
977 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
978 },
979 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
980 },
981 {
982 .ident = "EP45-DS5",
983 .matches = {
984 DMI_MATCH(DMI_BOARD_VENDOR,
985 "Gigabyte Technology Co., Ltd."),
986 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
987 },
988 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
989 },
990 { }
991 };
992#undef ENCODE_BUSDEVFN
993 const struct dmi_system_id *dmi = dmi_first_match(sysids);
994 unsigned int val;
995
996 if (!dmi)
997 return false;
998
999 val = (unsigned long)dmi->driver_data;
1000
1001 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1002}
1003
1004#ifdef CONFIG_ATA_ACPI
1005static void ahci_gtf_filter_workaround(struct ata_host *host)
1006{
1007 static const struct dmi_system_id sysids[] = {
1008
1009
1010
1011
1012
1013
1014
1015
1016 {
1017 .ident = "Aspire 3810T",
1018 .matches = {
1019 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1020 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1021 },
1022 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1023 },
1024 { }
1025 };
1026 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1027 unsigned int filter;
1028 int i;
1029
1030 if (!dmi)
1031 return;
1032
1033 filter = (unsigned long)dmi->driver_data;
1034 dev_printk(KERN_INFO, host->dev,
1035 "applying extra ACPI _GTF filter 0x%x for %s\n",
1036 filter, dmi->ident);
1037
1038 for (i = 0; i < host->n_ports; i++) {
1039 struct ata_port *ap = host->ports[i];
1040 struct ata_link *link;
1041 struct ata_device *dev;
1042
1043 ata_for_each_link(link, ap, EDGE)
1044 ata_for_each_dev(dev, link, ALL)
1045 dev->gtf_filter |= filter;
1046 }
1047}
1048#else
1049static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1050{}
1051#endif
1052
1053static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1054{
1055 static int printed_version;
1056 unsigned int board_id = ent->driver_data;
1057 struct ata_port_info pi = ahci_port_info[board_id];
1058 const struct ata_port_info *ppi[] = { &pi, NULL };
1059 struct device *dev = &pdev->dev;
1060 struct ahci_host_priv *hpriv;
1061 struct ata_host *host;
1062 int n_ports, i, rc;
1063
1064 VPRINTK("ENTER\n");
1065
1066 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1067
1068 if (!printed_version++)
1069 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1070
1071
1072
1073
1074 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1075 return -ENODEV;
1076
1077
1078
1079
1080
1081 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1082 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1083 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1084 pdev->subsystem_device == 0xcb89)
1085 return -ENODEV;
1086
1087
1088
1089
1090
1091 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1092 dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
1093 "can only drive SATA devices with this driver\n");
1094
1095
1096 rc = pcim_enable_device(pdev);
1097 if (rc)
1098 return rc;
1099
1100
1101
1102
1103 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1104 if (rc == -EBUSY)
1105 pcim_pin_device(pdev);
1106 if (rc)
1107 return rc;
1108
1109 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1110 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1111 u8 map;
1112
1113
1114
1115
1116
1117 pci_read_config_byte(pdev, ICH_MAP, &map);
1118 if (map & 0x3) {
1119 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
1120 "combined mode, can't enable AHCI mode\n");
1121 return -ENODEV;
1122 }
1123 }
1124
1125 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1126 if (!hpriv)
1127 return -ENOMEM;
1128 hpriv->flags |= (unsigned long)pi.private_data;
1129
1130
1131 if (board_id == board_ahci_mcp65 &&
1132 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1133 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1134
1135
1136 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1137 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1138
1139
1140 if (ahci_sb600_enable_64bit(pdev))
1141 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1142
1143 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1144 pci_intx(pdev, 1);
1145
1146 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1147
1148
1149 ahci_pci_save_initial_config(pdev, hpriv);
1150
1151
1152 if (hpriv->cap & HOST_CAP_NCQ) {
1153 pi.flags |= ATA_FLAG_NCQ;
1154
1155
1156
1157
1158
1159
1160 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1161 pi.flags |= ATA_FLAG_FPDMA_AA;
1162 }
1163
1164 if (hpriv->cap & HOST_CAP_PMP)
1165 pi.flags |= ATA_FLAG_PMP;
1166
1167 ahci_set_em_messages(hpriv, &pi);
1168
1169 if (ahci_broken_system_poweroff(pdev)) {
1170 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1171 dev_info(&pdev->dev,
1172 "quirky BIOS, skipping spindown on poweroff\n");
1173 }
1174
1175 if (ahci_broken_suspend(pdev)) {
1176 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1177 dev_printk(KERN_WARNING, &pdev->dev,
1178 "BIOS update required for suspend/resume\n");
1179 }
1180
1181 if (ahci_broken_online(pdev)) {
1182 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1183 dev_info(&pdev->dev,
1184 "online status unreliable, applying workaround\n");
1185 }
1186
1187
1188
1189
1190
1191
1192 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1193
1194 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1195 if (!host)
1196 return -ENOMEM;
1197 host->private_data = hpriv;
1198
1199 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1200 host->flags |= ATA_HOST_PARALLEL_SCAN;
1201 else
1202 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1203
1204 if (pi.flags & ATA_FLAG_EM)
1205 ahci_reset_em(host);
1206
1207 for (i = 0; i < host->n_ports; i++) {
1208 struct ata_port *ap = host->ports[i];
1209
1210 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1211 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1212 0x100 + ap->port_no * 0x80, "port");
1213
1214
1215 if (ap->flags & ATA_FLAG_EM)
1216 ap->em_message_type = hpriv->em_msg_type;
1217
1218
1219
1220 if (!(hpriv->port_map & (1 << i)))
1221 ap->ops = &ata_dummy_port_ops;
1222 }
1223
1224
1225 ahci_p5wdh_workaround(host);
1226
1227
1228 ahci_gtf_filter_workaround(host);
1229
1230
1231 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1232 if (rc)
1233 return rc;
1234
1235 rc = ahci_pci_reset_controller(host);
1236 if (rc)
1237 return rc;
1238
1239 ahci_pci_init_controller(host);
1240 ahci_pci_print_info(host);
1241
1242 pci_set_master(pdev);
1243 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1244 &ahci_sht);
1245}
1246
1247static int __init ahci_init(void)
1248{
1249 return pci_register_driver(&ahci_pci_driver);
1250}
1251
1252static void __exit ahci_exit(void)
1253{
1254 pci_unregister_driver(&ahci_pci_driver);
1255}
1256
1257
1258MODULE_AUTHOR("Jeff Garzik");
1259MODULE_DESCRIPTION("AHCI SATA low-level driver");
1260MODULE_LICENSE("GPL");
1261MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1262MODULE_VERSION(DRV_VERSION);
1263
1264module_init(ahci_init);
1265module_exit(ahci_exit);
1266