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35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/device.h>
42#include <scsi/scsi_host.h>
43#include <linux/libata.h>
44
45#define DRV_NAME "pata_scc"
46#define DRV_VERSION "0.3"
47
48#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
49
50
51#define SCC_CTRL_BAR 0
52#define SCC_BMID_BAR 1
53
54
55#define SCC_CTL_PIOSHT 0x000
56#define SCC_CTL_PIOCT 0x004
57#define SCC_CTL_MDMACT 0x008
58#define SCC_CTL_MCRCST 0x00C
59#define SCC_CTL_SDMACT 0x010
60#define SCC_CTL_SCRCST 0x014
61#define SCC_CTL_UDENVT 0x018
62#define SCC_CTL_TDVHSEL 0x020
63#define SCC_CTL_MODEREG 0x024
64#define SCC_CTL_ECMODE 0xF00
65#define SCC_CTL_MAEA0 0xF50
66#define SCC_CTL_MAEC0 0xF54
67#define SCC_CTL_CCKCTRL 0xFF0
68
69
70#define SCC_DMA_CMD 0x000
71#define SCC_DMA_STATUS 0x004
72#define SCC_DMA_TABLE_OFS 0x008
73#define SCC_DMA_INTMASK 0x010
74#define SCC_DMA_INTST 0x014
75#define SCC_DMA_PTERADD 0x018
76#define SCC_REG_CMD_ADDR 0x020
77#define SCC_REG_DATA 0x000
78#define SCC_REG_ERR 0x004
79#define SCC_REG_FEATURE 0x004
80#define SCC_REG_NSECT 0x008
81#define SCC_REG_LBAL 0x00C
82#define SCC_REG_LBAM 0x010
83#define SCC_REG_LBAH 0x014
84#define SCC_REG_DEVICE 0x018
85#define SCC_REG_STATUS 0x01C
86#define SCC_REG_CMD 0x01C
87#define SCC_REG_ALTSTATUS 0x020
88
89
90#define TDVHSEL_MASTER 0x00000001
91#define TDVHSEL_SLAVE 0x00000004
92
93#define MODE_JCUSFEN 0x00000080
94
95#define ECMODE_VALUE 0x01
96
97#define CCKCTRL_ATARESET 0x00040000
98#define CCKCTRL_BUFCNT 0x00020000
99#define CCKCTRL_CRST 0x00010000
100#define CCKCTRL_OCLKEN 0x00000100
101#define CCKCTRL_ATACLKOEN 0x00000002
102#define CCKCTRL_LCLKEN 0x00000001
103
104#define QCHCD_IOS_SS 0x00000001
105
106#define QCHSD_STPDIAG 0x00020000
107
108#define INTMASK_MSK 0xD1000012
109#define INTSTS_SERROR 0x80000000
110#define INTSTS_PRERR 0x40000000
111#define INTSTS_RERR 0x10000000
112#define INTSTS_ICERR 0x01000000
113#define INTSTS_BMSINT 0x00000010
114#define INTSTS_BMHE 0x00000008
115#define INTSTS_IOIRQS 0x00000004
116#define INTSTS_INTRQ 0x00000002
117#define INTSTS_ACTEINT 0x00000001
118
119
120
121
122static const unsigned long JCHSTtbl[2][7] = {
123 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00},
124 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00}
125};
126
127
128static const unsigned long JCHHTtbl[2][7] = {
129 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00},
130 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00}
131};
132
133
134static const unsigned long JCHCTtbl[2][7] = {
135 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00},
136 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00}
137};
138
139
140
141static const unsigned long JCHDCTxtbl[2][7] = {
142 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00},
143 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00}
144};
145
146
147static const unsigned long JCSTWTxtbl[2][7] = {
148 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00},
149 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02}
150};
151
152
153static const unsigned long JCTSStbl[2][7] = {
154 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00},
155 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05}
156};
157
158
159static const unsigned long JCENVTtbl[2][7] = {
160 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00},
161 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}
162};
163
164
165static const unsigned long JCACTSELtbl[2][7] = {
166 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00},
167 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01}
168};
169
170static const struct pci_device_id scc_pci_tbl[] = {
171 { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0},
172 { }
173};
174
175
176
177
178
179
180
181
182
183
184
185
186static void scc_set_piomode (struct ata_port *ap, struct ata_device *adev)
187{
188 unsigned int pio = adev->pio_mode - XFER_PIO_0;
189 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
190 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
191 void __iomem *piosht_port = ctrl_base + SCC_CTL_PIOSHT;
192 void __iomem *pioct_port = ctrl_base + SCC_CTL_PIOCT;
193 unsigned long reg;
194 int offset;
195
196 reg = in_be32(cckctrl_port);
197 if (reg & CCKCTRL_ATACLKOEN)
198 offset = 1;
199 else
200 offset = 0;
201
202 reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
203 out_be32(piosht_port, reg);
204 reg = JCHCTtbl[offset][pio];
205 out_be32(pioct_port, reg);
206}
207
208
209
210
211
212
213
214
215
216
217
218
219static void scc_set_dmamode (struct ata_port *ap, struct ata_device *adev)
220{
221 unsigned int udma = adev->dma_mode;
222 unsigned int is_slave = (adev->devno != 0);
223 u8 speed = udma;
224 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
225 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
226 void __iomem *mdmact_port = ctrl_base + SCC_CTL_MDMACT;
227 void __iomem *mcrcst_port = ctrl_base + SCC_CTL_MCRCST;
228 void __iomem *sdmact_port = ctrl_base + SCC_CTL_SDMACT;
229 void __iomem *scrcst_port = ctrl_base + SCC_CTL_SCRCST;
230 void __iomem *udenvt_port = ctrl_base + SCC_CTL_UDENVT;
231 void __iomem *tdvhsel_port = ctrl_base + SCC_CTL_TDVHSEL;
232 int offset, idx;
233
234 if (in_be32(cckctrl_port) & CCKCTRL_ATACLKOEN)
235 offset = 1;
236 else
237 offset = 0;
238
239 if (speed >= XFER_UDMA_0)
240 idx = speed - XFER_UDMA_0;
241 else
242 return;
243
244 if (is_slave) {
245 out_be32(sdmact_port, JCHDCTxtbl[offset][idx]);
246 out_be32(scrcst_port, JCSTWTxtbl[offset][idx]);
247 out_be32(tdvhsel_port,
248 (in_be32(tdvhsel_port) & ~TDVHSEL_SLAVE) | (JCACTSELtbl[offset][idx] << 2));
249 } else {
250 out_be32(mdmact_port, JCHDCTxtbl[offset][idx]);
251 out_be32(mcrcst_port, JCSTWTxtbl[offset][idx]);
252 out_be32(tdvhsel_port,
253 (in_be32(tdvhsel_port) & ~TDVHSEL_MASTER) | JCACTSELtbl[offset][idx]);
254 }
255 out_be32(udenvt_port,
256 JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx]);
257}
258
259unsigned long scc_mode_filter(struct ata_device *adev, unsigned long mask)
260{
261
262 if (adev->class == ATA_DEV_ATAPI &&
263 (mask & (0xE0 << ATA_SHIFT_UDMA))) {
264 printk(KERN_INFO "%s: limit ATAPI UDMA to UDMA4\n", DRV_NAME);
265 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
266 }
267 return mask;
268}
269
270
271
272
273
274
275
276
277
278static void scc_tf_load (struct ata_port *ap, const struct ata_taskfile *tf)
279{
280 struct ata_ioports *ioaddr = &ap->ioaddr;
281 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
282
283 if (tf->ctl != ap->last_ctl) {
284 out_be32(ioaddr->ctl_addr, tf->ctl);
285 ap->last_ctl = tf->ctl;
286 ata_wait_idle(ap);
287 }
288
289 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
290 out_be32(ioaddr->feature_addr, tf->hob_feature);
291 out_be32(ioaddr->nsect_addr, tf->hob_nsect);
292 out_be32(ioaddr->lbal_addr, tf->hob_lbal);
293 out_be32(ioaddr->lbam_addr, tf->hob_lbam);
294 out_be32(ioaddr->lbah_addr, tf->hob_lbah);
295 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
296 tf->hob_feature,
297 tf->hob_nsect,
298 tf->hob_lbal,
299 tf->hob_lbam,
300 tf->hob_lbah);
301 }
302
303 if (is_addr) {
304 out_be32(ioaddr->feature_addr, tf->feature);
305 out_be32(ioaddr->nsect_addr, tf->nsect);
306 out_be32(ioaddr->lbal_addr, tf->lbal);
307 out_be32(ioaddr->lbam_addr, tf->lbam);
308 out_be32(ioaddr->lbah_addr, tf->lbah);
309 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
310 tf->feature,
311 tf->nsect,
312 tf->lbal,
313 tf->lbam,
314 tf->lbah);
315 }
316
317 if (tf->flags & ATA_TFLAG_DEVICE) {
318 out_be32(ioaddr->device_addr, tf->device);
319 VPRINTK("device 0x%X\n", tf->device);
320 }
321
322 ata_wait_idle(ap);
323}
324
325
326
327
328
329
330
331
332static u8 scc_check_status (struct ata_port *ap)
333{
334 return in_be32(ap->ioaddr.status_addr);
335}
336
337
338
339
340
341
342
343
344
345static void scc_tf_read (struct ata_port *ap, struct ata_taskfile *tf)
346{
347 struct ata_ioports *ioaddr = &ap->ioaddr;
348
349 tf->command = scc_check_status(ap);
350 tf->feature = in_be32(ioaddr->error_addr);
351 tf->nsect = in_be32(ioaddr->nsect_addr);
352 tf->lbal = in_be32(ioaddr->lbal_addr);
353 tf->lbam = in_be32(ioaddr->lbam_addr);
354 tf->lbah = in_be32(ioaddr->lbah_addr);
355 tf->device = in_be32(ioaddr->device_addr);
356
357 if (tf->flags & ATA_TFLAG_LBA48) {
358 out_be32(ioaddr->ctl_addr, tf->ctl | ATA_HOB);
359 tf->hob_feature = in_be32(ioaddr->error_addr);
360 tf->hob_nsect = in_be32(ioaddr->nsect_addr);
361 tf->hob_lbal = in_be32(ioaddr->lbal_addr);
362 tf->hob_lbam = in_be32(ioaddr->lbam_addr);
363 tf->hob_lbah = in_be32(ioaddr->lbah_addr);
364 out_be32(ioaddr->ctl_addr, tf->ctl);
365 ap->last_ctl = tf->ctl;
366 }
367}
368
369
370
371
372
373
374
375
376
377static void scc_exec_command (struct ata_port *ap,
378 const struct ata_taskfile *tf)
379{
380 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
381
382 out_be32(ap->ioaddr.command_addr, tf->command);
383 ata_sff_pause(ap);
384}
385
386
387
388
389
390
391static u8 scc_check_altstatus (struct ata_port *ap)
392{
393 return in_be32(ap->ioaddr.altstatus_addr);
394}
395
396
397
398
399
400
401
402
403
404static void scc_dev_select (struct ata_port *ap, unsigned int device)
405{
406 u8 tmp;
407
408 if (device == 0)
409 tmp = ATA_DEVICE_OBS;
410 else
411 tmp = ATA_DEVICE_OBS | ATA_DEV1;
412
413 out_be32(ap->ioaddr.device_addr, tmp);
414 ata_sff_pause(ap);
415}
416
417
418
419
420
421
422
423static void scc_set_devctl(struct ata_port *ap, u8 ctl)
424{
425 out_be32(ap->ioaddr.ctl_addr, ctl);
426}
427
428
429
430
431
432
433
434
435static void scc_bmdma_setup (struct ata_queued_cmd *qc)
436{
437 struct ata_port *ap = qc->ap;
438 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
439 u8 dmactl;
440 void __iomem *mmio = ap->ioaddr.bmdma_addr;
441
442
443 out_be32(mmio + SCC_DMA_TABLE_OFS, ap->bmdma_prd_dma);
444
445
446 dmactl = in_be32(mmio + SCC_DMA_CMD);
447 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
448 if (!rw)
449 dmactl |= ATA_DMA_WR;
450 out_be32(mmio + SCC_DMA_CMD, dmactl);
451
452
453 ap->ops->sff_exec_command(ap, &qc->tf);
454}
455
456
457
458
459
460
461
462
463static void scc_bmdma_start (struct ata_queued_cmd *qc)
464{
465 struct ata_port *ap = qc->ap;
466 u8 dmactl;
467 void __iomem *mmio = ap->ioaddr.bmdma_addr;
468
469
470 dmactl = in_be32(mmio + SCC_DMA_CMD);
471 out_be32(mmio + SCC_DMA_CMD, dmactl | ATA_DMA_START);
472}
473
474
475
476
477
478
479
480
481
482static unsigned int scc_devchk (struct ata_port *ap,
483 unsigned int device)
484{
485 struct ata_ioports *ioaddr = &ap->ioaddr;
486 u8 nsect, lbal;
487
488 ap->ops->sff_dev_select(ap, device);
489
490 out_be32(ioaddr->nsect_addr, 0x55);
491 out_be32(ioaddr->lbal_addr, 0xaa);
492
493 out_be32(ioaddr->nsect_addr, 0xaa);
494 out_be32(ioaddr->lbal_addr, 0x55);
495
496 out_be32(ioaddr->nsect_addr, 0x55);
497 out_be32(ioaddr->lbal_addr, 0xaa);
498
499 nsect = in_be32(ioaddr->nsect_addr);
500 lbal = in_be32(ioaddr->lbal_addr);
501
502 if ((nsect == 0x55) && (lbal == 0xaa))
503 return 1;
504
505 return 0;
506}
507
508
509
510
511
512
513
514static int scc_wait_after_reset(struct ata_link *link, unsigned int devmask,
515 unsigned long deadline)
516{
517 struct ata_port *ap = link->ap;
518 struct ata_ioports *ioaddr = &ap->ioaddr;
519 unsigned int dev0 = devmask & (1 << 0);
520 unsigned int dev1 = devmask & (1 << 1);
521 int rc, ret = 0;
522
523
524
525
526
527
528
529
530
531
532
533 ata_msleep(ap, 150);
534
535
536 rc = ata_sff_wait_ready(link, deadline);
537
538
539
540 if (rc)
541 return rc;
542
543
544
545
546 if (dev1) {
547 int i;
548
549 ap->ops->sff_dev_select(ap, 1);
550
551
552
553
554
555 for (i = 0; i < 2; i++) {
556 u8 nsect, lbal;
557
558 nsect = in_be32(ioaddr->nsect_addr);
559 lbal = in_be32(ioaddr->lbal_addr);
560 if ((nsect == 1) && (lbal == 1))
561 break;
562 ata_msleep(ap, 50);
563 }
564
565 rc = ata_sff_wait_ready(link, deadline);
566 if (rc) {
567 if (rc != -ENODEV)
568 return rc;
569 ret = rc;
570 }
571 }
572
573
574 ap->ops->sff_dev_select(ap, 0);
575 if (dev1)
576 ap->ops->sff_dev_select(ap, 1);
577 if (dev0)
578 ap->ops->sff_dev_select(ap, 0);
579
580 return ret;
581}
582
583
584
585
586
587
588
589static unsigned int scc_bus_softreset(struct ata_port *ap, unsigned int devmask,
590 unsigned long deadline)
591{
592 struct ata_ioports *ioaddr = &ap->ioaddr;
593
594 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
595
596
597 out_be32(ioaddr->ctl_addr, ap->ctl);
598 udelay(20);
599 out_be32(ioaddr->ctl_addr, ap->ctl | ATA_SRST);
600 udelay(20);
601 out_be32(ioaddr->ctl_addr, ap->ctl);
602
603 scc_wait_after_reset(&ap->link, devmask, deadline);
604
605 return 0;
606}
607
608
609
610
611
612
613
614
615
616
617static int scc_softreset(struct ata_link *link, unsigned int *classes,
618 unsigned long deadline)
619{
620 struct ata_port *ap = link->ap;
621 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
622 unsigned int devmask = 0, err_mask;
623 u8 err;
624
625 DPRINTK("ENTER\n");
626
627
628 if (scc_devchk(ap, 0))
629 devmask |= (1 << 0);
630 if (slave_possible && scc_devchk(ap, 1))
631 devmask |= (1 << 1);
632
633
634 ap->ops->sff_dev_select(ap, 0);
635
636
637 DPRINTK("about to softreset, devmask=%x\n", devmask);
638 err_mask = scc_bus_softreset(ap, devmask, deadline);
639 if (err_mask) {
640 ata_port_printk(ap, KERN_ERR, "SRST failed (err_mask=0x%x)\n",
641 err_mask);
642 return -EIO;
643 }
644
645
646 classes[0] = ata_sff_dev_classify(&ap->link.device[0],
647 devmask & (1 << 0), &err);
648 if (slave_possible && err != 0x81)
649 classes[1] = ata_sff_dev_classify(&ap->link.device[1],
650 devmask & (1 << 1), &err);
651
652 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
653 return 0;
654}
655
656
657
658
659
660
661static void scc_bmdma_stop (struct ata_queued_cmd *qc)
662{
663 struct ata_port *ap = qc->ap;
664 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
665 void __iomem *bmid_base = ap->host->iomap[SCC_BMID_BAR];
666 u32 reg;
667
668 while (1) {
669 reg = in_be32(bmid_base + SCC_DMA_INTST);
670
671 if (reg & INTSTS_SERROR) {
672 printk(KERN_WARNING "%s: SERROR\n", DRV_NAME);
673 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_SERROR|INTSTS_BMSINT);
674 out_be32(bmid_base + SCC_DMA_CMD,
675 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
676 continue;
677 }
678
679 if (reg & INTSTS_PRERR) {
680 u32 maea0, maec0;
681 maea0 = in_be32(ctrl_base + SCC_CTL_MAEA0);
682 maec0 = in_be32(ctrl_base + SCC_CTL_MAEC0);
683 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", DRV_NAME, maea0, maec0);
684 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_PRERR|INTSTS_BMSINT);
685 out_be32(bmid_base + SCC_DMA_CMD,
686 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
687 continue;
688 }
689
690 if (reg & INTSTS_RERR) {
691 printk(KERN_WARNING "%s: Response Error\n", DRV_NAME);
692 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_RERR|INTSTS_BMSINT);
693 out_be32(bmid_base + SCC_DMA_CMD,
694 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
695 continue;
696 }
697
698 if (reg & INTSTS_ICERR) {
699 out_be32(bmid_base + SCC_DMA_CMD,
700 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
701 printk(KERN_WARNING "%s: Illegal Configuration\n", DRV_NAME);
702 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ICERR|INTSTS_BMSINT);
703 continue;
704 }
705
706 if (reg & INTSTS_BMSINT) {
707 unsigned int classes;
708 unsigned long deadline = ata_deadline(jiffies, ATA_TMOUT_BOOT);
709 printk(KERN_WARNING "%s: Internal Bus Error\n", DRV_NAME);
710 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMSINT);
711
712 scc_softreset(&ap->link, &classes, deadline);
713 continue;
714 }
715
716 if (reg & INTSTS_BMHE) {
717 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMHE);
718 continue;
719 }
720
721 if (reg & INTSTS_ACTEINT) {
722 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ACTEINT);
723 continue;
724 }
725
726 if (reg & INTSTS_IOIRQS) {
727 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_IOIRQS);
728 continue;
729 }
730 break;
731 }
732
733
734 out_be32(bmid_base + SCC_DMA_CMD,
735 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
736
737
738 ata_sff_dma_pause(ap);
739}
740
741
742
743
744
745
746static u8 scc_bmdma_status (struct ata_port *ap)
747{
748 void __iomem *mmio = ap->ioaddr.bmdma_addr;
749 u8 host_stat = in_be32(mmio + SCC_DMA_STATUS);
750 u32 int_status = in_be32(mmio + SCC_DMA_INTST);
751 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
752 static int retry = 0;
753
754
755 if (!(in_be32(mmio + SCC_DMA_CMD) & ATA_DMA_START))
756 return host_stat;
757
758
759 if ((scc_check_altstatus(ap) & ATA_ERR)
760 && (int_status & INTSTS_INTRQ))
761 return (host_stat | ATA_DMA_INTR);
762
763
764 if (int_status & INTSTS_IOIRQS) {
765 host_stat |= ATA_DMA_INTR;
766
767
768 if ((qc->tf.protocol == ATA_PROT_DMA &&
769 qc->dev->xfer_mode > XFER_UDMA_4)) {
770 if (!(int_status & INTSTS_ACTEINT)) {
771 printk(KERN_WARNING "ata%u: operation failed (transfer data loss)\n",
772 ap->print_id);
773 host_stat |= ATA_DMA_ERR;
774 if (retry++)
775 ap->udma_mask &= ~(1 << qc->dev->xfer_mode);
776 } else
777 retry = 0;
778 }
779 }
780
781 return host_stat;
782}
783
784
785
786
787
788
789
790
791
792
793
794static unsigned int scc_data_xfer (struct ata_device *dev, unsigned char *buf,
795 unsigned int buflen, int rw)
796{
797 struct ata_port *ap = dev->link->ap;
798 unsigned int words = buflen >> 1;
799 unsigned int i;
800 __le16 *buf16 = (__le16 *) buf;
801 void __iomem *mmio = ap->ioaddr.data_addr;
802
803
804 if (rw == READ)
805 for (i = 0; i < words; i++)
806 buf16[i] = cpu_to_le16(in_be32(mmio));
807 else
808 for (i = 0; i < words; i++)
809 out_be32(mmio, le16_to_cpu(buf16[i]));
810
811
812 if (unlikely(buflen & 0x01)) {
813 __le16 align_buf[1] = { 0 };
814 unsigned char *trailing_buf = buf + buflen - 1;
815
816 if (rw == READ) {
817 align_buf[0] = cpu_to_le16(in_be32(mmio));
818 memcpy(trailing_buf, align_buf, 1);
819 } else {
820 memcpy(align_buf, trailing_buf, 1);
821 out_be32(mmio, le16_to_cpu(align_buf[0]));
822 }
823 words++;
824 }
825
826 return words << 1;
827}
828
829
830
831
832
833
834
835static int scc_pata_prereset(struct ata_link *link, unsigned long deadline)
836{
837 link->ap->cbl = ATA_CBL_PATA80;
838 return ata_sff_prereset(link, deadline);
839}
840
841
842
843
844
845
846
847
848
849static void scc_postreset(struct ata_link *link, unsigned int *classes)
850{
851 struct ata_port *ap = link->ap;
852
853 DPRINTK("ENTER\n");
854
855
856 if (classes[0] != ATA_DEV_NONE)
857 ap->ops->sff_dev_select(ap, 1);
858 if (classes[1] != ATA_DEV_NONE)
859 ap->ops->sff_dev_select(ap, 0);
860
861
862 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
863 DPRINTK("EXIT, no device\n");
864 return;
865 }
866
867
868 out_be32(ap->ioaddr.ctl_addr, ap->ctl);
869
870 DPRINTK("EXIT\n");
871}
872
873
874
875
876
877
878
879
880static void scc_irq_clear (struct ata_port *ap)
881{
882 void __iomem *mmio = ap->ioaddr.bmdma_addr;
883
884 if (!mmio)
885 return;
886
887 out_be32(mmio + SCC_DMA_STATUS, in_be32(mmio + SCC_DMA_STATUS));
888}
889
890
891
892
893
894
895
896
897
898static int scc_port_start (struct ata_port *ap)
899{
900 void __iomem *mmio = ap->ioaddr.bmdma_addr;
901 int rc;
902
903 rc = ata_bmdma_port_start(ap);
904 if (rc)
905 return rc;
906
907 out_be32(mmio + SCC_DMA_PTERADD, ap->bmdma_prd_dma);
908 return 0;
909}
910
911
912
913
914
915
916
917
918static void scc_port_stop (struct ata_port *ap)
919{
920 void __iomem *mmio = ap->ioaddr.bmdma_addr;
921
922 out_be32(mmio + SCC_DMA_PTERADD, 0);
923}
924
925static struct scsi_host_template scc_sht = {
926 ATA_BMDMA_SHT(DRV_NAME),
927};
928
929static struct ata_port_operations scc_pata_ops = {
930 .inherits = &ata_bmdma_port_ops,
931
932 .set_piomode = scc_set_piomode,
933 .set_dmamode = scc_set_dmamode,
934 .mode_filter = scc_mode_filter,
935
936 .sff_tf_load = scc_tf_load,
937 .sff_tf_read = scc_tf_read,
938 .sff_exec_command = scc_exec_command,
939 .sff_check_status = scc_check_status,
940 .sff_check_altstatus = scc_check_altstatus,
941 .sff_dev_select = scc_dev_select,
942 .sff_set_devctl = scc_set_devctl,
943
944 .bmdma_setup = scc_bmdma_setup,
945 .bmdma_start = scc_bmdma_start,
946 .bmdma_stop = scc_bmdma_stop,
947 .bmdma_status = scc_bmdma_status,
948 .sff_data_xfer = scc_data_xfer,
949
950 .prereset = scc_pata_prereset,
951 .softreset = scc_softreset,
952 .postreset = scc_postreset,
953
954 .sff_irq_clear = scc_irq_clear,
955
956 .port_start = scc_port_start,
957 .port_stop = scc_port_stop,
958};
959
960static struct ata_port_info scc_port_info[] = {
961 {
962 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_MMIO | ATA_FLAG_NO_LEGACY,
963 .pio_mask = ATA_PIO4,
964
965 .udma_mask = ATA_UDMA6,
966 .port_ops = &scc_pata_ops,
967 },
968};
969
970
971
972
973
974static int scc_reset_controller(struct ata_host *host)
975{
976 void __iomem *ctrl_base = host->iomap[SCC_CTRL_BAR];
977 void __iomem *bmid_base = host->iomap[SCC_BMID_BAR];
978 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
979 void __iomem *mode_port = ctrl_base + SCC_CTL_MODEREG;
980 void __iomem *ecmode_port = ctrl_base + SCC_CTL_ECMODE;
981 void __iomem *intmask_port = bmid_base + SCC_DMA_INTMASK;
982 void __iomem *dmastatus_port = bmid_base + SCC_DMA_STATUS;
983 u32 reg = 0;
984
985 out_be32(cckctrl_port, reg);
986 reg |= CCKCTRL_ATACLKOEN;
987 out_be32(cckctrl_port, reg);
988 reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
989 out_be32(cckctrl_port, reg);
990 reg |= CCKCTRL_CRST;
991 out_be32(cckctrl_port, reg);
992
993 for (;;) {
994 reg = in_be32(cckctrl_port);
995 if (reg & CCKCTRL_CRST)
996 break;
997 udelay(5000);
998 }
999
1000 reg |= CCKCTRL_ATARESET;
1001 out_be32(cckctrl_port, reg);
1002 out_be32(ecmode_port, ECMODE_VALUE);
1003 out_be32(mode_port, MODE_JCUSFEN);
1004 out_be32(intmask_port, INTMASK_MSK);
1005
1006 if (in_be32(dmastatus_port) & QCHSD_STPDIAG) {
1007 printk(KERN_WARNING "%s: failed to detect 80c cable. (PDIAG# is high)\n", DRV_NAME);
1008 return -EIO;
1009 }
1010
1011 return 0;
1012}
1013
1014
1015
1016
1017
1018
1019
1020static void scc_setup_ports (struct ata_ioports *ioaddr, void __iomem *base)
1021{
1022 ioaddr->cmd_addr = base + SCC_REG_CMD_ADDR;
1023 ioaddr->altstatus_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
1024 ioaddr->ctl_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
1025 ioaddr->bmdma_addr = base;
1026 ioaddr->data_addr = ioaddr->cmd_addr + SCC_REG_DATA;
1027 ioaddr->error_addr = ioaddr->cmd_addr + SCC_REG_ERR;
1028 ioaddr->feature_addr = ioaddr->cmd_addr + SCC_REG_FEATURE;
1029 ioaddr->nsect_addr = ioaddr->cmd_addr + SCC_REG_NSECT;
1030 ioaddr->lbal_addr = ioaddr->cmd_addr + SCC_REG_LBAL;
1031 ioaddr->lbam_addr = ioaddr->cmd_addr + SCC_REG_LBAM;
1032 ioaddr->lbah_addr = ioaddr->cmd_addr + SCC_REG_LBAH;
1033 ioaddr->device_addr = ioaddr->cmd_addr + SCC_REG_DEVICE;
1034 ioaddr->status_addr = ioaddr->cmd_addr + SCC_REG_STATUS;
1035 ioaddr->command_addr = ioaddr->cmd_addr + SCC_REG_CMD;
1036}
1037
1038static int scc_host_init(struct ata_host *host)
1039{
1040 struct pci_dev *pdev = to_pci_dev(host->dev);
1041 int rc;
1042
1043 rc = scc_reset_controller(host);
1044 if (rc)
1045 return rc;
1046
1047 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1048 if (rc)
1049 return rc;
1050 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1051 if (rc)
1052 return rc;
1053
1054 scc_setup_ports(&host->ports[0]->ioaddr, host->iomap[SCC_BMID_BAR]);
1055
1056 pci_set_master(pdev);
1057
1058 return 0;
1059}
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073static int scc_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1074{
1075 static int printed_version;
1076 unsigned int board_idx = (unsigned int) ent->driver_data;
1077 const struct ata_port_info *ppi[] = { &scc_port_info[board_idx], NULL };
1078 struct ata_host *host;
1079 int rc;
1080
1081 if (!printed_version++)
1082 dev_printk(KERN_DEBUG, &pdev->dev,
1083 "version " DRV_VERSION "\n");
1084
1085 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1);
1086 if (!host)
1087 return -ENOMEM;
1088
1089 rc = pcim_enable_device(pdev);
1090 if (rc)
1091 return rc;
1092
1093 rc = pcim_iomap_regions(pdev, (1 << SCC_CTRL_BAR) | (1 << SCC_BMID_BAR), DRV_NAME);
1094 if (rc == -EBUSY)
1095 pcim_pin_device(pdev);
1096 if (rc)
1097 return rc;
1098 host->iomap = pcim_iomap_table(pdev);
1099
1100 ata_port_pbar_desc(host->ports[0], SCC_CTRL_BAR, -1, "ctrl");
1101 ata_port_pbar_desc(host->ports[0], SCC_BMID_BAR, -1, "bmid");
1102
1103 rc = scc_host_init(host);
1104 if (rc)
1105 return rc;
1106
1107 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
1108 IRQF_SHARED, &scc_sht);
1109}
1110
1111static struct pci_driver scc_pci_driver = {
1112 .name = DRV_NAME,
1113 .id_table = scc_pci_tbl,
1114 .probe = scc_init_one,
1115 .remove = ata_pci_remove_one,
1116#ifdef CONFIG_PM
1117 .suspend = ata_pci_device_suspend,
1118 .resume = ata_pci_device_resume,
1119#endif
1120};
1121
1122static int __init scc_init (void)
1123{
1124 int rc;
1125
1126 DPRINTK("pci_register_driver\n");
1127 rc = pci_register_driver(&scc_pci_driver);
1128 if (rc)
1129 return rc;
1130
1131 DPRINTK("done\n");
1132 return 0;
1133}
1134
1135static void __exit scc_exit (void)
1136{
1137 pci_unregister_driver(&scc_pci_driver);
1138}
1139
1140module_init(scc_init);
1141module_exit(scc_exit);
1142
1143MODULE_AUTHOR("Toshiba corp");
1144MODULE_DESCRIPTION("SCSI low-level driver for Toshiba SCC PATA controller");
1145MODULE_LICENSE("GPL");
1146MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
1147MODULE_VERSION(DRV_VERSION);
1148