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39#include <linux/kernel.h>
40#include <linux/module.h>
41#include <linux/pci.h>
42#include <linux/init.h>
43#include <linux/blkdev.h>
44#include <linux/delay.h>
45#include <linux/interrupt.h>
46#include <linux/device.h>
47#include <scsi/scsi_host.h>
48#include <scsi/scsi_cmnd.h>
49#include <scsi/scsi.h>
50#include <linux/libata.h>
51
52#ifdef CONFIG_PPC_OF
53#include <asm/prom.h>
54#include <asm/pci-bridge.h>
55#endif
56
57#define DRV_NAME "sata_svw"
58#define DRV_VERSION "2.3"
59
60enum {
61
62 K2_FLAG_SATA_8_PORTS = (1 << 24),
63 K2_FLAG_NO_ATAPI_DMA = (1 << 25),
64 K2_FLAG_BAR_POS_3 = (1 << 26),
65
66
67 K2_SATA_TF_CMD_OFFSET = 0x00,
68 K2_SATA_TF_DATA_OFFSET = 0x00,
69 K2_SATA_TF_ERROR_OFFSET = 0x04,
70 K2_SATA_TF_NSECT_OFFSET = 0x08,
71 K2_SATA_TF_LBAL_OFFSET = 0x0c,
72 K2_SATA_TF_LBAM_OFFSET = 0x10,
73 K2_SATA_TF_LBAH_OFFSET = 0x14,
74 K2_SATA_TF_DEVICE_OFFSET = 0x18,
75 K2_SATA_TF_CMDSTAT_OFFSET = 0x1c,
76 K2_SATA_TF_CTL_OFFSET = 0x20,
77
78
79 K2_SATA_DMA_CMD_OFFSET = 0x30,
80
81
82 K2_SATA_SCR_STATUS_OFFSET = 0x40,
83 K2_SATA_SCR_ERROR_OFFSET = 0x44,
84 K2_SATA_SCR_CONTROL_OFFSET = 0x48,
85
86
87 K2_SATA_SICR1_OFFSET = 0x80,
88 K2_SATA_SICR2_OFFSET = 0x84,
89 K2_SATA_SIM_OFFSET = 0x88,
90
91
92 K2_SATA_PORT_OFFSET = 0x100,
93
94 chip_svw4 = 0,
95 chip_svw8 = 1,
96 chip_svw42 = 2,
97 chip_svw43 = 3,
98};
99
100static u8 k2_stat_check_status(struct ata_port *ap);
101
102
103static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
104{
105 u8 cmnd = qc->scsicmd->cmnd[0];
106
107 if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
108 return -1;
109 else {
110 switch (cmnd) {
111 case READ_10:
112 case READ_12:
113 case READ_16:
114 case WRITE_10:
115 case WRITE_12:
116 case WRITE_16:
117 return 0;
118
119 default:
120 return -1;
121 }
122
123 }
124}
125
126static int k2_sata_scr_read(struct ata_link *link,
127 unsigned int sc_reg, u32 *val)
128{
129 if (sc_reg > SCR_CONTROL)
130 return -EINVAL;
131 *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
132 return 0;
133}
134
135
136static int k2_sata_scr_write(struct ata_link *link,
137 unsigned int sc_reg, u32 val)
138{
139 if (sc_reg > SCR_CONTROL)
140 return -EINVAL;
141 writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
142 return 0;
143}
144
145
146static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
147{
148 struct ata_ioports *ioaddr = &ap->ioaddr;
149 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
150
151 if (tf->ctl != ap->last_ctl) {
152 writeb(tf->ctl, ioaddr->ctl_addr);
153 ap->last_ctl = tf->ctl;
154 ata_wait_idle(ap);
155 }
156 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
157 writew(tf->feature | (((u16)tf->hob_feature) << 8),
158 ioaddr->feature_addr);
159 writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
160 ioaddr->nsect_addr);
161 writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
162 ioaddr->lbal_addr);
163 writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
164 ioaddr->lbam_addr);
165 writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
166 ioaddr->lbah_addr);
167 } else if (is_addr) {
168 writew(tf->feature, ioaddr->feature_addr);
169 writew(tf->nsect, ioaddr->nsect_addr);
170 writew(tf->lbal, ioaddr->lbal_addr);
171 writew(tf->lbam, ioaddr->lbam_addr);
172 writew(tf->lbah, ioaddr->lbah_addr);
173 }
174
175 if (tf->flags & ATA_TFLAG_DEVICE)
176 writeb(tf->device, ioaddr->device_addr);
177
178 ata_wait_idle(ap);
179}
180
181
182static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
183{
184 struct ata_ioports *ioaddr = &ap->ioaddr;
185 u16 nsect, lbal, lbam, lbah, feature;
186
187 tf->command = k2_stat_check_status(ap);
188 tf->device = readw(ioaddr->device_addr);
189 feature = readw(ioaddr->error_addr);
190 nsect = readw(ioaddr->nsect_addr);
191 lbal = readw(ioaddr->lbal_addr);
192 lbam = readw(ioaddr->lbam_addr);
193 lbah = readw(ioaddr->lbah_addr);
194
195 tf->feature = feature;
196 tf->nsect = nsect;
197 tf->lbal = lbal;
198 tf->lbam = lbam;
199 tf->lbah = lbah;
200
201 if (tf->flags & ATA_TFLAG_LBA48) {
202 tf->hob_feature = feature >> 8;
203 tf->hob_nsect = nsect >> 8;
204 tf->hob_lbal = lbal >> 8;
205 tf->hob_lbam = lbam >> 8;
206 tf->hob_lbah = lbah >> 8;
207 }
208}
209
210
211
212
213
214
215
216
217
218static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)
219{
220 struct ata_port *ap = qc->ap;
221 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
222 u8 dmactl;
223 void __iomem *mmio = ap->ioaddr.bmdma_addr;
224
225
226 mb();
227 writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS);
228
229
230 dmactl = readb(mmio + ATA_DMA_CMD);
231 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
232 if (!rw)
233 dmactl |= ATA_DMA_WR;
234 writeb(dmactl, mmio + ATA_DMA_CMD);
235
236
237 if (qc->tf.protocol != ATA_PROT_DMA)
238 ap->ops->sff_exec_command(ap, &qc->tf);
239}
240
241
242
243
244
245
246
247
248
249static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)
250{
251 struct ata_port *ap = qc->ap;
252 void __iomem *mmio = ap->ioaddr.bmdma_addr;
253 u8 dmactl;
254
255
256 dmactl = readb(mmio + ATA_DMA_CMD);
257 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
258
259
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270
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273
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277
278
279
280
281 if (qc->tf.protocol == ATA_PROT_DMA)
282 ap->ops->sff_exec_command(ap, &qc->tf);
283}
284
285
286static u8 k2_stat_check_status(struct ata_port *ap)
287{
288 return readl(ap->ioaddr.status_addr);
289}
290
291#ifdef CONFIG_PPC_OF
292
293
294
295
296
297
298
299
300
301
302
303static int k2_sata_proc_info(struct Scsi_Host *shost, char *page, char **start,
304 off_t offset, int count, int inout)
305{
306 struct ata_port *ap;
307 struct device_node *np;
308 int len, index;
309
310
311 ap = ata_shost_to_port(shost);
312 if (ap == NULL)
313 return 0;
314
315
316 np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
317 if (np == NULL)
318 return 0;
319
320
321 index = (ap == ap->host->ports[0]) ? 0 : 1;
322 for (np = np->child; np != NULL; np = np->sibling) {
323 const u32 *reg = of_get_property(np, "reg", NULL);
324 if (!reg)
325 continue;
326 if (index == *reg)
327 break;
328 }
329 if (np == NULL)
330 return 0;
331
332 len = sprintf(page, "devspec: %s\n", np->full_name);
333
334 return len;
335}
336#endif
337
338
339static struct scsi_host_template k2_sata_sht = {
340 ATA_BMDMA_SHT(DRV_NAME),
341#ifdef CONFIG_PPC_OF
342 .proc_info = k2_sata_proc_info,
343#endif
344};
345
346
347static struct ata_port_operations k2_sata_ops = {
348 .inherits = &ata_bmdma_port_ops,
349 .sff_tf_load = k2_sata_tf_load,
350 .sff_tf_read = k2_sata_tf_read,
351 .sff_check_status = k2_stat_check_status,
352 .check_atapi_dma = k2_sata_check_atapi_dma,
353 .bmdma_setup = k2_bmdma_setup_mmio,
354 .bmdma_start = k2_bmdma_start_mmio,
355 .scr_read = k2_sata_scr_read,
356 .scr_write = k2_sata_scr_write,
357};
358
359static const struct ata_port_info k2_port_info[] = {
360
361 {
362 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
363 ATA_FLAG_MMIO | K2_FLAG_NO_ATAPI_DMA,
364 .pio_mask = ATA_PIO4,
365 .mwdma_mask = ATA_MWDMA2,
366 .udma_mask = ATA_UDMA6,
367 .port_ops = &k2_sata_ops,
368 },
369
370 {
371 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
372 ATA_FLAG_MMIO | K2_FLAG_NO_ATAPI_DMA |
373 K2_FLAG_SATA_8_PORTS,
374 .pio_mask = ATA_PIO4,
375 .mwdma_mask = ATA_MWDMA2,
376 .udma_mask = ATA_UDMA6,
377 .port_ops = &k2_sata_ops,
378 },
379
380 {
381 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
382 ATA_FLAG_MMIO | K2_FLAG_BAR_POS_3,
383 .pio_mask = ATA_PIO4,
384 .mwdma_mask = ATA_MWDMA2,
385 .udma_mask = ATA_UDMA6,
386 .port_ops = &k2_sata_ops,
387 },
388
389 {
390 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
391 ATA_FLAG_MMIO,
392 .pio_mask = ATA_PIO4,
393 .mwdma_mask = ATA_MWDMA2,
394 .udma_mask = ATA_UDMA6,
395 .port_ops = &k2_sata_ops,
396 },
397};
398
399static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base)
400{
401 port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET;
402 port->data_addr = base + K2_SATA_TF_DATA_OFFSET;
403 port->feature_addr =
404 port->error_addr = base + K2_SATA_TF_ERROR_OFFSET;
405 port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET;
406 port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET;
407 port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET;
408 port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET;
409 port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET;
410 port->command_addr =
411 port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET;
412 port->altstatus_addr =
413 port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET;
414 port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET;
415 port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET;
416}
417
418
419static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
420{
421 static int printed_version;
422 const struct ata_port_info *ppi[] =
423 { &k2_port_info[ent->driver_data], NULL };
424 struct ata_host *host;
425 void __iomem *mmio_base;
426 int n_ports, i, rc, bar_pos;
427
428 if (!printed_version++)
429 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
430
431
432 n_ports = 4;
433 if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)
434 n_ports = 8;
435
436 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
437 if (!host)
438 return -ENOMEM;
439
440 bar_pos = 5;
441 if (ppi[0]->flags & K2_FLAG_BAR_POS_3)
442 bar_pos = 3;
443
444
445
446
447 rc = pcim_enable_device(pdev);
448 if (rc)
449 return rc;
450
451
452
453
454
455 if (pci_resource_len(pdev, bar_pos) == 0) {
456
457
458
459
460 pcim_pin_device(pdev);
461 return -ENODEV;
462 }
463
464
465 rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME);
466 if (rc == -EBUSY)
467 pcim_pin_device(pdev);
468 if (rc)
469 return rc;
470 host->iomap = pcim_iomap_table(pdev);
471 mmio_base = host->iomap[bar_pos];
472
473
474
475
476 for (i = 0; i < host->n_ports; i++) {
477 struct ata_port *ap = host->ports[i];
478 unsigned int offset = i * K2_SATA_PORT_OFFSET;
479
480 k2_sata_setup_port(&ap->ioaddr, mmio_base + offset);
481
482 ata_port_pbar_desc(ap, 5, -1, "mmio");
483 ata_port_pbar_desc(ap, 5, offset, "port");
484 }
485
486 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
487 if (rc)
488 return rc;
489 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
490 if (rc)
491 return rc;
492
493
494
495
496
497 writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
498 mmio_base + K2_SATA_SICR1_OFFSET);
499
500
501 writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
502 writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
503
504 pci_set_master(pdev);
505 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
506 IRQF_SHARED, &k2_sata_sht);
507}
508
509
510
511
512
513
514
515static const struct pci_device_id k2_sata_pci_tbl[] = {
516 { PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 },
517 { PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 },
518 { PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 },
519 { PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 },
520 { PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 },
521 { PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 },
522 { PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 },
523
524 { }
525};
526
527static struct pci_driver k2_sata_pci_driver = {
528 .name = DRV_NAME,
529 .id_table = k2_sata_pci_tbl,
530 .probe = k2_sata_init_one,
531 .remove = ata_pci_remove_one,
532};
533
534static int __init k2_sata_init(void)
535{
536 return pci_register_driver(&k2_sata_pci_driver);
537}
538
539static void __exit k2_sata_exit(void)
540{
541 pci_unregister_driver(&k2_sata_pci_driver);
542}
543
544MODULE_AUTHOR("Benjamin Herrenschmidt");
545MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
546MODULE_LICENSE("GPL");
547MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
548MODULE_VERSION(DRV_VERSION);
549
550module_init(k2_sata_init);
551module_exit(k2_sata_exit);
552