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55
56#if defined(__i386__)
57# define BREAKPOINT() asm(" int $3");
58#else
59# define BREAKPOINT() { }
60#endif
61
62#define MAX_ISA_DEVICES 10
63#define MAX_PCI_DEVICES 10
64#define MAX_TOTAL_DEVICES 20
65
66#include <linux/module.h>
67#include <linux/errno.h>
68#include <linux/signal.h>
69#include <linux/sched.h>
70#include <linux/timer.h>
71#include <linux/interrupt.h>
72#include <linux/pci.h>
73#include <linux/tty.h>
74#include <linux/tty_flip.h>
75#include <linux/serial.h>
76#include <linux/major.h>
77#include <linux/string.h>
78#include <linux/fcntl.h>
79#include <linux/ptrace.h>
80#include <linux/ioport.h>
81#include <linux/mm.h>
82#include <linux/seq_file.h>
83#include <linux/slab.h>
84#include <linux/delay.h>
85#include <linux/netdevice.h>
86#include <linux/vmalloc.h>
87#include <linux/init.h>
88#include <linux/ioctl.h>
89#include <linux/synclink.h>
90
91#include <asm/system.h>
92#include <asm/io.h>
93#include <asm/irq.h>
94#include <asm/dma.h>
95#include <linux/bitops.h>
96#include <asm/types.h>
97#include <linux/termios.h>
98#include <linux/workqueue.h>
99#include <linux/hdlc.h>
100#include <linux/dma-mapping.h>
101
102#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
103#define SYNCLINK_GENERIC_HDLC 1
104#else
105#define SYNCLINK_GENERIC_HDLC 0
106#endif
107
108#define GET_USER(error,value,addr) error = get_user(value,addr)
109#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
110#define PUT_USER(error,value,addr) error = put_user(value,addr)
111#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
112
113#include <asm/uaccess.h>
114
115#define RCLRVALUE 0xffff
116
117static MGSL_PARAMS default_params = {
118 MGSL_MODE_HDLC,
119 0,
120 HDLC_FLAG_UNDERRUN_ABORT15,
121 HDLC_ENCODING_NRZI_SPACE,
122 0,
123 0xff,
124 HDLC_CRC_16_CCITT,
125 HDLC_PREAMBLE_LENGTH_8BITS,
126 HDLC_PREAMBLE_PATTERN_NONE,
127 9600,
128 8,
129 1,
130 ASYNC_PARITY_NONE
131};
132
133#define SHARED_MEM_ADDRESS_SIZE 0x40000
134#define BUFFERLISTSIZE 4096
135#define DMABUFFERSIZE 4096
136#define MAXRXFRAMES 7
137
138typedef struct _DMABUFFERENTRY
139{
140 u32 phys_addr;
141 volatile u16 count;
142 volatile u16 status;
143 volatile u16 rcc;
144 u16 reserved;
145 u32 link;
146 char *virt_addr;
147 u32 phys_entry;
148 dma_addr_t dma_addr;
149} DMABUFFERENTRY, *DMAPBUFFERENTRY;
150
151
152
153#define BH_RECEIVE 1
154#define BH_TRANSMIT 2
155#define BH_STATUS 4
156
157#define IO_PIN_SHUTDOWN_LIMIT 100
158
159struct _input_signal_events {
160 int ri_up;
161 int ri_down;
162 int dsr_up;
163 int dsr_down;
164 int dcd_up;
165 int dcd_down;
166 int cts_up;
167 int cts_down;
168};
169
170
171#define MAX_TX_HOLDING_BUFFERS 5
172struct tx_holding_buffer {
173 int buffer_size;
174 unsigned char * buffer;
175};
176
177
178
179
180
181
182struct mgsl_struct {
183 int magic;
184 struct tty_port port;
185 int line;
186 int hw_version;
187
188 struct mgsl_icount icount;
189
190 int timeout;
191 int x_char;
192 u16 read_status_mask;
193 u16 ignore_status_mask;
194 unsigned char *xmit_buf;
195 int xmit_head;
196 int xmit_tail;
197 int xmit_cnt;
198
199 wait_queue_head_t status_event_wait_q;
200 wait_queue_head_t event_wait_q;
201 struct timer_list tx_timer;
202 struct mgsl_struct *next_device;
203
204 spinlock_t irq_spinlock;
205 struct work_struct task;
206
207 u32 EventMask;
208 u32 RecordedEvents;
209
210 u32 max_frame_size;
211
212 u32 pending_bh;
213
214 bool bh_running;
215 int isr_overflow;
216 bool bh_requested;
217
218 int dcd_chkcount;
219 int cts_chkcount;
220 int dsr_chkcount;
221 int ri_chkcount;
222
223 char *buffer_list;
224 u32 buffer_list_phys;
225 dma_addr_t buffer_list_dma_addr;
226
227 unsigned int rx_buffer_count;
228 DMABUFFERENTRY *rx_buffer_list;
229 unsigned int current_rx_buffer;
230
231 int num_tx_dma_buffers;
232 int tx_dma_buffers_used;
233 unsigned int tx_buffer_count;
234 DMABUFFERENTRY *tx_buffer_list;
235 int start_tx_dma_buffer;
236 int current_tx_buffer;
237
238 unsigned char *intermediate_rxbuffer;
239
240 int num_tx_holding_buffers;
241 int get_tx_holding_index;
242 int put_tx_holding_index;
243 int tx_holding_count;
244 struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
245
246 bool rx_enabled;
247 bool rx_overflow;
248 bool rx_rcc_underrun;
249
250 bool tx_enabled;
251 bool tx_active;
252 u32 idle_mode;
253
254 u16 cmr_value;
255 u16 tcsr_value;
256
257 char device_name[25];
258
259 unsigned int bus_type;
260 unsigned char bus;
261 unsigned char function;
262
263 unsigned int io_base;
264 unsigned int io_addr_size;
265 bool io_addr_requested;
266
267 unsigned int irq_level;
268 unsigned long irq_flags;
269 bool irq_requested;
270
271 unsigned int dma_level;
272 bool dma_requested;
273
274 u16 mbre_bit;
275 u16 loopback_bits;
276 u16 usc_idle_mode;
277
278 MGSL_PARAMS params;
279
280 unsigned char serial_signals;
281
282 bool irq_occurred;
283 unsigned int init_error;
284 int fDiagnosticsmode;
285
286 u32 last_mem_alloc;
287 unsigned char* memory_base;
288 u32 phys_memory_base;
289 bool shared_mem_requested;
290
291 unsigned char* lcr_base;
292 u32 phys_lcr_base;
293 u32 lcr_offset;
294 bool lcr_mem_requested;
295
296 u32 misc_ctrl_value;
297 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
298 char char_buf[MAX_ASYNC_BUFFER_SIZE];
299 bool drop_rts_on_tx_done;
300
301 bool loopmode_insert_requested;
302 bool loopmode_send_done_requested;
303
304 struct _input_signal_events input_signal_events;
305
306
307 int netcount;
308 spinlock_t netlock;
309
310#if SYNCLINK_GENERIC_HDLC
311 struct net_device *netdev;
312#endif
313};
314
315#define MGSL_MAGIC 0x5401
316
317
318
319
320#ifndef SERIAL_XMIT_SIZE
321#define SERIAL_XMIT_SIZE 4096
322#endif
323
324
325
326
327
328
329
330#define DCPIN 2
331#define SDPIN 4
332
333#define DCAR 0
334#define CCAR SDPIN
335#define DATAREG DCPIN + SDPIN
336#define MSBONLY 0x41
337#define LSBONLY 0x40
338
339
340
341
342
343
344#define CMR 0x02
345#define CCSR 0x04
346#define CCR 0x06
347#define PSR 0x08
348#define PCR 0x0a
349#define TMDR 0x0c
350#define TMCR 0x0e
351#define CMCR 0x10
352#define HCR 0x12
353#define IVR 0x14
354#define IOCR 0x16
355#define ICR 0x18
356#define DCCR 0x1a
357#define MISR 0x1c
358#define SICR 0x1e
359#define RDR 0x20
360#define RMR 0x22
361#define RCSR 0x24
362#define RICR 0x26
363#define RSR 0x28
364#define RCLR 0x2a
365#define RCCR 0x2c
366#define TC0R 0x2e
367#define TDR 0x30
368#define TMR 0x32
369#define TCSR 0x34
370#define TICR 0x36
371#define TSR 0x38
372#define TCLR 0x3a
373#define TCCR 0x3c
374#define TC1R 0x3e
375
376
377
378
379
380
381#define DCR 0x06
382#define DACR 0x08
383#define BDCR 0x12
384#define DIVR 0x14
385#define DICR 0x18
386#define CDIR 0x1a
387#define SDIR 0x1c
388
389#define TDMR 0x02
390#define TDIAR 0x1e
391#define TBCR 0x2a
392#define TARL 0x2c
393#define TARU 0x2e
394#define NTBCR 0x3a
395#define NTARL 0x3c
396#define NTARU 0x3e
397
398#define RDMR 0x82
399#define RDIAR 0x9e
400#define RBCR 0xaa
401#define RARL 0xac
402#define RARU 0xae
403#define NRBCR 0xba
404#define NRARL 0xbc
405#define NRARU 0xbe
406
407
408
409
410
411
412#define MODEMSTATUS_DTR 0x80
413#define MODEMSTATUS_DSR 0x40
414#define MODEMSTATUS_RTS 0x20
415#define MODEMSTATUS_CTS 0x10
416#define MODEMSTATUS_RI 0x04
417#define MODEMSTATUS_DCD 0x01
418
419
420
421
422
423
424#define RTCmd_Null 0x0000
425#define RTCmd_ResetHighestIus 0x1000
426#define RTCmd_TriggerChannelLoadDma 0x2000
427#define RTCmd_TriggerRxDma 0x2800
428#define RTCmd_TriggerTxDma 0x3000
429#define RTCmd_TriggerRxAndTxDma 0x3800
430#define RTCmd_PurgeRxFifo 0x4800
431#define RTCmd_PurgeTxFifo 0x5000
432#define RTCmd_PurgeRxAndTxFifo 0x5800
433#define RTCmd_LoadRcc 0x6800
434#define RTCmd_LoadTcc 0x7000
435#define RTCmd_LoadRccAndTcc 0x7800
436#define RTCmd_LoadTC0 0x8800
437#define RTCmd_LoadTC1 0x9000
438#define RTCmd_LoadTC0AndTC1 0x9800
439#define RTCmd_SerialDataLSBFirst 0xa000
440#define RTCmd_SerialDataMSBFirst 0xa800
441#define RTCmd_SelectBigEndian 0xb000
442#define RTCmd_SelectLittleEndian 0xb800
443
444
445
446
447
448
449#define DmaCmd_Null 0x0000
450#define DmaCmd_ResetTxChannel 0x1000
451#define DmaCmd_ResetRxChannel 0x1200
452#define DmaCmd_StartTxChannel 0x2000
453#define DmaCmd_StartRxChannel 0x2200
454#define DmaCmd_ContinueTxChannel 0x3000
455#define DmaCmd_ContinueRxChannel 0x3200
456#define DmaCmd_PauseTxChannel 0x4000
457#define DmaCmd_PauseRxChannel 0x4200
458#define DmaCmd_AbortTxChannel 0x5000
459#define DmaCmd_AbortRxChannel 0x5200
460#define DmaCmd_InitTxChannel 0x7000
461#define DmaCmd_InitRxChannel 0x7200
462#define DmaCmd_ResetHighestDmaIus 0x8000
463#define DmaCmd_ResetAllChannels 0x9000
464#define DmaCmd_StartAllChannels 0xa000
465#define DmaCmd_ContinueAllChannels 0xb000
466#define DmaCmd_PauseAllChannels 0xc000
467#define DmaCmd_AbortAllChannels 0xd000
468#define DmaCmd_InitAllChannels 0xf000
469
470#define TCmd_Null 0x0000
471#define TCmd_ClearTxCRC 0x2000
472#define TCmd_SelectTicrTtsaData 0x4000
473#define TCmd_SelectTicrTxFifostatus 0x5000
474#define TCmd_SelectTicrIntLevel 0x6000
475#define TCmd_SelectTicrdma_level 0x7000
476#define TCmd_SendFrame 0x8000
477#define TCmd_SendAbort 0x9000
478#define TCmd_EnableDleInsertion 0xc000
479#define TCmd_DisableDleInsertion 0xd000
480#define TCmd_ClearEofEom 0xe000
481#define TCmd_SetEofEom 0xf000
482
483#define RCmd_Null 0x0000
484#define RCmd_ClearRxCRC 0x2000
485#define RCmd_EnterHuntmode 0x3000
486#define RCmd_SelectRicrRtsaData 0x4000
487#define RCmd_SelectRicrRxFifostatus 0x5000
488#define RCmd_SelectRicrIntLevel 0x6000
489#define RCmd_SelectRicrdma_level 0x7000
490
491
492
493
494
495#define RECEIVE_STATUS BIT5
496#define RECEIVE_DATA BIT4
497#define TRANSMIT_STATUS BIT3
498#define TRANSMIT_DATA BIT2
499#define IO_PIN BIT1
500#define MISC BIT0
501
502
503
504
505
506
507#define RXSTATUS_SHORT_FRAME BIT8
508#define RXSTATUS_CODE_VIOLATION BIT8
509#define RXSTATUS_EXITED_HUNT BIT7
510#define RXSTATUS_IDLE_RECEIVED BIT6
511#define RXSTATUS_BREAK_RECEIVED BIT5
512#define RXSTATUS_ABORT_RECEIVED BIT5
513#define RXSTATUS_RXBOUND BIT4
514#define RXSTATUS_CRC_ERROR BIT3
515#define RXSTATUS_FRAMING_ERROR BIT3
516#define RXSTATUS_ABORT BIT2
517#define RXSTATUS_PARITY_ERROR BIT2
518#define RXSTATUS_OVERRUN BIT1
519#define RXSTATUS_DATA_AVAILABLE BIT0
520#define RXSTATUS_ALL 0x01f6
521#define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
522
523
524
525
526
527#define IDLEMODE_FLAGS 0x0000
528#define IDLEMODE_ALT_ONE_ZERO 0x0100
529#define IDLEMODE_ZERO 0x0200
530#define IDLEMODE_ONE 0x0300
531#define IDLEMODE_ALT_MARK_SPACE 0x0500
532#define IDLEMODE_SPACE 0x0600
533#define IDLEMODE_MARK 0x0700
534#define IDLEMODE_MASK 0x0700
535
536
537
538
539#define IUSC_SL1660 0x4d44
540#define IUSC_PRE_SL1660 0x4553
541
542
543
544
545
546#define TCSR_PRESERVE 0x0F00
547
548#define TCSR_UNDERWAIT BIT11
549#define TXSTATUS_PREAMBLE_SENT BIT7
550#define TXSTATUS_IDLE_SENT BIT6
551#define TXSTATUS_ABORT_SENT BIT5
552#define TXSTATUS_EOF_SENT BIT4
553#define TXSTATUS_EOM_SENT BIT4
554#define TXSTATUS_CRC_SENT BIT3
555#define TXSTATUS_ALL_SENT BIT2
556#define TXSTATUS_UNDERRUN BIT1
557#define TXSTATUS_FIFO_EMPTY BIT0
558#define TXSTATUS_ALL 0x00fa
559#define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
560
561
562#define MISCSTATUS_RXC_LATCHED BIT15
563#define MISCSTATUS_RXC BIT14
564#define MISCSTATUS_TXC_LATCHED BIT13
565#define MISCSTATUS_TXC BIT12
566#define MISCSTATUS_RI_LATCHED BIT11
567#define MISCSTATUS_RI BIT10
568#define MISCSTATUS_DSR_LATCHED BIT9
569#define MISCSTATUS_DSR BIT8
570#define MISCSTATUS_DCD_LATCHED BIT7
571#define MISCSTATUS_DCD BIT6
572#define MISCSTATUS_CTS_LATCHED BIT5
573#define MISCSTATUS_CTS BIT4
574#define MISCSTATUS_RCC_UNDERRUN BIT3
575#define MISCSTATUS_DPLL_NO_SYNC BIT2
576#define MISCSTATUS_BRG1_ZERO BIT1
577#define MISCSTATUS_BRG0_ZERO BIT0
578
579#define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
580#define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
581
582#define SICR_RXC_ACTIVE BIT15
583#define SICR_RXC_INACTIVE BIT14
584#define SICR_RXC (BIT15+BIT14)
585#define SICR_TXC_ACTIVE BIT13
586#define SICR_TXC_INACTIVE BIT12
587#define SICR_TXC (BIT13+BIT12)
588#define SICR_RI_ACTIVE BIT11
589#define SICR_RI_INACTIVE BIT10
590#define SICR_RI (BIT11+BIT10)
591#define SICR_DSR_ACTIVE BIT9
592#define SICR_DSR_INACTIVE BIT8
593#define SICR_DSR (BIT9+BIT8)
594#define SICR_DCD_ACTIVE BIT7
595#define SICR_DCD_INACTIVE BIT6
596#define SICR_DCD (BIT7+BIT6)
597#define SICR_CTS_ACTIVE BIT5
598#define SICR_CTS_INACTIVE BIT4
599#define SICR_CTS (BIT5+BIT4)
600#define SICR_RCC_UNDERFLOW BIT3
601#define SICR_DPLL_NO_SYNC BIT2
602#define SICR_BRG1_ZERO BIT1
603#define SICR_BRG0_ZERO BIT0
604
605void usc_DisableMasterIrqBit( struct mgsl_struct *info );
606void usc_EnableMasterIrqBit( struct mgsl_struct *info );
607void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
608void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
609void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
610
611#define usc_EnableInterrupts( a, b ) \
612 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
613
614#define usc_DisableInterrupts( a, b ) \
615 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
616
617#define usc_EnableMasterIrqBit(a) \
618 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
619
620#define usc_DisableMasterIrqBit(a) \
621 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
622
623#define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
624
625
626
627
628
629
630#define TXSTATUS_PREAMBLE_SENT BIT7
631#define TXSTATUS_IDLE_SENT BIT6
632#define TXSTATUS_ABORT_SENT BIT5
633#define TXSTATUS_EOF BIT4
634#define TXSTATUS_CRC_SENT BIT3
635#define TXSTATUS_ALL_SENT BIT2
636#define TXSTATUS_UNDERRUN BIT1
637#define TXSTATUS_FIFO_EMPTY BIT0
638
639#define DICR_MASTER BIT15
640#define DICR_TRANSMIT BIT0
641#define DICR_RECEIVE BIT1
642
643#define usc_EnableDmaInterrupts(a,b) \
644 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
645
646#define usc_DisableDmaInterrupts(a,b) \
647 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
648
649#define usc_EnableStatusIrqs(a,b) \
650 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
651
652#define usc_DisablestatusIrqs(a,b) \
653 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
654
655
656
657
658
659#define DISABLE_UNCONDITIONAL 0
660#define DISABLE_END_OF_FRAME 1
661#define ENABLE_UNCONDITIONAL 2
662#define ENABLE_AUTO_CTS 3
663#define ENABLE_AUTO_DCD 3
664#define usc_EnableTransmitter(a,b) \
665 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
666#define usc_EnableReceiver(a,b) \
667 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
668
669static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
670static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
671static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
672
673static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
674static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
675static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
676void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
677void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
678
679#define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
680#define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
681
682#define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
683
684static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
685static void usc_start_receiver( struct mgsl_struct *info );
686static void usc_stop_receiver( struct mgsl_struct *info );
687
688static void usc_start_transmitter( struct mgsl_struct *info );
689static void usc_stop_transmitter( struct mgsl_struct *info );
690static void usc_set_txidle( struct mgsl_struct *info );
691static void usc_load_txfifo( struct mgsl_struct *info );
692
693static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
694static void usc_enable_loopback( struct mgsl_struct *info, int enable );
695
696static void usc_get_serial_signals( struct mgsl_struct *info );
697static void usc_set_serial_signals( struct mgsl_struct *info );
698
699static void usc_reset( struct mgsl_struct *info );
700
701static void usc_set_sync_mode( struct mgsl_struct *info );
702static void usc_set_sdlc_mode( struct mgsl_struct *info );
703static void usc_set_async_mode( struct mgsl_struct *info );
704static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
705
706static void usc_loopback_frame( struct mgsl_struct *info );
707
708static void mgsl_tx_timeout(unsigned long context);
709
710
711static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
712static void usc_loopmode_insert_request( struct mgsl_struct * info );
713static int usc_loopmode_active( struct mgsl_struct * info);
714static void usc_loopmode_send_done( struct mgsl_struct * info );
715
716static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
717
718#if SYNCLINK_GENERIC_HDLC
719#define dev_to_port(D) (dev_to_hdlc(D)->priv)
720static void hdlcdev_tx_done(struct mgsl_struct *info);
721static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
722static int hdlcdev_init(struct mgsl_struct *info);
723static void hdlcdev_exit(struct mgsl_struct *info);
724#endif
725
726
727
728
729
730
731#define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
732(0x00400020 + \
733((WrHold) << 30) + \
734((WrDly) << 28) + \
735((RdDly) << 26) + \
736((Nwdd) << 20) + \
737((Nwad) << 15) + \
738((Nxda) << 13) + \
739((Nrdd) << 11) + \
740((Nrad) << 6) )
741
742static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
743
744
745
746
747static bool mgsl_register_test( struct mgsl_struct *info );
748static bool mgsl_irq_test( struct mgsl_struct *info );
749static bool mgsl_dma_test( struct mgsl_struct *info );
750static bool mgsl_memory_test( struct mgsl_struct *info );
751static int mgsl_adapter_test( struct mgsl_struct *info );
752
753
754
755
756static int mgsl_claim_resources(struct mgsl_struct *info);
757static void mgsl_release_resources(struct mgsl_struct *info);
758static void mgsl_add_device(struct mgsl_struct *info);
759static struct mgsl_struct* mgsl_allocate_device(void);
760
761
762
763
764static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
765static bool mgsl_get_rx_frame( struct mgsl_struct *info );
766static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info );
767static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
768static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
769static int num_free_tx_dma_buffers(struct mgsl_struct *info);
770static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
771static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
772
773
774
775
776static int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
777static void mgsl_free_dma_buffers(struct mgsl_struct *info);
778static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
779static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
780static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
781static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
782static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
783static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
784static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
785static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
786static bool load_next_tx_holding_buffer(struct mgsl_struct *info);
787static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
788
789
790
791
792static void mgsl_bh_handler(struct work_struct *work);
793static void mgsl_bh_receive(struct mgsl_struct *info);
794static void mgsl_bh_transmit(struct mgsl_struct *info);
795static void mgsl_bh_status(struct mgsl_struct *info);
796
797
798
799
800static void mgsl_isr_null( struct mgsl_struct *info );
801static void mgsl_isr_transmit_data( struct mgsl_struct *info );
802static void mgsl_isr_receive_data( struct mgsl_struct *info );
803static void mgsl_isr_receive_status( struct mgsl_struct *info );
804static void mgsl_isr_transmit_status( struct mgsl_struct *info );
805static void mgsl_isr_io_pin( struct mgsl_struct *info );
806static void mgsl_isr_misc( struct mgsl_struct *info );
807static void mgsl_isr_receive_dma( struct mgsl_struct *info );
808static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
809
810typedef void (*isr_dispatch_func)(struct mgsl_struct *);
811
812static isr_dispatch_func UscIsrTable[7] =
813{
814 mgsl_isr_null,
815 mgsl_isr_misc,
816 mgsl_isr_io_pin,
817 mgsl_isr_transmit_data,
818 mgsl_isr_transmit_status,
819 mgsl_isr_receive_data,
820 mgsl_isr_receive_status
821};
822
823
824
825
826static int tiocmget(struct tty_struct *tty, struct file *file);
827static int tiocmset(struct tty_struct *tty, struct file *file,
828 unsigned int set, unsigned int clear);
829static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
830 __user *user_icount);
831static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params);
832static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params);
833static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
834static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
835static int mgsl_txenable(struct mgsl_struct * info, int enable);
836static int mgsl_txabort(struct mgsl_struct * info);
837static int mgsl_rxenable(struct mgsl_struct * info, int enable);
838static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
839static int mgsl_loopmode_send_done( struct mgsl_struct * info );
840
841
842static bool pci_registered;
843
844
845
846
847static struct mgsl_struct *mgsl_device_list;
848static int mgsl_device_count;
849
850
851
852
853
854
855static int break_on_load;
856
857
858
859
860
861static int ttymajor;
862
863
864
865
866static int io[MAX_ISA_DEVICES];
867static int irq[MAX_ISA_DEVICES];
868static int dma[MAX_ISA_DEVICES];
869static int debug_level;
870static int maxframe[MAX_TOTAL_DEVICES];
871static int txdmabufs[MAX_TOTAL_DEVICES];
872static int txholdbufs[MAX_TOTAL_DEVICES];
873
874module_param(break_on_load, bool, 0);
875module_param(ttymajor, int, 0);
876module_param_array(io, int, NULL, 0);
877module_param_array(irq, int, NULL, 0);
878module_param_array(dma, int, NULL, 0);
879module_param(debug_level, int, 0);
880module_param_array(maxframe, int, NULL, 0);
881module_param_array(txdmabufs, int, NULL, 0);
882module_param_array(txholdbufs, int, NULL, 0);
883
884static char *driver_name = "SyncLink serial driver";
885static char *driver_version = "$Revision: 4.38 $";
886
887static int synclink_init_one (struct pci_dev *dev,
888 const struct pci_device_id *ent);
889static void synclink_remove_one (struct pci_dev *dev);
890
891static struct pci_device_id synclink_pci_tbl[] = {
892 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
893 { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
894 { 0, },
895};
896MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
897
898MODULE_LICENSE("GPL");
899
900static struct pci_driver synclink_pci_driver = {
901 .name = "synclink",
902 .id_table = synclink_pci_tbl,
903 .probe = synclink_init_one,
904 .remove = __devexit_p(synclink_remove_one),
905};
906
907static struct tty_driver *serial_driver;
908
909
910#define WAKEUP_CHARS 256
911
912
913static void mgsl_change_params(struct mgsl_struct *info);
914static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
915
916
917
918
919
920
921
922static void* mgsl_get_text_ptr(void)
923{
924 return mgsl_get_text_ptr;
925}
926
927static inline int mgsl_paranoia_check(struct mgsl_struct *info,
928 char *name, const char *routine)
929{
930#ifdef MGSL_PARANOIA_CHECK
931 static const char *badmagic =
932 "Warning: bad magic number for mgsl struct (%s) in %s\n";
933 static const char *badinfo =
934 "Warning: null mgsl_struct for (%s) in %s\n";
935
936 if (!info) {
937 printk(badinfo, name, routine);
938 return 1;
939 }
940 if (info->magic != MGSL_MAGIC) {
941 printk(badmagic, name, routine);
942 return 1;
943 }
944#else
945 if (!info)
946 return 1;
947#endif
948 return 0;
949}
950
951
952
953
954
955
956
957
958
959
960static void ldisc_receive_buf(struct tty_struct *tty,
961 const __u8 *data, char *flags, int count)
962{
963 struct tty_ldisc *ld;
964 if (!tty)
965 return;
966 ld = tty_ldisc_ref(tty);
967 if (ld) {
968 if (ld->ops->receive_buf)
969 ld->ops->receive_buf(tty, data, flags, count);
970 tty_ldisc_deref(ld);
971 }
972}
973
974
975
976
977
978
979static void mgsl_stop(struct tty_struct *tty)
980{
981 struct mgsl_struct *info = tty->driver_data;
982 unsigned long flags;
983
984 if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
985 return;
986
987 if ( debug_level >= DEBUG_LEVEL_INFO )
988 printk("mgsl_stop(%s)\n",info->device_name);
989
990 spin_lock_irqsave(&info->irq_spinlock,flags);
991 if (info->tx_enabled)
992 usc_stop_transmitter(info);
993 spin_unlock_irqrestore(&info->irq_spinlock,flags);
994
995}
996
997
998
999
1000
1001
1002static void mgsl_start(struct tty_struct *tty)
1003{
1004 struct mgsl_struct *info = tty->driver_data;
1005 unsigned long flags;
1006
1007 if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1008 return;
1009
1010 if ( debug_level >= DEBUG_LEVEL_INFO )
1011 printk("mgsl_start(%s)\n",info->device_name);
1012
1013 spin_lock_irqsave(&info->irq_spinlock,flags);
1014 if (!info->tx_enabled)
1015 usc_start_transmitter(info);
1016 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1017
1018}
1019
1020
1021
1022
1023
1024
1025
1026
1027static int mgsl_bh_action(struct mgsl_struct *info)
1028{
1029 unsigned long flags;
1030 int rc = 0;
1031
1032 spin_lock_irqsave(&info->irq_spinlock,flags);
1033
1034 if (info->pending_bh & BH_RECEIVE) {
1035 info->pending_bh &= ~BH_RECEIVE;
1036 rc = BH_RECEIVE;
1037 } else if (info->pending_bh & BH_TRANSMIT) {
1038 info->pending_bh &= ~BH_TRANSMIT;
1039 rc = BH_TRANSMIT;
1040 } else if (info->pending_bh & BH_STATUS) {
1041 info->pending_bh &= ~BH_STATUS;
1042 rc = BH_STATUS;
1043 }
1044
1045 if (!rc) {
1046
1047 info->bh_running = false;
1048 info->bh_requested = false;
1049 }
1050
1051 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1052
1053 return rc;
1054}
1055
1056
1057
1058
1059static void mgsl_bh_handler(struct work_struct *work)
1060{
1061 struct mgsl_struct *info =
1062 container_of(work, struct mgsl_struct, task);
1063 int action;
1064
1065 if (!info)
1066 return;
1067
1068 if ( debug_level >= DEBUG_LEVEL_BH )
1069 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1070 __FILE__,__LINE__,info->device_name);
1071
1072 info->bh_running = true;
1073
1074 while((action = mgsl_bh_action(info)) != 0) {
1075
1076
1077 if ( debug_level >= DEBUG_LEVEL_BH )
1078 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1079 __FILE__,__LINE__,action);
1080
1081 switch (action) {
1082
1083 case BH_RECEIVE:
1084 mgsl_bh_receive(info);
1085 break;
1086 case BH_TRANSMIT:
1087 mgsl_bh_transmit(info);
1088 break;
1089 case BH_STATUS:
1090 mgsl_bh_status(info);
1091 break;
1092 default:
1093
1094 printk("Unknown work item ID=%08X!\n", action);
1095 break;
1096 }
1097 }
1098
1099 if ( debug_level >= DEBUG_LEVEL_BH )
1100 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1101 __FILE__,__LINE__,info->device_name);
1102}
1103
1104static void mgsl_bh_receive(struct mgsl_struct *info)
1105{
1106 bool (*get_rx_frame)(struct mgsl_struct *info) =
1107 (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1108
1109 if ( debug_level >= DEBUG_LEVEL_BH )
1110 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1111 __FILE__,__LINE__,info->device_name);
1112
1113 do
1114 {
1115 if (info->rx_rcc_underrun) {
1116 unsigned long flags;
1117 spin_lock_irqsave(&info->irq_spinlock,flags);
1118 usc_start_receiver(info);
1119 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1120 return;
1121 }
1122 } while(get_rx_frame(info));
1123}
1124
1125static void mgsl_bh_transmit(struct mgsl_struct *info)
1126{
1127 struct tty_struct *tty = info->port.tty;
1128 unsigned long flags;
1129
1130 if ( debug_level >= DEBUG_LEVEL_BH )
1131 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1132 __FILE__,__LINE__,info->device_name);
1133
1134 if (tty)
1135 tty_wakeup(tty);
1136
1137
1138
1139
1140 spin_lock_irqsave(&info->irq_spinlock,flags);
1141 if ( !info->tx_active && info->loopmode_send_done_requested )
1142 usc_loopmode_send_done( info );
1143 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1144}
1145
1146static void mgsl_bh_status(struct mgsl_struct *info)
1147{
1148 if ( debug_level >= DEBUG_LEVEL_BH )
1149 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1150 __FILE__,__LINE__,info->device_name);
1151
1152 info->ri_chkcount = 0;
1153 info->dsr_chkcount = 0;
1154 info->dcd_chkcount = 0;
1155 info->cts_chkcount = 0;
1156}
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167static void mgsl_isr_receive_status( struct mgsl_struct *info )
1168{
1169 u16 status = usc_InReg( info, RCSR );
1170
1171 if ( debug_level >= DEBUG_LEVEL_ISR )
1172 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1173 __FILE__,__LINE__,status);
1174
1175 if ( (status & RXSTATUS_ABORT_RECEIVED) &&
1176 info->loopmode_insert_requested &&
1177 usc_loopmode_active(info) )
1178 {
1179 ++info->icount.rxabort;
1180 info->loopmode_insert_requested = false;
1181
1182
1183 info->cmr_value &= ~BIT13;
1184 usc_OutReg(info, CMR, info->cmr_value);
1185
1186
1187 usc_OutReg(info, RICR,
1188 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1189 }
1190
1191 if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) {
1192 if (status & RXSTATUS_EXITED_HUNT)
1193 info->icount.exithunt++;
1194 if (status & RXSTATUS_IDLE_RECEIVED)
1195 info->icount.rxidle++;
1196 wake_up_interruptible(&info->event_wait_q);
1197 }
1198
1199 if (status & RXSTATUS_OVERRUN){
1200 info->icount.rxover++;
1201 usc_process_rxoverrun_sync( info );
1202 }
1203
1204 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1205 usc_UnlatchRxstatusBits( info, status );
1206
1207}
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219static void mgsl_isr_transmit_status( struct mgsl_struct *info )
1220{
1221 u16 status = usc_InReg( info, TCSR );
1222
1223 if ( debug_level >= DEBUG_LEVEL_ISR )
1224 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1225 __FILE__,__LINE__,status);
1226
1227 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1228 usc_UnlatchTxstatusBits( info, status );
1229
1230 if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1231 {
1232
1233
1234
1235
1236
1237 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1238 usc_RTCmd( info, RTCmd_PurgeTxFifo );
1239 }
1240
1241 if ( status & TXSTATUS_EOF_SENT )
1242 info->icount.txok++;
1243 else if ( status & TXSTATUS_UNDERRUN )
1244 info->icount.txunder++;
1245 else if ( status & TXSTATUS_ABORT_SENT )
1246 info->icount.txabort++;
1247 else
1248 info->icount.txunder++;
1249
1250 info->tx_active = false;
1251 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1252 del_timer(&info->tx_timer);
1253
1254 if ( info->drop_rts_on_tx_done ) {
1255 usc_get_serial_signals( info );
1256 if ( info->serial_signals & SerialSignal_RTS ) {
1257 info->serial_signals &= ~SerialSignal_RTS;
1258 usc_set_serial_signals( info );
1259 }
1260 info->drop_rts_on_tx_done = false;
1261 }
1262
1263#if SYNCLINK_GENERIC_HDLC
1264 if (info->netcount)
1265 hdlcdev_tx_done(info);
1266 else
1267#endif
1268 {
1269 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1270 usc_stop_transmitter(info);
1271 return;
1272 }
1273 info->pending_bh |= BH_TRANSMIT;
1274 }
1275
1276}
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286static void mgsl_isr_io_pin( struct mgsl_struct *info )
1287{
1288 struct mgsl_icount *icount;
1289 u16 status = usc_InReg( info, MISR );
1290
1291 if ( debug_level >= DEBUG_LEVEL_ISR )
1292 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1293 __FILE__,__LINE__,status);
1294
1295 usc_ClearIrqPendingBits( info, IO_PIN );
1296 usc_UnlatchIostatusBits( info, status );
1297
1298 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1299 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1300 icount = &info->icount;
1301
1302 if (status & MISCSTATUS_RI_LATCHED) {
1303 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1304 usc_DisablestatusIrqs(info,SICR_RI);
1305 icount->rng++;
1306 if ( status & MISCSTATUS_RI )
1307 info->input_signal_events.ri_up++;
1308 else
1309 info->input_signal_events.ri_down++;
1310 }
1311 if (status & MISCSTATUS_DSR_LATCHED) {
1312 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1313 usc_DisablestatusIrqs(info,SICR_DSR);
1314 icount->dsr++;
1315 if ( status & MISCSTATUS_DSR )
1316 info->input_signal_events.dsr_up++;
1317 else
1318 info->input_signal_events.dsr_down++;
1319 }
1320 if (status & MISCSTATUS_DCD_LATCHED) {
1321 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1322 usc_DisablestatusIrqs(info,SICR_DCD);
1323 icount->dcd++;
1324 if (status & MISCSTATUS_DCD) {
1325 info->input_signal_events.dcd_up++;
1326 } else
1327 info->input_signal_events.dcd_down++;
1328#if SYNCLINK_GENERIC_HDLC
1329 if (info->netcount) {
1330 if (status & MISCSTATUS_DCD)
1331 netif_carrier_on(info->netdev);
1332 else
1333 netif_carrier_off(info->netdev);
1334 }
1335#endif
1336 }
1337 if (status & MISCSTATUS_CTS_LATCHED)
1338 {
1339 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1340 usc_DisablestatusIrqs(info,SICR_CTS);
1341 icount->cts++;
1342 if ( status & MISCSTATUS_CTS )
1343 info->input_signal_events.cts_up++;
1344 else
1345 info->input_signal_events.cts_down++;
1346 }
1347 wake_up_interruptible(&info->status_event_wait_q);
1348 wake_up_interruptible(&info->event_wait_q);
1349
1350 if ( (info->port.flags & ASYNC_CHECK_CD) &&
1351 (status & MISCSTATUS_DCD_LATCHED) ) {
1352 if ( debug_level >= DEBUG_LEVEL_ISR )
1353 printk("%s CD now %s...", info->device_name,
1354 (status & MISCSTATUS_DCD) ? "on" : "off");
1355 if (status & MISCSTATUS_DCD)
1356 wake_up_interruptible(&info->port.open_wait);
1357 else {
1358 if ( debug_level >= DEBUG_LEVEL_ISR )
1359 printk("doing serial hangup...");
1360 if (info->port.tty)
1361 tty_hangup(info->port.tty);
1362 }
1363 }
1364
1365 if ( (info->port.flags & ASYNC_CTS_FLOW) &&
1366 (status & MISCSTATUS_CTS_LATCHED) ) {
1367 if (info->port.tty->hw_stopped) {
1368 if (status & MISCSTATUS_CTS) {
1369 if ( debug_level >= DEBUG_LEVEL_ISR )
1370 printk("CTS tx start...");
1371 if (info->port.tty)
1372 info->port.tty->hw_stopped = 0;
1373 usc_start_transmitter(info);
1374 info->pending_bh |= BH_TRANSMIT;
1375 return;
1376 }
1377 } else {
1378 if (!(status & MISCSTATUS_CTS)) {
1379 if ( debug_level >= DEBUG_LEVEL_ISR )
1380 printk("CTS tx stop...");
1381 if (info->port.tty)
1382 info->port.tty->hw_stopped = 1;
1383 usc_stop_transmitter(info);
1384 }
1385 }
1386 }
1387 }
1388
1389 info->pending_bh |= BH_STATUS;
1390
1391
1392 if ( status & MISCSTATUS_TXC_LATCHED ){
1393 usc_OutReg( info, SICR,
1394 (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1395 usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
1396 info->irq_occurred = true;
1397 }
1398
1399}
1400
1401
1402
1403
1404
1405
1406
1407
1408static void mgsl_isr_transmit_data( struct mgsl_struct *info )
1409{
1410 if ( debug_level >= DEBUG_LEVEL_ISR )
1411 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1412 __FILE__,__LINE__,info->xmit_cnt);
1413
1414 usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1415
1416 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1417 usc_stop_transmitter(info);
1418 return;
1419 }
1420
1421 if ( info->xmit_cnt )
1422 usc_load_txfifo( info );
1423 else
1424 info->tx_active = false;
1425
1426 if (info->xmit_cnt < WAKEUP_CHARS)
1427 info->pending_bh |= BH_TRANSMIT;
1428
1429}
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440static void mgsl_isr_receive_data( struct mgsl_struct *info )
1441{
1442 int Fifocount;
1443 u16 status;
1444 int work = 0;
1445 unsigned char DataByte;
1446 struct tty_struct *tty = info->port.tty;
1447 struct mgsl_icount *icount = &info->icount;
1448
1449 if ( debug_level >= DEBUG_LEVEL_ISR )
1450 printk("%s(%d):mgsl_isr_receive_data\n",
1451 __FILE__,__LINE__);
1452
1453 usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1454
1455
1456 usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1457
1458
1459
1460 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1461
1462
1463
1464 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
1465 int flag;
1466
1467
1468 outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1469 info->io_base + CCAR );
1470 DataByte = inb( info->io_base + CCAR );
1471
1472
1473 status = usc_InReg(info, RCSR);
1474 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1475 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) )
1476 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1477
1478 icount->rx++;
1479
1480 flag = 0;
1481 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1482 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) {
1483 printk("rxerr=%04X\n",status);
1484
1485 if ( status & RXSTATUS_BREAK_RECEIVED ) {
1486 status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR);
1487 icount->brk++;
1488 } else if (status & RXSTATUS_PARITY_ERROR)
1489 icount->parity++;
1490 else if (status & RXSTATUS_FRAMING_ERROR)
1491 icount->frame++;
1492 else if (status & RXSTATUS_OVERRUN) {
1493
1494
1495 usc_RTCmd(info,RTCmd_PurgeRxFifo);
1496 icount->overrun++;
1497 }
1498
1499
1500 if (status & info->ignore_status_mask)
1501 continue;
1502
1503 status &= info->read_status_mask;
1504
1505 if (status & RXSTATUS_BREAK_RECEIVED) {
1506 flag = TTY_BREAK;
1507 if (info->port.flags & ASYNC_SAK)
1508 do_SAK(tty);
1509 } else if (status & RXSTATUS_PARITY_ERROR)
1510 flag = TTY_PARITY;
1511 else if (status & RXSTATUS_FRAMING_ERROR)
1512 flag = TTY_FRAME;
1513 }
1514 tty_insert_flip_char(tty, DataByte, flag);
1515 if (status & RXSTATUS_OVERRUN) {
1516
1517
1518
1519
1520 work += tty_insert_flip_char(tty, 0, TTY_OVERRUN);
1521 }
1522 }
1523
1524 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1525 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1526 __FILE__,__LINE__,icount->rx,icount->brk,
1527 icount->parity,icount->frame,icount->overrun);
1528 }
1529
1530 if(work)
1531 tty_flip_buffer_push(tty);
1532}
1533
1534
1535
1536
1537
1538
1539
1540
1541static void mgsl_isr_misc( struct mgsl_struct *info )
1542{
1543 u16 status = usc_InReg( info, MISR );
1544
1545 if ( debug_level >= DEBUG_LEVEL_ISR )
1546 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1547 __FILE__,__LINE__,status);
1548
1549 if ((status & MISCSTATUS_RCC_UNDERRUN) &&
1550 (info->params.mode == MGSL_MODE_HDLC)) {
1551
1552
1553 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
1554 usc_DmaCmd(info, DmaCmd_ResetRxChannel);
1555 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
1556 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
1557 usc_DisableInterrupts(info, RECEIVE_DATA + RECEIVE_STATUS);
1558
1559
1560 info->pending_bh |= BH_RECEIVE;
1561 info->rx_rcc_underrun = true;
1562 }
1563
1564 usc_ClearIrqPendingBits( info, MISC );
1565 usc_UnlatchMiscstatusBits( info, status );
1566
1567}
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577static void mgsl_isr_null( struct mgsl_struct *info )
1578{
1579
1580}
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601static void mgsl_isr_receive_dma( struct mgsl_struct *info )
1602{
1603 u16 status;
1604
1605
1606 usc_OutDmaReg( info, CDIR, BIT9+BIT1 );
1607
1608
1609
1610 status = usc_InDmaReg( info, RDMR );
1611
1612 if ( debug_level >= DEBUG_LEVEL_ISR )
1613 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1614 __FILE__,__LINE__,info->device_name,status);
1615
1616 info->pending_bh |= BH_RECEIVE;
1617
1618 if ( status & BIT3 ) {
1619 info->rx_overflow = true;
1620 info->icount.buf_overrun++;
1621 }
1622
1623}
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
1646{
1647 u16 status;
1648
1649
1650 usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
1651
1652
1653
1654
1655 status = usc_InDmaReg( info, TDMR );
1656
1657 if ( debug_level >= DEBUG_LEVEL_ISR )
1658 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1659 __FILE__,__LINE__,info->device_name,status);
1660
1661 if ( status & BIT2 ) {
1662 --info->tx_dma_buffers_used;
1663
1664
1665
1666
1667 if ( load_next_tx_holding_buffer(info) ) {
1668
1669
1670
1671 info->pending_bh |= BH_TRANSMIT;
1672 }
1673 }
1674
1675}
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688static irqreturn_t mgsl_interrupt(int dummy, void *dev_id)
1689{
1690 struct mgsl_struct *info = dev_id;
1691 u16 UscVector;
1692 u16 DmaVector;
1693
1694 if ( debug_level >= DEBUG_LEVEL_ISR )
1695 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n",
1696 __FILE__, __LINE__, info->irq_level);
1697
1698 spin_lock(&info->irq_spinlock);
1699
1700 for(;;) {
1701
1702 UscVector = usc_InReg(info, IVR) >> 9;
1703 DmaVector = usc_InDmaReg(info, DIVR);
1704
1705 if ( debug_level >= DEBUG_LEVEL_ISR )
1706 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1707 __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1708
1709 if ( !UscVector && !DmaVector )
1710 break;
1711
1712
1713 if ( UscVector )
1714 (*UscIsrTable[UscVector])(info);
1715 else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
1716 mgsl_isr_transmit_dma(info);
1717 else
1718 mgsl_isr_receive_dma(info);
1719
1720 if ( info->isr_overflow ) {
1721 printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n",
1722 __FILE__, __LINE__, info->device_name, info->irq_level);
1723 usc_DisableMasterIrqBit(info);
1724 usc_DisableDmaInterrupts(info,DICR_MASTER);
1725 break;
1726 }
1727 }
1728
1729
1730
1731
1732
1733 if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1734 if ( debug_level >= DEBUG_LEVEL_ISR )
1735 printk("%s(%d):%s queueing bh task.\n",
1736 __FILE__,__LINE__,info->device_name);
1737 schedule_work(&info->task);
1738 info->bh_requested = true;
1739 }
1740
1741 spin_unlock(&info->irq_spinlock);
1742
1743 if ( debug_level >= DEBUG_LEVEL_ISR )
1744 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n",
1745 __FILE__, __LINE__, info->irq_level);
1746
1747 return IRQ_HANDLED;
1748}
1749
1750
1751
1752
1753
1754
1755
1756
1757static int startup(struct mgsl_struct * info)
1758{
1759 int retval = 0;
1760
1761 if ( debug_level >= DEBUG_LEVEL_INFO )
1762 printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1763
1764 if (info->port.flags & ASYNC_INITIALIZED)
1765 return 0;
1766
1767 if (!info->xmit_buf) {
1768
1769 info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1770 if (!info->xmit_buf) {
1771 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1772 __FILE__,__LINE__,info->device_name);
1773 return -ENOMEM;
1774 }
1775 }
1776
1777 info->pending_bh = 0;
1778
1779 memset(&info->icount, 0, sizeof(info->icount));
1780
1781 setup_timer(&info->tx_timer, mgsl_tx_timeout, (unsigned long)info);
1782
1783
1784 retval = mgsl_claim_resources(info);
1785
1786
1787 if ( !retval )
1788 retval = mgsl_adapter_test(info);
1789
1790 if ( retval ) {
1791 if (capable(CAP_SYS_ADMIN) && info->port.tty)
1792 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1793 mgsl_release_resources(info);
1794 return retval;
1795 }
1796
1797
1798 mgsl_change_params(info);
1799
1800 if (info->port.tty)
1801 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1802
1803 info->port.flags |= ASYNC_INITIALIZED;
1804
1805 return 0;
1806
1807}
1808
1809
1810
1811
1812
1813
1814
1815
1816static void shutdown(struct mgsl_struct * info)
1817{
1818 unsigned long flags;
1819
1820 if (!(info->port.flags & ASYNC_INITIALIZED))
1821 return;
1822
1823 if (debug_level >= DEBUG_LEVEL_INFO)
1824 printk("%s(%d):mgsl_shutdown(%s)\n",
1825 __FILE__,__LINE__, info->device_name );
1826
1827
1828
1829 wake_up_interruptible(&info->status_event_wait_q);
1830 wake_up_interruptible(&info->event_wait_q);
1831
1832 del_timer_sync(&info->tx_timer);
1833
1834 if (info->xmit_buf) {
1835 free_page((unsigned long) info->xmit_buf);
1836 info->xmit_buf = NULL;
1837 }
1838
1839 spin_lock_irqsave(&info->irq_spinlock,flags);
1840 usc_DisableMasterIrqBit(info);
1841 usc_stop_receiver(info);
1842 usc_stop_transmitter(info);
1843 usc_DisableInterrupts(info,RECEIVE_DATA + RECEIVE_STATUS +
1844 TRANSMIT_DATA + TRANSMIT_STATUS + IO_PIN + MISC );
1845 usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
1846
1847
1848
1849
1850 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
1851
1852
1853
1854
1855 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
1856
1857 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
1858 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1859 usc_set_serial_signals(info);
1860 }
1861
1862 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1863
1864 mgsl_release_resources(info);
1865
1866 if (info->port.tty)
1867 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1868
1869 info->port.flags &= ~ASYNC_INITIALIZED;
1870
1871}
1872
1873static void mgsl_program_hw(struct mgsl_struct *info)
1874{
1875 unsigned long flags;
1876
1877 spin_lock_irqsave(&info->irq_spinlock,flags);
1878
1879 usc_stop_receiver(info);
1880 usc_stop_transmitter(info);
1881 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1882
1883 if (info->params.mode == MGSL_MODE_HDLC ||
1884 info->params.mode == MGSL_MODE_RAW ||
1885 info->netcount)
1886 usc_set_sync_mode(info);
1887 else
1888 usc_set_async_mode(info);
1889
1890 usc_set_serial_signals(info);
1891
1892 info->dcd_chkcount = 0;
1893 info->cts_chkcount = 0;
1894 info->ri_chkcount = 0;
1895 info->dsr_chkcount = 0;
1896
1897 usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
1898 usc_EnableInterrupts(info, IO_PIN);
1899 usc_get_serial_signals(info);
1900
1901 if (info->netcount || info->port.tty->termios->c_cflag & CREAD)
1902 usc_start_receiver(info);
1903
1904 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1905}
1906
1907
1908
1909static void mgsl_change_params(struct mgsl_struct *info)
1910{
1911 unsigned cflag;
1912 int bits_per_char;
1913
1914 if (!info->port.tty || !info->port.tty->termios)
1915 return;
1916
1917 if (debug_level >= DEBUG_LEVEL_INFO)
1918 printk("%s(%d):mgsl_change_params(%s)\n",
1919 __FILE__,__LINE__, info->device_name );
1920
1921 cflag = info->port.tty->termios->c_cflag;
1922
1923
1924
1925 if (cflag & CBAUD)
1926 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1927 else
1928 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
1929
1930
1931
1932 switch (cflag & CSIZE) {
1933 case CS5: info->params.data_bits = 5; break;
1934 case CS6: info->params.data_bits = 6; break;
1935 case CS7: info->params.data_bits = 7; break;
1936 case CS8: info->params.data_bits = 8; break;
1937
1938 default: info->params.data_bits = 7; break;
1939 }
1940
1941 if (cflag & CSTOPB)
1942 info->params.stop_bits = 2;
1943 else
1944 info->params.stop_bits = 1;
1945
1946 info->params.parity = ASYNC_PARITY_NONE;
1947 if (cflag & PARENB) {
1948 if (cflag & PARODD)
1949 info->params.parity = ASYNC_PARITY_ODD;
1950 else
1951 info->params.parity = ASYNC_PARITY_EVEN;
1952#ifdef CMSPAR
1953 if (cflag & CMSPAR)
1954 info->params.parity = ASYNC_PARITY_SPACE;
1955#endif
1956 }
1957
1958
1959
1960
1961 bits_per_char = info->params.data_bits +
1962 info->params.stop_bits + 1;
1963
1964
1965
1966
1967
1968 if (info->params.data_rate <= 460800)
1969 info->params.data_rate = tty_get_baud_rate(info->port.tty);
1970
1971 if ( info->params.data_rate ) {
1972 info->timeout = (32*HZ*bits_per_char) /
1973 info->params.data_rate;
1974 }
1975 info->timeout += HZ/50;
1976
1977 if (cflag & CRTSCTS)
1978 info->port.flags |= ASYNC_CTS_FLOW;
1979 else
1980 info->port.flags &= ~ASYNC_CTS_FLOW;
1981
1982 if (cflag & CLOCAL)
1983 info->port.flags &= ~ASYNC_CHECK_CD;
1984 else
1985 info->port.flags |= ASYNC_CHECK_CD;
1986
1987
1988
1989 info->read_status_mask = RXSTATUS_OVERRUN;
1990 if (I_INPCK(info->port.tty))
1991 info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1992 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
1993 info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
1994
1995 if (I_IGNPAR(info->port.tty))
1996 info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1997 if (I_IGNBRK(info->port.tty)) {
1998 info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
1999
2000
2001
2002 if (I_IGNPAR(info->port.tty))
2003 info->ignore_status_mask |= RXSTATUS_OVERRUN;
2004 }
2005
2006 mgsl_program_hw(info);
2007
2008}
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019static int mgsl_put_char(struct tty_struct *tty, unsigned char ch)
2020{
2021 struct mgsl_struct *info = tty->driver_data;
2022 unsigned long flags;
2023 int ret = 0;
2024
2025 if (debug_level >= DEBUG_LEVEL_INFO) {
2026 printk(KERN_DEBUG "%s(%d):mgsl_put_char(%d) on %s\n",
2027 __FILE__, __LINE__, ch, info->device_name);
2028 }
2029
2030 if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
2031 return 0;
2032
2033 if (!info->xmit_buf)
2034 return 0;
2035
2036 spin_lock_irqsave(&info->irq_spinlock, flags);
2037
2038 if ((info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active) {
2039 if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2040 info->xmit_buf[info->xmit_head++] = ch;
2041 info->xmit_head &= SERIAL_XMIT_SIZE-1;
2042 info->xmit_cnt++;
2043 ret = 1;
2044 }
2045 }
2046 spin_unlock_irqrestore(&info->irq_spinlock, flags);
2047 return ret;
2048
2049}
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059static void mgsl_flush_chars(struct tty_struct *tty)
2060{
2061 struct mgsl_struct *info = tty->driver_data;
2062 unsigned long flags;
2063
2064 if ( debug_level >= DEBUG_LEVEL_INFO )
2065 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2066 __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2067
2068 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
2069 return;
2070
2071 if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2072 !info->xmit_buf)
2073 return;
2074
2075 if ( debug_level >= DEBUG_LEVEL_INFO )
2076 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2077 __FILE__,__LINE__,info->device_name );
2078
2079 spin_lock_irqsave(&info->irq_spinlock,flags);
2080
2081 if (!info->tx_active) {
2082 if ( (info->params.mode == MGSL_MODE_HDLC ||
2083 info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
2084
2085
2086
2087 mgsl_load_tx_dma_buffer(info,
2088 info->xmit_buf,info->xmit_cnt);
2089 }
2090 usc_start_transmitter(info);
2091 }
2092
2093 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2094
2095}
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109static int mgsl_write(struct tty_struct * tty,
2110 const unsigned char *buf, int count)
2111{
2112 int c, ret = 0;
2113 struct mgsl_struct *info = tty->driver_data;
2114 unsigned long flags;
2115
2116 if ( debug_level >= DEBUG_LEVEL_INFO )
2117 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2118 __FILE__,__LINE__,info->device_name,count);
2119
2120 if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
2121 goto cleanup;
2122
2123 if (!info->xmit_buf)
2124 goto cleanup;
2125
2126 if ( info->params.mode == MGSL_MODE_HDLC ||
2127 info->params.mode == MGSL_MODE_RAW ) {
2128
2129
2130 if (info->tx_active) {
2131
2132 if ( info->params.mode == MGSL_MODE_HDLC ) {
2133 ret = 0;
2134 goto cleanup;
2135 }
2136
2137
2138
2139
2140
2141 if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
2142
2143 ret = 0;
2144 goto cleanup;
2145 }
2146
2147
2148 ret = count;
2149 save_tx_buffer_request(info,buf,count);
2150
2151
2152
2153
2154 spin_lock_irqsave(&info->irq_spinlock,flags);
2155 load_next_tx_holding_buffer(info);
2156 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2157 goto cleanup;
2158 }
2159
2160
2161
2162
2163
2164 if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2165 !usc_loopmode_active(info) )
2166 {
2167 ret = 0;
2168 goto cleanup;
2169 }
2170
2171 if ( info->xmit_cnt ) {
2172
2173
2174 ret = 0;
2175
2176
2177
2178 mgsl_load_tx_dma_buffer(info,
2179 info->xmit_buf,info->xmit_cnt);
2180 if ( debug_level >= DEBUG_LEVEL_INFO )
2181 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2182 __FILE__,__LINE__,info->device_name);
2183 } else {
2184 if ( debug_level >= DEBUG_LEVEL_INFO )
2185 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2186 __FILE__,__LINE__,info->device_name);
2187 ret = count;
2188 info->xmit_cnt = count;
2189 mgsl_load_tx_dma_buffer(info,buf,count);
2190 }
2191 } else {
2192 while (1) {
2193 spin_lock_irqsave(&info->irq_spinlock,flags);
2194 c = min_t(int, count,
2195 min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2196 SERIAL_XMIT_SIZE - info->xmit_head));
2197 if (c <= 0) {
2198 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2199 break;
2200 }
2201 memcpy(info->xmit_buf + info->xmit_head, buf, c);
2202 info->xmit_head = ((info->xmit_head + c) &
2203 (SERIAL_XMIT_SIZE-1));
2204 info->xmit_cnt += c;
2205 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2206 buf += c;
2207 count -= c;
2208 ret += c;
2209 }
2210 }
2211
2212 if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2213 spin_lock_irqsave(&info->irq_spinlock,flags);
2214 if (!info->tx_active)
2215 usc_start_transmitter(info);
2216 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2217 }
2218cleanup:
2219 if ( debug_level >= DEBUG_LEVEL_INFO )
2220 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2221 __FILE__,__LINE__,info->device_name,ret);
2222
2223 return ret;
2224
2225}
2226
2227
2228
2229
2230
2231
2232
2233
2234static int mgsl_write_room(struct tty_struct *tty)
2235{
2236 struct mgsl_struct *info = tty->driver_data;
2237 int ret;
2238
2239 if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
2240 return 0;
2241 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2242 if (ret < 0)
2243 ret = 0;
2244
2245 if (debug_level >= DEBUG_LEVEL_INFO)
2246 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2247 __FILE__,__LINE__, info->device_name,ret );
2248
2249 if ( info->params.mode == MGSL_MODE_HDLC ||
2250 info->params.mode == MGSL_MODE_RAW ) {
2251
2252 if ( info->tx_active )
2253 return 0;
2254 else
2255 return HDLC_MAX_FRAME_SIZE;
2256 }
2257
2258 return ret;
2259
2260}
2261
2262
2263
2264
2265
2266
2267
2268
2269static int mgsl_chars_in_buffer(struct tty_struct *tty)
2270{
2271 struct mgsl_struct *info = tty->driver_data;
2272
2273 if (debug_level >= DEBUG_LEVEL_INFO)
2274 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2275 __FILE__,__LINE__, info->device_name );
2276
2277 if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
2278 return 0;
2279
2280 if (debug_level >= DEBUG_LEVEL_INFO)
2281 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2282 __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2283
2284 if ( info->params.mode == MGSL_MODE_HDLC ||
2285 info->params.mode == MGSL_MODE_RAW ) {
2286
2287 if ( info->tx_active )
2288 return info->max_frame_size;
2289 else
2290 return 0;
2291 }
2292
2293 return info->xmit_cnt;
2294}
2295
2296
2297
2298
2299
2300
2301
2302
2303static void mgsl_flush_buffer(struct tty_struct *tty)
2304{
2305 struct mgsl_struct *info = tty->driver_data;
2306 unsigned long flags;
2307
2308 if (debug_level >= DEBUG_LEVEL_INFO)
2309 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2310 __FILE__,__LINE__, info->device_name );
2311
2312 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
2313 return;
2314
2315 spin_lock_irqsave(&info->irq_spinlock,flags);
2316 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2317 del_timer(&info->tx_timer);
2318 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2319
2320 tty_wakeup(tty);
2321}
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2332{
2333 struct mgsl_struct *info = tty->driver_data;
2334 unsigned long flags;
2335
2336 if (debug_level >= DEBUG_LEVEL_INFO)
2337 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2338 __FILE__,__LINE__, info->device_name, ch );
2339
2340 if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
2341 return;
2342
2343 info->x_char = ch;
2344 if (ch) {
2345
2346 spin_lock_irqsave(&info->irq_spinlock,flags);
2347 if (!info->tx_enabled)
2348 usc_start_transmitter(info);
2349 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2350 }
2351}
2352
2353
2354
2355
2356
2357
2358
2359
2360static void mgsl_throttle(struct tty_struct * tty)
2361{
2362 struct mgsl_struct *info = tty->driver_data;
2363 unsigned long flags;
2364
2365 if (debug_level >= DEBUG_LEVEL_INFO)
2366 printk("%s(%d):mgsl_throttle(%s) entry\n",
2367 __FILE__,__LINE__, info->device_name );
2368
2369 if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
2370 return;
2371
2372 if (I_IXOFF(tty))
2373 mgsl_send_xchar(tty, STOP_CHAR(tty));
2374
2375 if (tty->termios->c_cflag & CRTSCTS) {
2376 spin_lock_irqsave(&info->irq_spinlock,flags);
2377 info->serial_signals &= ~SerialSignal_RTS;
2378 usc_set_serial_signals(info);
2379 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2380 }
2381}
2382
2383
2384
2385
2386
2387
2388
2389
2390static void mgsl_unthrottle(struct tty_struct * tty)
2391{
2392 struct mgsl_struct *info = tty->driver_data;
2393 unsigned long flags;
2394
2395 if (debug_level >= DEBUG_LEVEL_INFO)
2396 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2397 __FILE__,__LINE__, info->device_name );
2398
2399 if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
2400 return;
2401
2402 if (I_IXOFF(tty)) {
2403 if (info->x_char)
2404 info->x_char = 0;
2405 else
2406 mgsl_send_xchar(tty, START_CHAR(tty));
2407 }
2408
2409 if (tty->termios->c_cflag & CRTSCTS) {
2410 spin_lock_irqsave(&info->irq_spinlock,flags);
2411 info->serial_signals |= SerialSignal_RTS;
2412 usc_set_serial_signals(info);
2413 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2414 }
2415
2416}
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
2428{
2429 int err;
2430
2431 if (debug_level >= DEBUG_LEVEL_INFO)
2432 printk("%s(%d):mgsl_get_params(%s)\n",
2433 __FILE__,__LINE__, info->device_name);
2434
2435 if (!user_icount) {
2436 memset(&info->icount, 0, sizeof(info->icount));
2437 } else {
2438 mutex_lock(&info->port.mutex);
2439 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2440 mutex_unlock(&info->port.mutex);
2441 if (err)
2442 return -EFAULT;
2443 }
2444
2445 return 0;
2446
2447}
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
2459{
2460 int err;
2461 if (debug_level >= DEBUG_LEVEL_INFO)
2462 printk("%s(%d):mgsl_get_params(%s)\n",
2463 __FILE__,__LINE__, info->device_name);
2464
2465 mutex_lock(&info->port.mutex);
2466 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2467 mutex_unlock(&info->port.mutex);
2468 if (err) {
2469 if ( debug_level >= DEBUG_LEVEL_INFO )
2470 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2471 __FILE__,__LINE__,info->device_name);
2472 return -EFAULT;
2473 }
2474
2475 return 0;
2476
2477}
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
2491{
2492 unsigned long flags;
2493 MGSL_PARAMS tmp_params;
2494 int err;
2495
2496 if (debug_level >= DEBUG_LEVEL_INFO)
2497 printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2498 info->device_name );
2499 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2500 if (err) {
2501 if ( debug_level >= DEBUG_LEVEL_INFO )
2502 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2503 __FILE__,__LINE__,info->device_name);
2504 return -EFAULT;
2505 }
2506
2507 mutex_lock(&info->port.mutex);
2508 spin_lock_irqsave(&info->irq_spinlock,flags);
2509 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2510 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2511
2512 mgsl_change_params(info);
2513 mutex_unlock(&info->port.mutex);
2514
2515 return 0;
2516
2517}
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
2529{
2530 int err;
2531
2532 if (debug_level >= DEBUG_LEVEL_INFO)
2533 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2534 __FILE__,__LINE__, info->device_name, info->idle_mode);
2535
2536 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2537 if (err) {
2538 if ( debug_level >= DEBUG_LEVEL_INFO )
2539 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2540 __FILE__,__LINE__,info->device_name);
2541 return -EFAULT;
2542 }
2543
2544 return 0;
2545
2546}
2547
2548
2549
2550
2551
2552
2553
2554
2555static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2556{
2557 unsigned long flags;
2558
2559 if (debug_level >= DEBUG_LEVEL_INFO)
2560 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2561 info->device_name, idle_mode );
2562
2563 spin_lock_irqsave(&info->irq_spinlock,flags);
2564 info->idle_mode = idle_mode;
2565 usc_set_txidle( info );
2566 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2567 return 0;
2568
2569}
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582static int mgsl_txenable(struct mgsl_struct * info, int enable)
2583{
2584 unsigned long flags;
2585
2586 if (debug_level >= DEBUG_LEVEL_INFO)
2587 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2588 info->device_name, enable);
2589
2590 spin_lock_irqsave(&info->irq_spinlock,flags);
2591 if ( enable ) {
2592 if ( !info->tx_enabled ) {
2593
2594 usc_start_transmitter(info);
2595
2596
2597
2598
2599
2600
2601
2602 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2603 usc_loopmode_insert_request( info );
2604 }
2605 } else {
2606 if ( info->tx_enabled )
2607 usc_stop_transmitter(info);
2608 }
2609 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2610 return 0;
2611
2612}
2613
2614
2615
2616
2617
2618
2619static int mgsl_txabort(struct mgsl_struct * info)
2620{
2621 unsigned long flags;
2622
2623 if (debug_level >= DEBUG_LEVEL_INFO)
2624 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2625 info->device_name);
2626
2627 spin_lock_irqsave(&info->irq_spinlock,flags);
2628 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2629 {
2630 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2631 usc_loopmode_cancel_transmit( info );
2632 else
2633 usc_TCmd(info,TCmd_SendAbort);
2634 }
2635 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2636 return 0;
2637
2638}
2639
2640
2641
2642
2643
2644
2645
2646static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2647{
2648 unsigned long flags;
2649
2650 if (debug_level >= DEBUG_LEVEL_INFO)
2651 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2652 info->device_name, enable);
2653
2654 spin_lock_irqsave(&info->irq_spinlock,flags);
2655 if ( enable ) {
2656 if ( !info->rx_enabled )
2657 usc_start_receiver(info);
2658 } else {
2659 if ( info->rx_enabled )
2660 usc_stop_receiver(info);
2661 }
2662 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2663 return 0;
2664
2665}
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
2676{
2677 unsigned long flags;
2678 int s;
2679 int rc=0;
2680 struct mgsl_icount cprev, cnow;
2681 int events;
2682 int mask;
2683 struct _input_signal_events oldsigs, newsigs;
2684 DECLARE_WAITQUEUE(wait, current);
2685
2686 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2687 if (rc) {
2688 return -EFAULT;
2689 }
2690
2691 if (debug_level >= DEBUG_LEVEL_INFO)
2692 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2693 info->device_name, mask);
2694
2695 spin_lock_irqsave(&info->irq_spinlock,flags);
2696
2697
2698 usc_get_serial_signals(info);
2699 s = info->serial_signals;
2700 events = mask &
2701 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2702 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2703 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2704 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2705 if (events) {
2706 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2707 goto exit;
2708 }
2709
2710
2711 cprev = info->icount;
2712 oldsigs = info->input_signal_events;
2713
2714
2715 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2716 u16 oldreg = usc_InReg(info,RICR);
2717 u16 newreg = oldreg +
2718 (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
2719 (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
2720 if (oldreg != newreg)
2721 usc_OutReg(info, RICR, newreg);
2722 }
2723
2724 set_current_state(TASK_INTERRUPTIBLE);
2725 add_wait_queue(&info->event_wait_q, &wait);
2726
2727 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2728
2729
2730 for(;;) {
2731 schedule();
2732 if (signal_pending(current)) {
2733 rc = -ERESTARTSYS;
2734 break;
2735 }
2736
2737
2738 spin_lock_irqsave(&info->irq_spinlock,flags);
2739 cnow = info->icount;
2740 newsigs = info->input_signal_events;
2741 set_current_state(TASK_INTERRUPTIBLE);
2742 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2743
2744
2745 if (newsigs.dsr_up == oldsigs.dsr_up &&
2746 newsigs.dsr_down == oldsigs.dsr_down &&
2747 newsigs.dcd_up == oldsigs.dcd_up &&
2748 newsigs.dcd_down == oldsigs.dcd_down &&
2749 newsigs.cts_up == oldsigs.cts_up &&
2750 newsigs.cts_down == oldsigs.cts_down &&
2751 newsigs.ri_up == oldsigs.ri_up &&
2752 newsigs.ri_down == oldsigs.ri_down &&
2753 cnow.exithunt == cprev.exithunt &&
2754 cnow.rxidle == cprev.rxidle) {
2755 rc = -EIO;
2756 break;
2757 }
2758
2759 events = mask &
2760 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2761 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2762 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2763 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2764 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2765 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2766 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2767 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2768 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2769 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2770 if (events)
2771 break;
2772
2773 cprev = cnow;
2774 oldsigs = newsigs;
2775 }
2776
2777 remove_wait_queue(&info->event_wait_q, &wait);
2778 set_current_state(TASK_RUNNING);
2779
2780 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2781 spin_lock_irqsave(&info->irq_spinlock,flags);
2782 if (!waitqueue_active(&info->event_wait_q)) {
2783
2784 usc_OutReg(info, RICR, usc_InReg(info,RICR) &
2785 ~(RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED));
2786 }
2787 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2788 }
2789exit:
2790 if ( rc == 0 )
2791 PUT_USER(rc, events, mask_ptr);
2792
2793 return rc;
2794
2795}
2796
2797static int modem_input_wait(struct mgsl_struct *info,int arg)
2798{
2799 unsigned long flags;
2800 int rc;
2801 struct mgsl_icount cprev, cnow;
2802 DECLARE_WAITQUEUE(wait, current);
2803
2804
2805 spin_lock_irqsave(&info->irq_spinlock,flags);
2806 cprev = info->icount;
2807 add_wait_queue(&info->status_event_wait_q, &wait);
2808 set_current_state(TASK_INTERRUPTIBLE);
2809 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2810
2811 for(;;) {
2812 schedule();
2813 if (signal_pending(current)) {
2814 rc = -ERESTARTSYS;
2815 break;
2816 }
2817
2818
2819 spin_lock_irqsave(&info->irq_spinlock,flags);
2820 cnow = info->icount;
2821 set_current_state(TASK_INTERRUPTIBLE);
2822 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2823
2824
2825 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2826 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2827 rc = -EIO;
2828 break;
2829 }
2830
2831
2832 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2833 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2834 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2835 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2836 rc = 0;
2837 break;
2838 }
2839
2840 cprev = cnow;
2841 }
2842 remove_wait_queue(&info->status_event_wait_q, &wait);
2843 set_current_state(TASK_RUNNING);
2844 return rc;
2845}
2846
2847
2848
2849static int tiocmget(struct tty_struct *tty, struct file *file)
2850{
2851 struct mgsl_struct *info = tty->driver_data;
2852 unsigned int result;
2853 unsigned long flags;
2854
2855 spin_lock_irqsave(&info->irq_spinlock,flags);
2856 usc_get_serial_signals(info);
2857 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2858
2859 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2860 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2861 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2862 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2863 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2864 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2865
2866 if (debug_level >= DEBUG_LEVEL_INFO)
2867 printk("%s(%d):%s tiocmget() value=%08X\n",
2868 __FILE__,__LINE__, info->device_name, result );
2869 return result;
2870}
2871
2872
2873
2874static int tiocmset(struct tty_struct *tty, struct file *file,
2875 unsigned int set, unsigned int clear)
2876{
2877 struct mgsl_struct *info = tty->driver_data;
2878 unsigned long flags;
2879
2880 if (debug_level >= DEBUG_LEVEL_INFO)
2881 printk("%s(%d):%s tiocmset(%x,%x)\n",
2882 __FILE__,__LINE__,info->device_name, set, clear);
2883
2884 if (set & TIOCM_RTS)
2885 info->serial_signals |= SerialSignal_RTS;
2886 if (set & TIOCM_DTR)
2887 info->serial_signals |= SerialSignal_DTR;
2888 if (clear & TIOCM_RTS)
2889 info->serial_signals &= ~SerialSignal_RTS;
2890 if (clear & TIOCM_DTR)
2891 info->serial_signals &= ~SerialSignal_DTR;
2892
2893 spin_lock_irqsave(&info->irq_spinlock,flags);
2894 usc_set_serial_signals(info);
2895 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2896
2897 return 0;
2898}
2899
2900
2901
2902
2903
2904
2905
2906static int mgsl_break(struct tty_struct *tty, int break_state)
2907{
2908 struct mgsl_struct * info = tty->driver_data;
2909 unsigned long flags;
2910
2911 if (debug_level >= DEBUG_LEVEL_INFO)
2912 printk("%s(%d):mgsl_break(%s,%d)\n",
2913 __FILE__,__LINE__, info->device_name, break_state);
2914
2915 if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
2916 return -EINVAL;
2917
2918 spin_lock_irqsave(&info->irq_spinlock,flags);
2919 if (break_state == -1)
2920 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2921 else
2922 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
2923 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2924 return 0;
2925
2926}
2927
2928
2929
2930
2931
2932
2933
2934static int msgl_get_icount(struct tty_struct *tty,
2935 struct serial_icounter_struct *icount)
2936
2937{
2938 struct mgsl_struct * info = tty->driver_data;
2939 struct mgsl_icount cnow;
2940 unsigned long flags;
2941
2942 spin_lock_irqsave(&info->irq_spinlock,flags);
2943 cnow = info->icount;
2944 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2945
2946 icount->cts = cnow.cts;
2947 icount->dsr = cnow.dsr;
2948 icount->rng = cnow.rng;
2949 icount->dcd = cnow.dcd;
2950 icount->rx = cnow.rx;
2951 icount->tx = cnow.tx;
2952 icount->frame = cnow.frame;
2953 icount->overrun = cnow.overrun;
2954 icount->parity = cnow.parity;
2955 icount->brk = cnow.brk;
2956 icount->buf_overrun = cnow.buf_overrun;
2957 return 0;
2958}
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971static int mgsl_ioctl(struct tty_struct *tty, struct file * file,
2972 unsigned int cmd, unsigned long arg)
2973{
2974 struct mgsl_struct * info = tty->driver_data;
2975
2976 if (debug_level >= DEBUG_LEVEL_INFO)
2977 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2978 info->device_name, cmd );
2979
2980 if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
2981 return -ENODEV;
2982
2983 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
2984 (cmd != TIOCMIWAIT)) {
2985 if (tty->flags & (1 << TTY_IO_ERROR))
2986 return -EIO;
2987 }
2988
2989 return mgsl_ioctl_common(info, cmd, arg);
2990}
2991
2992static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
2993{
2994 void __user *argp = (void __user *)arg;
2995
2996 switch (cmd) {
2997 case MGSL_IOCGPARAMS:
2998 return mgsl_get_params(info, argp);
2999 case MGSL_IOCSPARAMS:
3000 return mgsl_set_params(info, argp);
3001 case MGSL_IOCGTXIDLE:
3002 return mgsl_get_txidle(info, argp);
3003 case MGSL_IOCSTXIDLE:
3004 return mgsl_set_txidle(info,(int)arg);
3005 case MGSL_IOCTXENABLE:
3006 return mgsl_txenable(info,(int)arg);
3007 case MGSL_IOCRXENABLE:
3008 return mgsl_rxenable(info,(int)arg);
3009 case MGSL_IOCTXABORT:
3010 return mgsl_txabort(info);
3011 case MGSL_IOCGSTATS:
3012 return mgsl_get_stats(info, argp);
3013 case MGSL_IOCWAITEVENT:
3014 return mgsl_wait_event(info, argp);
3015 case MGSL_IOCLOOPTXDONE:
3016 return mgsl_loopmode_send_done(info);
3017
3018
3019
3020 case TIOCMIWAIT:
3021 return modem_input_wait(info,(int)arg);
3022
3023 default:
3024 return -ENOIOCTLCMD;
3025 }
3026 return 0;
3027}
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3041{
3042 struct mgsl_struct *info = tty->driver_data;
3043 unsigned long flags;
3044
3045 if (debug_level >= DEBUG_LEVEL_INFO)
3046 printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3047 tty->driver->name );
3048
3049 mgsl_change_params(info);
3050
3051
3052 if (old_termios->c_cflag & CBAUD &&
3053 !(tty->termios->c_cflag & CBAUD)) {
3054 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3055 spin_lock_irqsave(&info->irq_spinlock,flags);
3056 usc_set_serial_signals(info);
3057 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3058 }
3059
3060
3061 if (!(old_termios->c_cflag & CBAUD) &&
3062 tty->termios->c_cflag & CBAUD) {
3063 info->serial_signals |= SerialSignal_DTR;
3064 if (!(tty->termios->c_cflag & CRTSCTS) ||
3065 !test_bit(TTY_THROTTLED, &tty->flags)) {
3066 info->serial_signals |= SerialSignal_RTS;
3067 }
3068 spin_lock_irqsave(&info->irq_spinlock,flags);
3069 usc_set_serial_signals(info);
3070 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3071 }
3072
3073
3074 if (old_termios->c_cflag & CRTSCTS &&
3075 !(tty->termios->c_cflag & CRTSCTS)) {
3076 tty->hw_stopped = 0;
3077 mgsl_start(tty);
3078 }
3079
3080}
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094static void mgsl_close(struct tty_struct *tty, struct file * filp)
3095{
3096 struct mgsl_struct * info = tty->driver_data;
3097
3098 if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
3099 return;
3100
3101 if (debug_level >= DEBUG_LEVEL_INFO)
3102 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3103 __FILE__,__LINE__, info->device_name, info->port.count);
3104
3105 if (tty_port_close_start(&info->port, tty, filp) == 0)
3106 goto cleanup;
3107
3108 mutex_lock(&info->port.mutex);
3109 if (info->port.flags & ASYNC_INITIALIZED)
3110 mgsl_wait_until_sent(tty, info->timeout);
3111 mgsl_flush_buffer(tty);
3112 tty_ldisc_flush(tty);
3113 shutdown(info);
3114 mutex_unlock(&info->port.mutex);
3115
3116 tty_port_close_end(&info->port, tty);
3117 info->port.tty = NULL;
3118cleanup:
3119 if (debug_level >= DEBUG_LEVEL_INFO)
3120 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
3121 tty->driver->name, info->port.count);
3122
3123}
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3137{
3138 struct mgsl_struct * info = tty->driver_data;
3139 unsigned long orig_jiffies, char_time;
3140
3141 if (!info )
3142 return;
3143
3144 if (debug_level >= DEBUG_LEVEL_INFO)
3145 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3146 __FILE__,__LINE__, info->device_name );
3147
3148 if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
3149 return;
3150
3151 if (!(info->port.flags & ASYNC_INITIALIZED))
3152 goto exit;
3153
3154 orig_jiffies = jiffies;
3155
3156
3157
3158
3159
3160
3161
3162 if ( info->params.data_rate ) {
3163 char_time = info->timeout/(32 * 5);
3164 if (!char_time)
3165 char_time++;
3166 } else
3167 char_time = 1;
3168
3169 if (timeout)
3170 char_time = min_t(unsigned long, char_time, timeout);
3171
3172 if ( info->params.mode == MGSL_MODE_HDLC ||
3173 info->params.mode == MGSL_MODE_RAW ) {
3174 while (info->tx_active) {
3175 msleep_interruptible(jiffies_to_msecs(char_time));
3176 if (signal_pending(current))
3177 break;
3178 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3179 break;
3180 }
3181 } else {
3182 while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3183 info->tx_enabled) {
3184 msleep_interruptible(jiffies_to_msecs(char_time));
3185 if (signal_pending(current))
3186 break;
3187 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3188 break;
3189 }
3190 }
3191
3192exit:
3193 if (debug_level >= DEBUG_LEVEL_INFO)
3194 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3195 __FILE__,__LINE__, info->device_name );
3196
3197}
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207static void mgsl_hangup(struct tty_struct *tty)
3208{
3209 struct mgsl_struct * info = tty->driver_data;
3210
3211 if (debug_level >= DEBUG_LEVEL_INFO)
3212 printk("%s(%d):mgsl_hangup(%s)\n",
3213 __FILE__,__LINE__, info->device_name );
3214
3215 if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
3216 return;
3217
3218 mgsl_flush_buffer(tty);
3219 shutdown(info);
3220
3221 info->port.count = 0;
3222 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
3223 info->port.tty = NULL;
3224
3225 wake_up_interruptible(&info->port.open_wait);
3226
3227}
3228
3229
3230
3231
3232
3233
3234
3235static int carrier_raised(struct tty_port *port)
3236{
3237 unsigned long flags;
3238 struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3239
3240 spin_lock_irqsave(&info->irq_spinlock, flags);
3241 usc_get_serial_signals(info);
3242 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3243 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3244}
3245
3246static void dtr_rts(struct tty_port *port, int on)
3247{
3248 struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3249 unsigned long flags;
3250
3251 spin_lock_irqsave(&info->irq_spinlock,flags);
3252 if (on)
3253 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3254 else
3255 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3256 usc_set_serial_signals(info);
3257 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3258}
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274static int block_til_ready(struct tty_struct *tty, struct file * filp,
3275 struct mgsl_struct *info)
3276{
3277 DECLARE_WAITQUEUE(wait, current);
3278 int retval;
3279 bool do_clocal = false;
3280 bool extra_count = false;
3281 unsigned long flags;
3282 int dcd;
3283 struct tty_port *port = &info->port;
3284
3285 if (debug_level >= DEBUG_LEVEL_INFO)
3286 printk("%s(%d):block_til_ready on %s\n",
3287 __FILE__,__LINE__, tty->driver->name );
3288
3289 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3290
3291 port->flags |= ASYNC_NORMAL_ACTIVE;
3292 return 0;
3293 }
3294
3295 if (tty->termios->c_cflag & CLOCAL)
3296 do_clocal = true;
3297
3298
3299
3300
3301
3302
3303
3304
3305 retval = 0;
3306 add_wait_queue(&port->open_wait, &wait);
3307
3308 if (debug_level >= DEBUG_LEVEL_INFO)
3309 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3310 __FILE__,__LINE__, tty->driver->name, port->count );
3311
3312 spin_lock_irqsave(&info->irq_spinlock, flags);
3313 if (!tty_hung_up_p(filp)) {
3314 extra_count = true;
3315 port->count--;
3316 }
3317 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3318 port->blocked_open++;
3319
3320 while (1) {
3321 if (tty->termios->c_cflag & CBAUD)
3322 tty_port_raise_dtr_rts(port);
3323
3324 set_current_state(TASK_INTERRUPTIBLE);
3325
3326 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3327 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3328 -EAGAIN : -ERESTARTSYS;
3329 break;
3330 }
3331
3332 dcd = tty_port_carrier_raised(&info->port);
3333
3334 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || dcd))
3335 break;
3336
3337 if (signal_pending(current)) {
3338 retval = -ERESTARTSYS;
3339 break;
3340 }
3341
3342 if (debug_level >= DEBUG_LEVEL_INFO)
3343 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3344 __FILE__,__LINE__, tty->driver->name, port->count );
3345
3346 tty_unlock();
3347 schedule();
3348 tty_lock();
3349 }
3350
3351 set_current_state(TASK_RUNNING);
3352 remove_wait_queue(&port->open_wait, &wait);
3353
3354
3355 if (extra_count)
3356 port->count++;
3357 port->blocked_open--;
3358
3359 if (debug_level >= DEBUG_LEVEL_INFO)
3360 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3361 __FILE__,__LINE__, tty->driver->name, port->count );
3362
3363 if (!retval)
3364 port->flags |= ASYNC_NORMAL_ACTIVE;
3365
3366 return retval;
3367
3368}
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380static int mgsl_open(struct tty_struct *tty, struct file * filp)
3381{
3382 struct mgsl_struct *info;
3383 int retval, line;
3384 unsigned long flags;
3385
3386
3387 line = tty->index;
3388 if ((line < 0) || (line >= mgsl_device_count)) {
3389 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3390 __FILE__,__LINE__,line);
3391 return -ENODEV;
3392 }
3393
3394
3395 info = mgsl_device_list;
3396 while(info && info->line != line)
3397 info = info->next_device;
3398 if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
3399 return -ENODEV;
3400
3401 tty->driver_data = info;
3402 info->port.tty = tty;
3403
3404 if (debug_level >= DEBUG_LEVEL_INFO)
3405 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3406 __FILE__,__LINE__,tty->driver->name, info->port.count);
3407
3408
3409 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
3410 if (info->port.flags & ASYNC_CLOSING)
3411 interruptible_sleep_on(&info->port.close_wait);
3412 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
3413 -EAGAIN : -ERESTARTSYS);
3414 goto cleanup;
3415 }
3416
3417 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3418
3419 spin_lock_irqsave(&info->netlock, flags);
3420 if (info->netcount) {
3421 retval = -EBUSY;
3422 spin_unlock_irqrestore(&info->netlock, flags);
3423 goto cleanup;
3424 }
3425 info->port.count++;
3426 spin_unlock_irqrestore(&info->netlock, flags);
3427
3428 if (info->port.count == 1) {
3429
3430 retval = startup(info);
3431 if (retval < 0)
3432 goto cleanup;
3433 }
3434
3435 retval = block_til_ready(tty, filp, info);
3436 if (retval) {
3437 if (debug_level >= DEBUG_LEVEL_INFO)
3438 printk("%s(%d):block_til_ready(%s) returned %d\n",
3439 __FILE__,__LINE__, info->device_name, retval);
3440 goto cleanup;
3441 }
3442
3443 if (debug_level >= DEBUG_LEVEL_INFO)
3444 printk("%s(%d):mgsl_open(%s) success\n",
3445 __FILE__,__LINE__, info->device_name);
3446 retval = 0;
3447
3448cleanup:
3449 if (retval) {
3450 if (tty->count == 1)
3451 info->port.tty = NULL;
3452 if(info->port.count)
3453 info->port.count--;
3454 }
3455
3456 return retval;
3457
3458}
3459
3460
3461
3462
3463
3464static inline void line_info(struct seq_file *m, struct mgsl_struct *info)
3465{
3466 char stat_buf[30];
3467 unsigned long flags;
3468
3469 if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3470 seq_printf(m, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3471 info->device_name, info->io_base, info->irq_level,
3472 info->phys_memory_base, info->phys_lcr_base);
3473 } else {
3474 seq_printf(m, "%s:(E)ISA io:%04X irq:%d dma:%d",
3475 info->device_name, info->io_base,
3476 info->irq_level, info->dma_level);
3477 }
3478
3479
3480 spin_lock_irqsave(&info->irq_spinlock,flags);
3481 usc_get_serial_signals(info);
3482 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3483
3484 stat_buf[0] = 0;
3485 stat_buf[1] = 0;
3486 if (info->serial_signals & SerialSignal_RTS)
3487 strcat(stat_buf, "|RTS");
3488 if (info->serial_signals & SerialSignal_CTS)
3489 strcat(stat_buf, "|CTS");
3490 if (info->serial_signals & SerialSignal_DTR)
3491 strcat(stat_buf, "|DTR");
3492 if (info->serial_signals & SerialSignal_DSR)
3493 strcat(stat_buf, "|DSR");
3494 if (info->serial_signals & SerialSignal_DCD)
3495 strcat(stat_buf, "|CD");
3496 if (info->serial_signals & SerialSignal_RI)
3497 strcat(stat_buf, "|RI");
3498
3499 if (info->params.mode == MGSL_MODE_HDLC ||
3500 info->params.mode == MGSL_MODE_RAW ) {
3501 seq_printf(m, " HDLC txok:%d rxok:%d",
3502 info->icount.txok, info->icount.rxok);
3503 if (info->icount.txunder)
3504 seq_printf(m, " txunder:%d", info->icount.txunder);
3505 if (info->icount.txabort)
3506 seq_printf(m, " txabort:%d", info->icount.txabort);
3507 if (info->icount.rxshort)
3508 seq_printf(m, " rxshort:%d", info->icount.rxshort);
3509 if (info->icount.rxlong)
3510 seq_printf(m, " rxlong:%d", info->icount.rxlong);
3511 if (info->icount.rxover)
3512 seq_printf(m, " rxover:%d", info->icount.rxover);
3513 if (info->icount.rxcrc)
3514 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
3515 } else {
3516 seq_printf(m, " ASYNC tx:%d rx:%d",
3517 info->icount.tx, info->icount.rx);
3518 if (info->icount.frame)
3519 seq_printf(m, " fe:%d", info->icount.frame);
3520 if (info->icount.parity)
3521 seq_printf(m, " pe:%d", info->icount.parity);
3522 if (info->icount.brk)
3523 seq_printf(m, " brk:%d", info->icount.brk);
3524 if (info->icount.overrun)
3525 seq_printf(m, " oe:%d", info->icount.overrun);
3526 }
3527
3528
3529 seq_printf(m, " %s\n", stat_buf+1);
3530
3531 seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3532 info->tx_active,info->bh_requested,info->bh_running,
3533 info->pending_bh);
3534
3535 spin_lock_irqsave(&info->irq_spinlock,flags);
3536 {
3537 u16 Tcsr = usc_InReg( info, TCSR );
3538 u16 Tdmr = usc_InDmaReg( info, TDMR );
3539 u16 Ticr = usc_InReg( info, TICR );
3540 u16 Rscr = usc_InReg( info, RCSR );
3541 u16 Rdmr = usc_InDmaReg( info, RDMR );
3542 u16 Ricr = usc_InReg( info, RICR );
3543 u16 Icr = usc_InReg( info, ICR );
3544 u16 Dccr = usc_InReg( info, DCCR );
3545 u16 Tmr = usc_InReg( info, TMR );
3546 u16 Tccr = usc_InReg( info, TCCR );
3547 u16 Ccar = inw( info->io_base + CCAR );
3548 seq_printf(m, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3549 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3550 Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3551 }
3552 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3553}
3554
3555
3556static int mgsl_proc_show(struct seq_file *m, void *v)
3557{
3558 struct mgsl_struct *info;
3559
3560 seq_printf(m, "synclink driver:%s\n", driver_version);
3561
3562 info = mgsl_device_list;
3563 while( info ) {
3564 line_info(m, info);
3565 info = info->next_device;
3566 }
3567 return 0;
3568}
3569
3570static int mgsl_proc_open(struct inode *inode, struct file *file)
3571{
3572 return single_open(file, mgsl_proc_show, NULL);
3573}
3574
3575static const struct file_operations mgsl_proc_fops = {
3576 .owner = THIS_MODULE,
3577 .open = mgsl_proc_open,
3578 .read = seq_read,
3579 .llseek = seq_lseek,
3580 .release = single_release,
3581};
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3592{
3593 unsigned short BuffersPerFrame;
3594
3595 info->last_mem_alloc = 0;
3596
3597
3598
3599
3600
3601
3602 BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3603 if ( info->max_frame_size % DMABUFFERSIZE )
3604 BuffersPerFrame++;
3605
3606 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3630 info->rx_buffer_count = 62 - info->tx_buffer_count;
3631 } else {
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3643 info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3644
3645
3646
3647
3648
3649
3650 if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3651 info->rx_buffer_count = 62 - info->tx_buffer_count;
3652
3653 }
3654
3655 if ( debug_level >= DEBUG_LEVEL_INFO )
3656 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3657 __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3658
3659 if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3660 mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
3661 mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
3662 mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
3663 mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
3664 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3665 return -ENOMEM;
3666 }
3667
3668 mgsl_reset_rx_dma_buffers( info );
3669 mgsl_reset_tx_dma_buffers( info );
3670
3671 return 0;
3672
3673}
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3699{
3700 unsigned int i;
3701
3702 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3703
3704 info->buffer_list = info->memory_base + info->last_mem_alloc;
3705 info->buffer_list_phys = info->last_mem_alloc;
3706 info->last_mem_alloc += BUFFERLISTSIZE;
3707 } else {
3708
3709
3710
3711
3712
3713
3714 info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL);
3715 if (info->buffer_list == NULL)
3716 return -ENOMEM;
3717 info->buffer_list_phys = (u32)(info->buffer_list_dma_addr);
3718 }
3719
3720
3721
3722 memset( info->buffer_list, 0, BUFFERLISTSIZE );
3723
3724
3725
3726
3727 info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3728 info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3729 info->tx_buffer_list += info->rx_buffer_count;
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740 for ( i = 0; i < info->rx_buffer_count; i++ ) {
3741
3742 info->rx_buffer_list[i].phys_entry =
3743 info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3744
3745
3746
3747
3748 info->rx_buffer_list[i].link = info->buffer_list_phys;
3749
3750 if ( i < info->rx_buffer_count - 1 )
3751 info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3752 }
3753
3754 for ( i = 0; i < info->tx_buffer_count; i++ ) {
3755
3756 info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3757 ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3758
3759
3760
3761
3762 info->tx_buffer_list[i].link = info->buffer_list_phys +
3763 info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3764
3765 if ( i < info->tx_buffer_count - 1 )
3766 info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3767 }
3768
3769 return 0;
3770
3771}
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3783{
3784 if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI)
3785 dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr);
3786
3787 info->buffer_list = NULL;
3788 info->rx_buffer_list = NULL;
3789 info->tx_buffer_list = NULL;
3790
3791}
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3810{
3811 int i;
3812 u32 phys_addr;
3813
3814
3815
3816 for ( i = 0; i < Buffercount; i++ ) {
3817 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3818
3819 BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3820 phys_addr = info->last_mem_alloc;
3821 info->last_mem_alloc += DMABUFFERSIZE;
3822 } else {
3823
3824 BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL);
3825 if (BufferList[i].virt_addr == NULL)
3826 return -ENOMEM;
3827 phys_addr = (u32)(BufferList[i].dma_addr);
3828 }
3829 BufferList[i].phys_addr = phys_addr;
3830 }
3831
3832 return 0;
3833
3834}
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
3851{
3852 int i;
3853
3854 if ( BufferList ) {
3855 for ( i = 0 ; i < Buffercount ; i++ ) {
3856 if ( BufferList[i].virt_addr ) {
3857 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
3858 dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr);
3859 BufferList[i].virt_addr = NULL;
3860 }
3861 }
3862 }
3863
3864}
3865
3866
3867
3868
3869
3870
3871
3872
3873static void mgsl_free_dma_buffers( struct mgsl_struct *info )
3874{
3875 mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
3876 mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
3877 mgsl_free_buffer_list_memory( info );
3878
3879}
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3895{
3896 info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
3897 if ( info->intermediate_rxbuffer == NULL )
3898 return -ENOMEM;
3899
3900 return 0;
3901
3902}
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3915{
3916 kfree(info->intermediate_rxbuffer);
3917 info->intermediate_rxbuffer = NULL;
3918
3919}
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
3935{
3936 int i;
3937
3938 if ( debug_level >= DEBUG_LEVEL_INFO )
3939 printk("%s %s(%d) allocating %d tx holding buffers\n",
3940 info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
3941
3942 memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
3943
3944 for ( i=0; i<info->num_tx_holding_buffers; ++i) {
3945 info->tx_holding_buffers[i].buffer =
3946 kmalloc(info->max_frame_size, GFP_KERNEL);
3947 if (info->tx_holding_buffers[i].buffer == NULL) {
3948 for (--i; i >= 0; i--) {
3949 kfree(info->tx_holding_buffers[i].buffer);
3950 info->tx_holding_buffers[i].buffer = NULL;
3951 }
3952 return -ENOMEM;
3953 }
3954 }
3955
3956 return 0;
3957
3958}
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
3971{
3972 int i;
3973
3974 for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
3975 kfree(info->tx_holding_buffers[i].buffer);
3976 info->tx_holding_buffers[i].buffer = NULL;
3977 }
3978
3979 info->get_tx_holding_index = 0;
3980 info->put_tx_holding_index = 0;
3981 info->tx_holding_count = 0;
3982
3983}
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000static bool load_next_tx_holding_buffer(struct mgsl_struct *info)
4001{
4002 bool ret = false;
4003
4004 if ( info->tx_holding_count ) {
4005
4006
4007
4008 struct tx_holding_buffer *ptx =
4009 &info->tx_holding_buffers[info->get_tx_holding_index];
4010 int num_free = num_free_tx_dma_buffers(info);
4011 int num_needed = ptx->buffer_size / DMABUFFERSIZE;
4012 if ( ptx->buffer_size % DMABUFFERSIZE )
4013 ++num_needed;
4014
4015 if (num_needed <= num_free) {
4016 info->xmit_cnt = ptx->buffer_size;
4017 mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
4018
4019 --info->tx_holding_count;
4020 if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
4021 info->get_tx_holding_index=0;
4022
4023
4024 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
4025
4026 ret = true;
4027 }
4028 }
4029
4030 return ret;
4031}
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
4047{
4048 struct tx_holding_buffer *ptx;
4049
4050 if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
4051 return 0;
4052 }
4053
4054 ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
4055 ptx->buffer_size = BufferSize;
4056 memcpy( ptx->buffer, Buffer, BufferSize);
4057
4058 ++info->tx_holding_count;
4059 if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
4060 info->put_tx_holding_index=0;
4061
4062 return 1;
4063}
4064
4065static int mgsl_claim_resources(struct mgsl_struct *info)
4066{
4067 if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4068 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4069 __FILE__,__LINE__,info->device_name, info->io_base);
4070 return -ENODEV;
4071 }
4072 info->io_addr_requested = true;
4073
4074 if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4075 info->device_name, info ) < 0 ) {
4076 printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
4077 __FILE__,__LINE__,info->device_name, info->irq_level );
4078 goto errout;
4079 }
4080 info->irq_requested = true;
4081
4082 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4083 if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4084 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4085 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4086 goto errout;
4087 }
4088 info->shared_mem_requested = true;
4089 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4090 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4091 __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4092 goto errout;
4093 }
4094 info->lcr_mem_requested = true;
4095
4096 info->memory_base = ioremap_nocache(info->phys_memory_base,
4097 0x40000);
4098 if (!info->memory_base) {
4099 printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
4100 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4101 goto errout;
4102 }
4103
4104 if ( !mgsl_memory_test(info) ) {
4105 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4106 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4107 goto errout;
4108 }
4109
4110 info->lcr_base = ioremap_nocache(info->phys_lcr_base,
4111 PAGE_SIZE);
4112 if (!info->lcr_base) {
4113 printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
4114 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4115 goto errout;
4116 }
4117 info->lcr_base += info->lcr_offset;
4118
4119 } else {
4120
4121
4122 if (request_dma(info->dma_level,info->device_name) < 0){
4123 printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
4124 __FILE__,__LINE__,info->device_name, info->dma_level );
4125 mgsl_release_resources( info );
4126 return -ENODEV;
4127 }
4128 info->dma_requested = true;
4129
4130
4131 set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4132 enable_dma(info->dma_level);
4133 }
4134
4135 if ( mgsl_allocate_dma_buffers(info) < 0 ) {
4136 printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
4137 __FILE__,__LINE__,info->device_name, info->dma_level );
4138 goto errout;
4139 }
4140
4141 return 0;
4142errout:
4143 mgsl_release_resources(info);
4144 return -ENODEV;
4145
4146}
4147
4148static void mgsl_release_resources(struct mgsl_struct *info)
4149{
4150 if ( debug_level >= DEBUG_LEVEL_INFO )
4151 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4152 __FILE__,__LINE__,info->device_name );
4153
4154 if ( info->irq_requested ) {
4155 free_irq(info->irq_level, info);
4156 info->irq_requested = false;
4157 }
4158 if ( info->dma_requested ) {
4159 disable_dma(info->dma_level);
4160 free_dma(info->dma_level);
4161 info->dma_requested = false;
4162 }
4163 mgsl_free_dma_buffers(info);
4164 mgsl_free_intermediate_rxbuffer_memory(info);
4165 mgsl_free_intermediate_txbuffer_memory(info);
4166
4167 if ( info->io_addr_requested ) {
4168 release_region(info->io_base,info->io_addr_size);
4169 info->io_addr_requested = false;
4170 }
4171 if ( info->shared_mem_requested ) {
4172 release_mem_region(info->phys_memory_base,0x40000);
4173 info->shared_mem_requested = false;
4174 }
4175 if ( info->lcr_mem_requested ) {
4176 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
4177 info->lcr_mem_requested = false;
4178 }
4179 if (info->memory_base){
4180 iounmap(info->memory_base);
4181 info->memory_base = NULL;
4182 }
4183 if (info->lcr_base){
4184 iounmap(info->lcr_base - info->lcr_offset);
4185 info->lcr_base = NULL;
4186 }
4187
4188 if ( debug_level >= DEBUG_LEVEL_INFO )
4189 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4190 __FILE__,__LINE__,info->device_name );
4191
4192}
4193
4194
4195
4196
4197
4198
4199
4200
4201
4202static void mgsl_add_device( struct mgsl_struct *info )
4203{
4204 info->next_device = NULL;
4205 info->line = mgsl_device_count;
4206 sprintf(info->device_name,"ttySL%d",info->line);
4207
4208 if (info->line < MAX_TOTAL_DEVICES) {
4209 if (maxframe[info->line])
4210 info->max_frame_size = maxframe[info->line];
4211
4212 if (txdmabufs[info->line]) {
4213 info->num_tx_dma_buffers = txdmabufs[info->line];
4214 if (info->num_tx_dma_buffers < 1)
4215 info->num_tx_dma_buffers = 1;
4216 }
4217
4218 if (txholdbufs[info->line]) {
4219 info->num_tx_holding_buffers = txholdbufs[info->line];
4220 if (info->num_tx_holding_buffers < 1)
4221 info->num_tx_holding_buffers = 1;
4222 else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
4223 info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
4224 }
4225 }
4226
4227 mgsl_device_count++;
4228
4229 if ( !mgsl_device_list )
4230 mgsl_device_list = info;
4231 else {
4232 struct mgsl_struct *current_dev = mgsl_device_list;
4233 while( current_dev->next_device )
4234 current_dev = current_dev->next_device;
4235 current_dev->next_device = info;
4236 }
4237
4238 if ( info->max_frame_size < 4096 )
4239 info->max_frame_size = 4096;
4240 else if ( info->max_frame_size > 65535 )
4241 info->max_frame_size = 65535;
4242
4243 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4244 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4245 info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4246 info->phys_memory_base, info->phys_lcr_base,
4247 info->max_frame_size );
4248 } else {
4249 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4250 info->device_name, info->io_base, info->irq_level, info->dma_level,
4251 info->max_frame_size );
4252 }
4253
4254#if SYNCLINK_GENERIC_HDLC
4255 hdlcdev_init(info);
4256#endif
4257
4258}
4259
4260static const struct tty_port_operations mgsl_port_ops = {
4261 .carrier_raised = carrier_raised,
4262 .dtr_rts = dtr_rts,
4263};
4264
4265
4266
4267
4268
4269
4270
4271
4272
4273static struct mgsl_struct* mgsl_allocate_device(void)
4274{
4275 struct mgsl_struct *info;
4276
4277 info = kzalloc(sizeof(struct mgsl_struct),
4278 GFP_KERNEL);
4279
4280 if (!info) {
4281 printk("Error can't allocate device instance data\n");
4282 } else {
4283 tty_port_init(&info->port);
4284 info->port.ops = &mgsl_port_ops;
4285 info->magic = MGSL_MAGIC;
4286 INIT_WORK(&info->task, mgsl_bh_handler);
4287 info->max_frame_size = 4096;
4288 info->port.close_delay = 5*HZ/10;
4289 info->port.closing_wait = 30*HZ;
4290 init_waitqueue_head(&info->status_event_wait_q);
4291 init_waitqueue_head(&info->event_wait_q);
4292 spin_lock_init(&info->irq_spinlock);
4293 spin_lock_init(&info->netlock);
4294 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
4295 info->idle_mode = HDLC_TXIDLE_FLAGS;
4296 info->num_tx_dma_buffers = 1;
4297 info->num_tx_holding_buffers = 0;
4298 }
4299
4300 return info;
4301
4302}
4303
4304static const struct tty_operations mgsl_ops = {
4305 .open = mgsl_open,
4306 .close = mgsl_close,
4307 .write = mgsl_write,
4308 .put_char = mgsl_put_char,
4309 .flush_chars = mgsl_flush_chars,
4310 .write_room = mgsl_write_room,
4311 .chars_in_buffer = mgsl_chars_in_buffer,
4312 .flush_buffer = mgsl_flush_buffer,
4313 .ioctl = mgsl_ioctl,
4314 .throttle = mgsl_throttle,
4315 .unthrottle = mgsl_unthrottle,
4316 .send_xchar = mgsl_send_xchar,
4317 .break_ctl = mgsl_break,
4318 .wait_until_sent = mgsl_wait_until_sent,
4319 .set_termios = mgsl_set_termios,
4320 .stop = mgsl_stop,
4321 .start = mgsl_start,
4322 .hangup = mgsl_hangup,
4323 .tiocmget = tiocmget,
4324 .tiocmset = tiocmset,
4325 .get_icount = msgl_get_icount,
4326 .proc_fops = &mgsl_proc_fops,
4327};
4328
4329
4330
4331
4332static int mgsl_init_tty(void)
4333{
4334 int rc;
4335
4336 serial_driver = alloc_tty_driver(128);
4337 if (!serial_driver)
4338 return -ENOMEM;
4339
4340 serial_driver->owner = THIS_MODULE;
4341 serial_driver->driver_name = "synclink";
4342 serial_driver->name = "ttySL";
4343 serial_driver->major = ttymajor;
4344 serial_driver->minor_start = 64;
4345 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4346 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4347 serial_driver->init_termios = tty_std_termios;
4348 serial_driver->init_termios.c_cflag =
4349 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4350 serial_driver->init_termios.c_ispeed = 9600;
4351 serial_driver->init_termios.c_ospeed = 9600;
4352 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4353 tty_set_operations(serial_driver, &mgsl_ops);
4354 if ((rc = tty_register_driver(serial_driver)) < 0) {
4355 printk("%s(%d):Couldn't register serial driver\n",
4356 __FILE__,__LINE__);
4357 put_tty_driver(serial_driver);
4358 serial_driver = NULL;
4359 return rc;
4360 }
4361
4362 printk("%s %s, tty major#%d\n",
4363 driver_name, driver_version,
4364 serial_driver->major);
4365 return 0;
4366}
4367
4368
4369
4370static void mgsl_enum_isa_devices(void)
4371{
4372 struct mgsl_struct *info;
4373 int i;
4374
4375
4376
4377 for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4378 if ( debug_level >= DEBUG_LEVEL_INFO )
4379 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4380 io[i], irq[i], dma[i] );
4381
4382 info = mgsl_allocate_device();
4383 if ( !info ) {
4384
4385 if ( debug_level >= DEBUG_LEVEL_ERROR )
4386 printk( "can't allocate device instance data.\n");
4387 continue;
4388 }
4389
4390
4391 info->io_base = (unsigned int)io[i];
4392 info->irq_level = (unsigned int)irq[i];
4393 info->irq_level = irq_canonicalize(info->irq_level);
4394 info->dma_level = (unsigned int)dma[i];
4395 info->bus_type = MGSL_BUS_TYPE_ISA;
4396 info->io_addr_size = 16;
4397 info->irq_flags = 0;
4398
4399 mgsl_add_device( info );
4400 }
4401}
4402
4403static void synclink_cleanup(void)
4404{
4405 int rc;
4406 struct mgsl_struct *info;
4407 struct mgsl_struct *tmp;
4408
4409 printk("Unloading %s: %s\n", driver_name, driver_version);
4410
4411 if (serial_driver) {
4412 if ((rc = tty_unregister_driver(serial_driver)))
4413 printk("%s(%d) failed to unregister tty driver err=%d\n",
4414 __FILE__,__LINE__,rc);
4415 put_tty_driver(serial_driver);
4416 }
4417
4418 info = mgsl_device_list;
4419 while(info) {
4420#if SYNCLINK_GENERIC_HDLC
4421 hdlcdev_exit(info);
4422#endif
4423 mgsl_release_resources(info);
4424 tmp = info;
4425 info = info->next_device;
4426 kfree(tmp);
4427 }
4428
4429 if (pci_registered)
4430 pci_unregister_driver(&synclink_pci_driver);
4431}
4432
4433static int __init synclink_init(void)
4434{
4435 int rc;
4436
4437 if (break_on_load) {
4438 mgsl_get_text_ptr();
4439 BREAKPOINT();
4440 }
4441
4442 printk("%s %s\n", driver_name, driver_version);
4443
4444 mgsl_enum_isa_devices();
4445 if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
4446 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4447 else
4448 pci_registered = true;
4449
4450 if ((rc = mgsl_init_tty()) < 0)
4451 goto error;
4452
4453 return 0;
4454
4455error:
4456 synclink_cleanup();
4457 return rc;
4458}
4459
4460static void __exit synclink_exit(void)
4461{
4462 synclink_cleanup();
4463}
4464
4465module_init(synclink_init);
4466module_exit(synclink_exit);
4467
4468
4469
4470
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4490{
4491
4492
4493
4494 outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4495
4496
4497 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4498 inw( info->io_base + CCAR );
4499
4500}
4501
4502
4503
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514
4515
4516static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4517{
4518
4519 outw( Cmd + info->mbre_bit, info->io_base );
4520
4521
4522 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4523 inw( info->io_base );
4524
4525}
4526
4527
4528
4529
4530
4531
4532
4533
4534
4535
4536
4537
4538
4539
4540
4541
4542
4543static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4544{
4545
4546
4547
4548 outw( RegAddr + info->mbre_bit, info->io_base );
4549 outw( RegValue, info->io_base );
4550
4551
4552 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4553 inw( info->io_base );
4554
4555}
4556
4557
4558
4559
4560
4561
4562
4563
4564
4565
4566
4567
4568
4569
4570
4571
4572static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4573{
4574
4575
4576
4577 outw( RegAddr + info->mbre_bit, info->io_base );
4578 return inw( info->io_base );
4579
4580}
4581
4582
4583
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593
4594
4595
4596
4597
4598
4599static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4600{
4601 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4602 outw( RegValue, info->io_base + CCAR );
4603
4604
4605 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4606 inw( info->io_base + CCAR );
4607
4608}
4609
4610
4611
4612
4613
4614
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4625{
4626 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4627 return inw( info->io_base + CCAR );
4628
4629}
4630
4631
4632
4633
4634
4635
4636
4637
4638static void usc_set_sdlc_mode( struct mgsl_struct *info )
4639{
4640 u16 RegValue;
4641 bool PreSL1660;
4642
4643
4644
4645
4646
4647
4648
4649
4650
4651
4652 usc_OutReg(info,TMCR,0x1f);
4653 RegValue=usc_InReg(info,TMDR);
4654 PreSL1660 = (RegValue == IUSC_PRE_SL1660);
4655
4656 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4657 {
4658
4659
4660
4661
4662
4663
4664
4665
4666
4667
4668
4669
4670 RegValue = 0x8e06;
4671
4672
4673
4674
4675
4676 }
4677 else
4678 {
4679
4680
4681
4682
4683
4684
4685
4686
4687
4688
4689
4690 if (info->params.mode == MGSL_MODE_RAW) {
4691 RegValue = 0x0001;
4692
4693 usc_OutReg( info, IOCR,
4694 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4695
4696
4697
4698
4699
4700
4701
4702
4703
4704
4705
4706
4707
4708 RegValue |= 0x0400;
4709 }
4710 else {
4711
4712 RegValue = 0x0606;
4713
4714 if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4715 RegValue |= BIT14;
4716 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4717 RegValue |= BIT15;
4718 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
4719 RegValue |= BIT15 + BIT14;
4720 }
4721
4722 if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4723 RegValue |= BIT13;
4724 }
4725
4726 if ( info->params.mode == MGSL_MODE_HDLC &&
4727 (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
4728 RegValue |= BIT12;
4729
4730 if ( info->params.addr_filter != 0xff )
4731 {
4732
4733 usc_OutReg( info, RSR, info->params.addr_filter );
4734 RegValue |= BIT4;
4735 }
4736
4737 usc_OutReg( info, CMR, RegValue );
4738 info->cmr_value = RegValue;
4739
4740
4741
4742
4743
4744
4745
4746
4747
4748
4749
4750
4751
4752
4753
4754
4755 RegValue = 0x0500;
4756
4757 switch ( info->params.encoding ) {
4758 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4759 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4760 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4761 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4762 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4763 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4764 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4765 }
4766
4767 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4768 RegValue |= BIT9;
4769 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4770 RegValue |= ( BIT12 | BIT10 | BIT9 );
4771
4772 usc_OutReg( info, RMR, RegValue );
4773
4774
4775
4776
4777
4778
4779
4780
4781 usc_OutReg( info, RCLR, RCLRVALUE );
4782
4783 usc_RCmd( info, RCmd_SelectRicrdma_level );
4784
4785
4786
4787
4788
4789
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800
4801
4802
4803 RegValue = usc_InReg( info, RICR ) & 0xc0;
4804
4805 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4806 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4807 else
4808 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4809
4810
4811
4812 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4813 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4814
4815
4816
4817
4818
4819
4820
4821
4822
4823
4824
4825
4826
4827
4828
4829
4830 RegValue = 0x0400;
4831
4832 switch ( info->params.encoding ) {
4833 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4834 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4835 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4836 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4837 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4838 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4839 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4840 }
4841
4842 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4843 RegValue |= BIT9 + BIT8;
4844 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4845 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4846
4847 usc_OutReg( info, TMR, RegValue );
4848
4849 usc_set_txidle( info );
4850
4851
4852 usc_TCmd( info, TCmd_SelectTicrdma_level );
4853
4854
4855
4856
4857
4858
4859
4860
4861
4862
4863
4864
4865
4866
4867
4868
4869 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4870 usc_OutReg( info, TICR, 0x0736 );
4871 else
4872 usc_OutReg( info, TICR, 0x1436 );
4873
4874 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
4875 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
4876
4877
4878
4879
4880
4881
4882
4883
4884
4885
4886
4887
4888
4889
4890
4891
4892
4893
4894 info->tcsr_value = 0;
4895
4896 if ( !PreSL1660 )
4897 info->tcsr_value |= TCSR_UNDERWAIT;
4898
4899 usc_OutReg( info, TCSR, info->tcsr_value );
4900
4901
4902
4903
4904
4905
4906
4907
4908
4909
4910
4911
4912
4913
4914 RegValue = 0x0f40;
4915
4916 if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
4917 RegValue |= 0x0003;
4918 else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
4919 RegValue |= 0x0004;
4920 else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4921 RegValue |= 0x0006;
4922 else
4923 RegValue |= 0x0007;
4924
4925 if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
4926 RegValue |= 0x0018;
4927 else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
4928 RegValue |= 0x0020;
4929 else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4930 RegValue |= 0x0038;
4931 else
4932 RegValue |= 0x0030;
4933
4934 usc_OutReg( info, CMCR, RegValue );
4935
4936
4937
4938
4939
4940
4941
4942
4943
4944
4945
4946
4947
4948
4949
4950
4951
4952 RegValue = 0x0000;
4953
4954 if ( info->params.flags & (HDLC_FLAG_RXC_DPLL + HDLC_FLAG_TXC_DPLL) ) {
4955 u32 XtalSpeed;
4956 u32 DpllDivisor;
4957 u16 Tc;
4958
4959
4960
4961
4962 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4963 XtalSpeed = 11059200;
4964 else
4965 XtalSpeed = 14745600;
4966
4967 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4968 DpllDivisor = 16;
4969 RegValue |= BIT10;
4970 }
4971 else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4972 DpllDivisor = 8;
4973 RegValue |= BIT11;
4974 }
4975 else
4976 DpllDivisor = 32;
4977
4978
4979
4980
4981
4982
4983
4984
4985
4986
4987
4988
4989
4990
4991
4992 if ( info->params.clock_speed )
4993 {
4994 Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
4995 if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
4996 / info->params.clock_speed) )
4997 Tc--;
4998 }
4999 else
5000 Tc = -1;
5001
5002
5003
5004 usc_OutReg( info, TC1R, Tc );
5005
5006 RegValue |= BIT4;
5007
5008 switch ( info->params.encoding ) {
5009 case HDLC_ENCODING_NRZ:
5010 case HDLC_ENCODING_NRZB:
5011 case HDLC_ENCODING_NRZI_MARK:
5012 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
5013 case HDLC_ENCODING_BIPHASE_MARK:
5014 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
5015 case HDLC_ENCODING_BIPHASE_LEVEL:
5016 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
5017 }
5018 }
5019
5020 usc_OutReg( info, HCR, RegValue );
5021
5022
5023
5024
5025
5026
5027
5028
5029
5030
5031
5032
5033
5034
5035
5036
5037
5038
5039
5040
5041 usc_OutReg( info, CCSR, 0x1020 );
5042
5043
5044 if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5045 usc_OutReg( info, SICR,
5046 (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5047 }
5048
5049
5050
5051 usc_EnableMasterIrqBit( info );
5052
5053 usc_ClearIrqPendingBits( info, RECEIVE_STATUS + RECEIVE_DATA +
5054 TRANSMIT_STATUS + TRANSMIT_DATA + MISC);
5055
5056
5057 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
5058 usc_EnableInterrupts(info, MISC);
5059
5060 info->mbre_bit = 0;
5061 outw( 0, info->io_base );
5062 usc_DmaCmd( info, DmaCmd_ResetAllChannels );
5063 info->mbre_bit = BIT8;
5064 outw( BIT8, info->io_base );
5065
5066 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5067
5068
5069 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5070 }
5071
5072
5073
5074
5075
5076
5077
5078
5079
5080
5081
5082
5083
5084
5085
5086
5087
5088
5089
5090
5091
5092
5093
5094 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5095
5096 usc_OutDmaReg( info, DCR, 0xa00b );
5097 }
5098 else
5099 usc_OutDmaReg( info, DCR, 0x800b );
5100
5101
5102
5103
5104
5105
5106
5107
5108
5109
5110
5111
5112
5113
5114
5115 usc_OutDmaReg( info, RDMR, 0xf200 );
5116
5117
5118
5119
5120
5121
5122
5123
5124
5125
5126
5127
5128
5129
5130
5131 usc_OutDmaReg( info, TDMR, 0xf200 );
5132
5133
5134
5135
5136
5137
5138
5139
5140
5141
5142
5143
5144
5145
5146
5147 usc_OutDmaReg( info, DICR, 0x9000 );
5148
5149 usc_InDmaReg( info, RDMR );
5150 usc_InDmaReg( info, TDMR );
5151 usc_OutDmaReg( info, CDIR, 0x0303 );
5152
5153
5154
5155
5156
5157
5158
5159
5160
5161
5162
5163
5164
5165
5166
5167 RegValue = 0x8080;
5168
5169 switch ( info->params.preamble_length ) {
5170 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5171 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
5172 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break;
5173 }
5174
5175 switch ( info->params.preamble ) {
5176 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
5177 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5178 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
5179 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break;
5180 }
5181
5182 usc_OutReg( info, CCR, RegValue );
5183
5184
5185
5186
5187
5188
5189
5190
5191
5192 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5193
5194 usc_OutDmaReg( info, BDCR, 0x0000 );
5195 }
5196 else
5197 usc_OutDmaReg( info, BDCR, 0x2000 );
5198
5199 usc_stop_transmitter(info);
5200 usc_stop_receiver(info);
5201
5202}
5203
5204
5205
5206
5207
5208
5209
5210
5211
5212
5213
5214static void usc_enable_loopback(struct mgsl_struct *info, int enable)
5215{
5216 if (enable) {
5217
5218 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6));
5219
5220
5221
5222
5223
5224
5225
5226
5227
5228
5229
5230
5231
5232
5233 usc_OutReg( info, CMCR, 0x0f64 );
5234
5235
5236
5237 if (info->params.clock_speed) {
5238 if (info->bus_type == MGSL_BUS_TYPE_PCI)
5239 usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5240 else
5241 usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5242 } else
5243 usc_OutReg(info, TC0R, (u16)8);
5244
5245
5246
5247 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5248
5249
5250 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5251
5252
5253 info->loopback_bits = 0x300;
5254 outw( 0x0300, info->io_base + CCAR );
5255 } else {
5256
5257 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6));
5258
5259
5260 info->loopback_bits = 0;
5261 outw( 0,info->io_base + CCAR );
5262 }
5263
5264}
5265
5266
5267
5268
5269
5270
5271
5272
5273
5274
5275
5276
5277
5278static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
5279{
5280 u32 XtalSpeed;
5281 u16 Tc;
5282
5283 if ( data_rate ) {
5284 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5285 XtalSpeed = 11059200;
5286 else
5287 XtalSpeed = 14745600;
5288
5289
5290
5291
5292
5293
5294
5295
5296
5297 Tc = (u16)(XtalSpeed/data_rate);
5298 if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
5299 Tc--;
5300
5301
5302 usc_OutReg( info, TC0R, Tc );
5303
5304
5305
5306
5307
5308
5309
5310 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5311
5312
5313 usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
5314 } else {
5315
5316 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5317 }
5318
5319}
5320
5321
5322
5323
5324
5325
5326
5327
5328
5329
5330
5331
5332
5333
5334
5335static void usc_process_rxoverrun_sync( struct mgsl_struct *info )
5336{
5337 int start_index;
5338 int end_index;
5339 int frame_start_index;
5340 bool start_of_frame_found = false;
5341 bool end_of_frame_found = false;
5342 bool reprogram_dma = false;
5343
5344 DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
5345 u32 phys_addr;
5346
5347 usc_DmaCmd( info, DmaCmd_PauseRxChannel );
5348 usc_RCmd( info, RCmd_EnterHuntmode );
5349 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5350
5351
5352
5353
5354 frame_start_index = start_index = end_index = info->current_rx_buffer;
5355
5356
5357
5358
5359
5360
5361 while( !buffer_list[end_index].count )
5362 {
5363
5364
5365
5366 if ( !start_of_frame_found )
5367 {
5368 start_of_frame_found = true;
5369 frame_start_index = end_index;
5370 end_of_frame_found = false;
5371 }
5372
5373 if ( buffer_list[end_index].status )
5374 {
5375
5376
5377
5378
5379
5380
5381 start_of_frame_found = false;
5382 end_of_frame_found = true;
5383 }
5384
5385
5386 end_index++;
5387 if ( end_index == info->rx_buffer_count )
5388 end_index = 0;
5389
5390 if ( start_index == end_index )
5391 {
5392
5393
5394
5395 mgsl_reset_rx_dma_buffers( info );
5396 frame_start_index = 0;
5397 start_of_frame_found = false;
5398 reprogram_dma = true;
5399 break;
5400 }
5401 }
5402
5403 if ( start_of_frame_found && !end_of_frame_found )
5404 {
5405
5406
5407
5408
5409
5410
5411
5412 start_index = frame_start_index;
5413
5414 do
5415 {
5416 *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
5417
5418
5419 if ( start_index == info->rx_buffer_count )
5420 start_index = 0;
5421
5422 } while( start_index != end_index );
5423
5424 reprogram_dma = true;
5425 }
5426
5427 if ( reprogram_dma )
5428 {
5429 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
5430 usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5431 usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5432
5433 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5434
5435
5436 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5437
5438
5439 phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
5440 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5441 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5442
5443 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5444 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5445 usc_EnableInterrupts( info, RECEIVE_STATUS );
5446
5447
5448
5449
5450 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5451 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5452 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5453 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5454 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5455 else
5456 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5457 }
5458 else
5459 {
5460
5461 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5462 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5463 }
5464
5465}
5466
5467
5468
5469
5470
5471
5472
5473
5474static void usc_stop_receiver( struct mgsl_struct *info )
5475{
5476 if (debug_level >= DEBUG_LEVEL_ISR)
5477 printk("%s(%d):usc_stop_receiver(%s)\n",
5478 __FILE__,__LINE__, info->device_name );
5479
5480
5481
5482 usc_DmaCmd( info, DmaCmd_ResetRxChannel );
5483
5484 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5485 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5486 usc_DisableInterrupts( info, RECEIVE_DATA + RECEIVE_STATUS );
5487
5488 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5489
5490
5491 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5492 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5493
5494 info->rx_enabled = false;
5495 info->rx_overflow = false;
5496 info->rx_rcc_underrun = false;
5497
5498}
5499
5500
5501
5502
5503
5504
5505
5506
5507static void usc_start_receiver( struct mgsl_struct *info )
5508{
5509 u32 phys_addr;
5510
5511 if (debug_level >= DEBUG_LEVEL_ISR)
5512 printk("%s(%d):usc_start_receiver(%s)\n",
5513 __FILE__,__LINE__, info->device_name );
5514
5515 mgsl_reset_rx_dma_buffers( info );
5516 usc_stop_receiver( info );
5517
5518 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5519 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5520
5521 if ( info->params.mode == MGSL_MODE_HDLC ||
5522 info->params.mode == MGSL_MODE_RAW ) {
5523
5524
5525
5526
5527
5528 phys_addr = info->rx_buffer_list[0].phys_entry;
5529 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5530 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5531
5532 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5533 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5534 usc_EnableInterrupts( info, RECEIVE_STATUS );
5535
5536
5537
5538
5539 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5540 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5541 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5542 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5543 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5544 else
5545 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5546 } else {
5547 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
5548 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
5549 usc_EnableInterrupts(info, RECEIVE_DATA);
5550
5551 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5552 usc_RCmd( info, RCmd_EnterHuntmode );
5553
5554 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5555 }
5556
5557 usc_OutReg( info, CCSR, 0x1020 );
5558
5559 info->rx_enabled = true;
5560
5561}
5562
5563
5564
5565
5566
5567
5568
5569
5570
5571static void usc_start_transmitter( struct mgsl_struct *info )
5572{
5573 u32 phys_addr;
5574 unsigned int FrameSize;
5575
5576 if (debug_level >= DEBUG_LEVEL_ISR)
5577 printk("%s(%d):usc_start_transmitter(%s)\n",
5578 __FILE__,__LINE__, info->device_name );
5579
5580 if ( info->xmit_cnt ) {
5581
5582
5583
5584
5585
5586 info->drop_rts_on_tx_done = false;
5587
5588 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
5589 usc_get_serial_signals( info );
5590 if ( !(info->serial_signals & SerialSignal_RTS) ) {
5591 info->serial_signals |= SerialSignal_RTS;
5592 usc_set_serial_signals( info );
5593 info->drop_rts_on_tx_done = true;
5594 }
5595 }
5596
5597
5598 if ( info->params.mode == MGSL_MODE_ASYNC ) {
5599 if ( !info->tx_active ) {
5600 usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
5601 usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
5602 usc_EnableInterrupts(info, TRANSMIT_DATA);
5603 usc_load_txfifo(info);
5604 }
5605 } else {
5606
5607 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5608
5609
5610
5611
5612 FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
5613
5614
5615
5616
5617
5618 if ( info->params.mode == MGSL_MODE_RAW )
5619 info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
5620
5621
5622
5623 usc_OutReg( info, TCLR, (u16)FrameSize );
5624
5625 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5626
5627
5628 phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
5629 usc_OutDmaReg( info, NTARL, (u16)phys_addr );
5630 usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
5631
5632 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5633 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5634 usc_EnableInterrupts( info, TRANSMIT_STATUS );
5635
5636 if ( info->params.mode == MGSL_MODE_RAW &&
5637 info->num_tx_dma_buffers > 1 ) {
5638
5639
5640
5641
5642
5643
5644
5645 usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
5646 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
5647 }
5648
5649
5650 usc_DmaCmd( info, DmaCmd_InitTxChannel );
5651
5652 usc_TCmd( info, TCmd_SendFrame );
5653
5654 mod_timer(&info->tx_timer, jiffies +
5655 msecs_to_jiffies(5000));
5656 }
5657 info->tx_active = true;
5658 }
5659
5660 if ( !info->tx_enabled ) {
5661 info->tx_enabled = true;
5662 if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
5663 usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
5664 else
5665 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
5666 }
5667
5668}
5669
5670
5671
5672
5673
5674
5675
5676
5677static void usc_stop_transmitter( struct mgsl_struct *info )
5678{
5679 if (debug_level >= DEBUG_LEVEL_ISR)
5680 printk("%s(%d):usc_stop_transmitter(%s)\n",
5681 __FILE__,__LINE__, info->device_name );
5682
5683 del_timer(&info->tx_timer);
5684
5685 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5686 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5687 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5688
5689 usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
5690 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5691 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5692
5693 info->tx_enabled = false;
5694 info->tx_active = false;
5695
5696}
5697
5698
5699
5700
5701
5702
5703
5704
5705
5706static void usc_load_txfifo( struct mgsl_struct *info )
5707{
5708 int Fifocount;
5709 u8 TwoBytes[2];
5710
5711 if ( !info->xmit_cnt && !info->x_char )
5712 return;
5713
5714
5715 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
5716
5717
5718
5719 while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
5720
5721
5722
5723 if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
5724
5725
5726 TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
5727 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5728 TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
5729 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5730
5731 outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5732
5733 info->xmit_cnt -= 2;
5734 info->icount.tx += 2;
5735 } else {
5736
5737
5738 outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5739 info->io_base + CCAR );
5740
5741 if (info->x_char) {
5742
5743 outw( info->x_char,info->io_base + CCAR );
5744 info->x_char = 0;
5745 } else {
5746 outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5747 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5748 info->xmit_cnt--;
5749 }
5750 info->icount.tx++;
5751 }
5752 }
5753
5754}
5755
5756
5757
5758
5759
5760
5761
5762
5763static void usc_reset( struct mgsl_struct *info )
5764{
5765 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5766 int i;
5767 u32 readval;
5768
5769
5770
5771
5772 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5773 u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5774
5775 info->misc_ctrl_value |= BIT30;
5776 *MiscCtrl = info->misc_ctrl_value;
5777
5778
5779
5780
5781
5782
5783 for(i=0;i<10;i++)
5784 readval = *MiscCtrl;
5785
5786 info->misc_ctrl_value &= ~BIT30;
5787 *MiscCtrl = info->misc_ctrl_value;
5788
5789 *LCR0BRDR = BUS_DESCRIPTOR(
5790 1,
5791 2,
5792 2,
5793 0,
5794 4,
5795 0,
5796 0,
5797 5
5798 );
5799 } else {
5800
5801 outb( 0,info->io_base + 8 );
5802 }
5803
5804 info->mbre_bit = 0;
5805 info->loopback_bits = 0;
5806 info->usc_idle_mode = 0;
5807
5808
5809
5810
5811
5812
5813
5814
5815
5816
5817
5818
5819
5820
5821
5822
5823
5824
5825 outw( 0x000c,info->io_base + SDPIN );
5826
5827
5828 outw( 0,info->io_base );
5829 outw( 0,info->io_base + CCAR );
5830
5831
5832 usc_RTCmd( info, RTCmd_SelectLittleEndian );
5833
5834
5835
5836
5837
5838
5839
5840
5841
5842
5843
5844
5845
5846
5847
5848
5849 usc_OutReg( info, PCR, 0xf0f5 );
5850
5851
5852
5853
5854
5855
5856
5857
5858
5859
5860
5861
5862
5863
5864
5865
5866 usc_OutReg( info, IOCR, 0x0004 );
5867
5868}
5869
5870
5871
5872
5873
5874
5875
5876
5877static void usc_set_async_mode( struct mgsl_struct *info )
5878{
5879 u16 RegValue;
5880
5881
5882 usc_DisableMasterIrqBit( info );
5883
5884 outw( 0, info->io_base );
5885 usc_DmaCmd( info, DmaCmd_ResetAllChannels );
5886
5887 usc_loopback_frame( info );
5888
5889
5890
5891
5892
5893
5894
5895
5896
5897
5898
5899
5900
5901 RegValue = 0;
5902 if ( info->params.stop_bits != 1 )
5903 RegValue |= BIT14;
5904 usc_OutReg( info, CMR, RegValue );
5905
5906
5907
5908
5909
5910
5911
5912
5913
5914
5915
5916
5917
5918
5919 RegValue = 0;
5920
5921 if ( info->params.data_bits != 8 )
5922 RegValue |= BIT4+BIT3+BIT2;
5923
5924 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5925 RegValue |= BIT5;
5926 if ( info->params.parity != ASYNC_PARITY_ODD )
5927 RegValue |= BIT6;
5928 }
5929
5930 usc_OutReg( info, RMR, RegValue );
5931
5932
5933
5934
5935 usc_RCmd( info, RCmd_SelectRicrIntLevel );
5936
5937
5938
5939
5940
5941
5942
5943
5944
5945
5946
5947
5948
5949
5950
5951
5952
5953
5954
5955
5956
5957
5958 usc_OutReg( info, RICR, 0x0000 );
5959
5960 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5961 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
5962
5963
5964
5965
5966
5967
5968
5969
5970
5971
5972
5973
5974
5975
5976 RegValue = 0;
5977
5978 if ( info->params.data_bits != 8 )
5979 RegValue |= BIT4+BIT3+BIT2;
5980
5981 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5982 RegValue |= BIT5;
5983 if ( info->params.parity != ASYNC_PARITY_ODD )
5984 RegValue |= BIT6;
5985 }
5986
5987 usc_OutReg( info, TMR, RegValue );
5988
5989 usc_set_txidle( info );
5990
5991
5992
5993
5994 usc_TCmd( info, TCmd_SelectTicrIntLevel );
5995
5996
5997
5998
5999
6000
6001
6002
6003
6004
6005
6006
6007
6008
6009
6010
6011
6012 usc_OutReg( info, TICR, 0x1f40 );
6013
6014 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
6015 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
6016
6017 usc_enable_async_clock( info, info->params.data_rate );
6018
6019
6020
6021
6022
6023
6024
6025
6026
6027
6028
6029
6030
6031
6032
6033
6034
6035
6036
6037
6038 usc_OutReg( info, CCSR, 0x0020 );
6039
6040 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6041 RECEIVE_DATA + RECEIVE_STATUS );
6042
6043 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6044 RECEIVE_DATA + RECEIVE_STATUS );
6045
6046 usc_EnableMasterIrqBit( info );
6047
6048 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6049
6050
6051 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6052 }
6053
6054 if (info->params.loopback) {
6055 info->loopback_bits = 0x300;
6056 outw(0x0300, info->io_base + CCAR);
6057 }
6058
6059}
6060
6061
6062
6063
6064
6065
6066
6067
6068
6069
6070
6071
6072
6073
6074
6075static void usc_loopback_frame( struct mgsl_struct *info )
6076{
6077 int i;
6078 unsigned long oldmode = info->params.mode;
6079
6080 info->params.mode = MGSL_MODE_HDLC;
6081
6082 usc_DisableMasterIrqBit( info );
6083
6084 usc_set_sdlc_mode( info );
6085 usc_enable_loopback( info, 1 );
6086
6087
6088 usc_OutReg( info, TC0R, 0 );
6089
6090
6091
6092
6093
6094
6095
6096
6097
6098
6099
6100
6101
6102
6103
6104 usc_OutReg( info, CCR, 0x0100 );
6105
6106
6107 usc_RTCmd( info, RTCmd_PurgeRxFifo );
6108 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
6109
6110
6111
6112
6113 usc_OutReg( info, TCLR, 2 );
6114 usc_RTCmd( info, RTCmd_PurgeTxFifo );
6115
6116
6117 usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
6118 outw(0,info->io_base + DATAREG);
6119
6120
6121 usc_TCmd( info, TCmd_SendFrame );
6122 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
6123
6124
6125 for (i=0 ; i<1000 ; i++)
6126 if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
6127 break;
6128
6129
6130 usc_enable_loopback(info, 0);
6131
6132 usc_EnableMasterIrqBit(info);
6133
6134 info->params.mode = oldmode;
6135
6136}
6137
6138
6139
6140
6141
6142
6143static void usc_set_sync_mode( struct mgsl_struct *info )
6144{
6145 usc_loopback_frame( info );
6146 usc_set_sdlc_mode( info );
6147
6148 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6149
6150
6151 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6152 }
6153
6154 usc_enable_aux_clock(info, info->params.clock_speed);
6155
6156 if (info->params.loopback)
6157 usc_enable_loopback(info,1);
6158
6159}
6160
6161
6162
6163
6164
6165
6166static void usc_set_txidle( struct mgsl_struct *info )
6167{
6168 u16 usc_idle_mode = IDLEMODE_FLAGS;
6169
6170
6171
6172 switch( info->idle_mode ){
6173 case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
6174 case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
6175 case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
6176 case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
6177 case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
6178 case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
6179 case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
6180 }
6181
6182 info->usc_idle_mode = usc_idle_mode;
6183
6184 info->tcsr_value &= ~IDLEMODE_MASK;
6185 info->tcsr_value += usc_idle_mode;
6186 usc_OutReg(info, TCSR, info->tcsr_value);
6187
6188
6189
6190
6191
6192
6193
6194
6195 if ( info->params.mode == MGSL_MODE_RAW ) {
6196 unsigned char syncpat = 0;
6197 switch( info->idle_mode ) {
6198 case HDLC_TXIDLE_FLAGS:
6199 syncpat = 0x7e;
6200 break;
6201 case HDLC_TXIDLE_ALT_ZEROS_ONES:
6202 syncpat = 0x55;
6203 break;
6204 case HDLC_TXIDLE_ZEROS:
6205 case HDLC_TXIDLE_SPACE:
6206 syncpat = 0x00;
6207 break;
6208 case HDLC_TXIDLE_ONES:
6209 case HDLC_TXIDLE_MARK:
6210 syncpat = 0xff;
6211 break;
6212 case HDLC_TXIDLE_ALT_MARK_SPACE:
6213 syncpat = 0xaa;
6214 break;
6215 }
6216
6217 usc_SetTransmitSyncChars(info,syncpat,syncpat);
6218 }
6219
6220}
6221
6222
6223
6224
6225
6226
6227
6228
6229static void usc_get_serial_signals( struct mgsl_struct *info )
6230{
6231 u16 status;
6232
6233
6234 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
6235
6236
6237
6238
6239 status = usc_InReg( info, MISR );
6240
6241
6242
6243 if ( status & MISCSTATUS_CTS )
6244 info->serial_signals |= SerialSignal_CTS;
6245
6246 if ( status & MISCSTATUS_DCD )
6247 info->serial_signals |= SerialSignal_DCD;
6248
6249 if ( status & MISCSTATUS_RI )
6250 info->serial_signals |= SerialSignal_RI;
6251
6252 if ( status & MISCSTATUS_DSR )
6253 info->serial_signals |= SerialSignal_DSR;
6254
6255}
6256
6257
6258
6259
6260
6261
6262
6263
6264
6265static void usc_set_serial_signals( struct mgsl_struct *info )
6266{
6267 u16 Control;
6268 unsigned char V24Out = info->serial_signals;
6269
6270
6271
6272 Control = usc_InReg( info, PCR );
6273
6274 if ( V24Out & SerialSignal_RTS )
6275 Control &= ~(BIT6);
6276 else
6277 Control |= BIT6;
6278
6279 if ( V24Out & SerialSignal_DTR )
6280 Control &= ~(BIT4);
6281 else
6282 Control |= BIT4;
6283
6284 usc_OutReg( info, PCR, Control );
6285
6286}
6287
6288
6289
6290
6291
6292
6293
6294
6295
6296
6297static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
6298{
6299 if ( data_rate ) {
6300
6301
6302
6303
6304
6305
6306
6307
6308
6309
6310
6311
6312
6313
6314 usc_OutReg( info, CMCR, 0x0f64 );
6315
6316
6317
6318
6319
6320
6321
6322
6323 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6324 usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6325 else
6326 usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6327
6328
6329
6330
6331
6332
6333
6334
6335 usc_OutReg( info, HCR,
6336 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
6337
6338
6339
6340
6341 usc_OutReg( info, IOCR,
6342 (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
6343 } else {
6344
6345 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
6346 }
6347
6348}
6349
6350
6351
6352
6353
6354
6355
6356
6357
6358
6359
6360
6361
6362
6363
6364
6365
6366
6367
6368
6369
6370
6371
6372
6373
6374
6375
6376
6377
6378
6379
6380
6381
6382
6383
6384
6385
6386
6387
6388
6389
6390
6391
6392
6393
6394
6395
6396
6397
6398
6399
6400
6401
6402
6403
6404
6405
6406
6407static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
6408{
6409 unsigned int i;
6410
6411 for ( i = 0; i < info->tx_buffer_count; i++ ) {
6412 *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
6413 }
6414
6415 info->current_tx_buffer = 0;
6416 info->start_tx_dma_buffer = 0;
6417 info->tx_dma_buffers_used = 0;
6418
6419 info->get_tx_holding_index = 0;
6420 info->put_tx_holding_index = 0;
6421 info->tx_holding_count = 0;
6422
6423}
6424
6425
6426
6427
6428
6429
6430
6431
6432
6433static int num_free_tx_dma_buffers(struct mgsl_struct *info)
6434{
6435 return info->tx_buffer_count - info->tx_dma_buffers_used;
6436}
6437
6438
6439
6440
6441
6442
6443
6444
6445
6446
6447
6448static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
6449{
6450 unsigned int i;
6451
6452 for ( i = 0; i < info->rx_buffer_count; i++ ) {
6453 *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
6454
6455
6456 }
6457
6458 info->current_rx_buffer = 0;
6459
6460}
6461
6462
6463
6464
6465
6466
6467
6468
6469
6470
6471
6472
6473
6474
6475
6476static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
6477{
6478 bool Done = false;
6479 DMABUFFERENTRY *pBufEntry;
6480 unsigned int Index;
6481
6482
6483
6484
6485 Index = StartIndex;
6486
6487 while( !Done ) {
6488 pBufEntry = &(info->rx_buffer_list[Index]);
6489
6490 if ( Index == EndIndex ) {
6491
6492 Done = true;
6493 }
6494
6495
6496
6497
6498 *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
6499
6500
6501 Index++;
6502 if ( Index == info->rx_buffer_count )
6503 Index = 0;
6504 }
6505
6506
6507 info->current_rx_buffer = Index;
6508
6509}
6510
6511
6512
6513
6514
6515
6516
6517
6518
6519static bool mgsl_get_rx_frame(struct mgsl_struct *info)
6520{
6521 unsigned int StartIndex, EndIndex;
6522 unsigned short status;
6523 DMABUFFERENTRY *pBufEntry;
6524 unsigned int framesize = 0;
6525 bool ReturnCode = false;
6526 unsigned long flags;
6527 struct tty_struct *tty = info->port.tty;
6528 bool return_frame = false;
6529
6530
6531
6532
6533
6534
6535
6536
6537 StartIndex = EndIndex = info->current_rx_buffer;
6538
6539 while( !info->rx_buffer_list[EndIndex].status ) {
6540
6541
6542
6543
6544
6545
6546
6547 if ( info->rx_buffer_list[EndIndex].count )
6548 goto Cleanup;
6549
6550
6551 EndIndex++;
6552 if ( EndIndex == info->rx_buffer_count )
6553 EndIndex = 0;
6554
6555
6556 if ( EndIndex == StartIndex ) {
6557
6558
6559
6560
6561
6562 if ( info->rx_enabled ){
6563 spin_lock_irqsave(&info->irq_spinlock,flags);
6564 usc_start_receiver(info);
6565 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6566 }
6567 goto Cleanup;
6568 }
6569 }
6570
6571
6572
6573
6574 status = info->rx_buffer_list[EndIndex].status;
6575
6576 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6577 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6578 if ( status & RXSTATUS_SHORT_FRAME )
6579 info->icount.rxshort++;
6580 else if ( status & RXSTATUS_ABORT )
6581 info->icount.rxabort++;
6582 else if ( status & RXSTATUS_OVERRUN )
6583 info->icount.rxover++;
6584 else {
6585 info->icount.rxcrc++;
6586 if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
6587 return_frame = true;
6588 }
6589 framesize = 0;
6590#if SYNCLINK_GENERIC_HDLC
6591 {
6592 info->netdev->stats.rx_errors++;
6593 info->netdev->stats.rx_frame_errors++;
6594 }
6595#endif
6596 } else
6597 return_frame = true;
6598
6599 if ( return_frame ) {
6600
6601
6602
6603
6604
6605
6606 framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
6607
6608
6609 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
6610 framesize -= 2;
6611 else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
6612 framesize -= 4;
6613 }
6614
6615 if ( debug_level >= DEBUG_LEVEL_BH )
6616 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6617 __FILE__,__LINE__,info->device_name,status,framesize);
6618
6619 if ( debug_level >= DEBUG_LEVEL_DATA )
6620 mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
6621 min_t(int, framesize, DMABUFFERSIZE),0);
6622
6623 if (framesize) {
6624 if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
6625 ((framesize+1) > info->max_frame_size) ) ||
6626 (framesize > info->max_frame_size) )
6627 info->icount.rxlong++;
6628 else {
6629
6630 int copy_count = framesize;
6631 int index = StartIndex;
6632 unsigned char *ptmp = info->intermediate_rxbuffer;
6633
6634 if ( !(status & RXSTATUS_CRC_ERROR))
6635 info->icount.rxok++;
6636
6637 while(copy_count) {
6638 int partial_count;
6639 if ( copy_count > DMABUFFERSIZE )
6640 partial_count = DMABUFFERSIZE;
6641 else
6642 partial_count = copy_count;
6643
6644 pBufEntry = &(info->rx_buffer_list[index]);
6645 memcpy( ptmp, pBufEntry->virt_addr, partial_count );
6646 ptmp += partial_count;
6647 copy_count -= partial_count;
6648
6649 if ( ++index == info->rx_buffer_count )
6650 index = 0;
6651 }
6652
6653 if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
6654 ++framesize;
6655 *ptmp = (status & RXSTATUS_CRC_ERROR ?
6656 RX_CRC_ERROR :
6657 RX_OK);
6658
6659 if ( debug_level >= DEBUG_LEVEL_DATA )
6660 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6661 __FILE__,__LINE__,info->device_name,
6662 *ptmp);
6663 }
6664
6665#if SYNCLINK_GENERIC_HDLC
6666 if (info->netcount)
6667 hdlcdev_rx(info,info->intermediate_rxbuffer,framesize);
6668 else
6669#endif
6670 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6671 }
6672 }
6673
6674 mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
6675
6676 ReturnCode = true;
6677
6678Cleanup:
6679
6680 if ( info->rx_enabled && info->rx_overflow ) {
6681
6682
6683
6684
6685
6686 if ( !info->rx_buffer_list[EndIndex].status &&
6687 info->rx_buffer_list[EndIndex].count ) {
6688 spin_lock_irqsave(&info->irq_spinlock,flags);
6689 usc_start_receiver(info);
6690 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6691 }
6692 }
6693
6694 return ReturnCode;
6695
6696}
6697
6698
6699
6700
6701
6702
6703
6704
6705
6706
6707
6708
6709
6710
6711
6712
6713
6714
6715
6716
6717static bool mgsl_get_raw_rx_frame(struct mgsl_struct *info)
6718{
6719 unsigned int CurrentIndex, NextIndex;
6720 unsigned short status;
6721 DMABUFFERENTRY *pBufEntry;
6722 unsigned int framesize = 0;
6723 bool ReturnCode = false;
6724 unsigned long flags;
6725 struct tty_struct *tty = info->port.tty;
6726
6727
6728
6729
6730
6731
6732
6733
6734
6735
6736
6737
6738
6739
6740
6741
6742 CurrentIndex = NextIndex = info->current_rx_buffer;
6743 ++NextIndex;
6744 if ( NextIndex == info->rx_buffer_count )
6745 NextIndex = 0;
6746
6747 if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
6748 (info->rx_buffer_list[CurrentIndex].count == 0 &&
6749 info->rx_buffer_list[NextIndex].count == 0)) {
6750
6751
6752
6753
6754
6755
6756
6757 status = info->rx_buffer_list[CurrentIndex].status;
6758
6759 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6760 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6761 if ( status & RXSTATUS_SHORT_FRAME )
6762 info->icount.rxshort++;
6763 else if ( status & RXSTATUS_ABORT )
6764 info->icount.rxabort++;
6765 else if ( status & RXSTATUS_OVERRUN )
6766 info->icount.rxover++;
6767 else
6768 info->icount.rxcrc++;
6769 framesize = 0;
6770 } else {
6771
6772
6773
6774
6775
6776
6777
6778
6779
6780
6781
6782
6783
6784
6785
6786
6787
6788
6789
6790
6791
6792
6793
6794 if ( status ) {
6795
6796
6797
6798
6799
6800
6801
6802
6803
6804
6805
6806 if ( info->rx_buffer_list[CurrentIndex].rcc )
6807 framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
6808 else
6809 framesize = DMABUFFERSIZE;
6810 }
6811 else
6812 framesize = DMABUFFERSIZE;
6813 }
6814
6815 if ( framesize > DMABUFFERSIZE ) {
6816
6817
6818
6819
6820
6821
6822 framesize = framesize % DMABUFFERSIZE;
6823 }
6824
6825
6826 if ( debug_level >= DEBUG_LEVEL_BH )
6827 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6828 __FILE__,__LINE__,info->device_name,status,framesize);
6829
6830 if ( debug_level >= DEBUG_LEVEL_DATA )
6831 mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
6832 min_t(int, framesize, DMABUFFERSIZE),0);
6833
6834 if (framesize) {
6835
6836
6837
6838 pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
6839 memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
6840 info->icount.rxok++;
6841
6842 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6843 }
6844
6845
6846 mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
6847
6848 ReturnCode = true;
6849 }
6850
6851
6852 if ( info->rx_enabled && info->rx_overflow ) {
6853
6854
6855
6856
6857
6858 if ( !info->rx_buffer_list[CurrentIndex].status &&
6859 info->rx_buffer_list[CurrentIndex].count ) {
6860 spin_lock_irqsave(&info->irq_spinlock,flags);
6861 usc_start_receiver(info);
6862 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6863 }
6864 }
6865
6866 return ReturnCode;
6867
6868}
6869
6870
6871
6872
6873
6874
6875
6876
6877
6878
6879
6880
6881
6882static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info,
6883 const char *Buffer, unsigned int BufferSize)
6884{
6885 unsigned short Copycount;
6886 unsigned int i = 0;
6887 DMABUFFERENTRY *pBufEntry;
6888
6889 if ( debug_level >= DEBUG_LEVEL_DATA )
6890 mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1);
6891
6892 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
6893
6894
6895
6896 info->cmr_value |= BIT13;
6897 }
6898
6899
6900
6901
6902
6903 i = info->current_tx_buffer;
6904 info->start_tx_dma_buffer = i;
6905
6906
6907
6908
6909 info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
6910 info->tx_buffer_list[i].rcc = BufferSize;
6911 info->tx_buffer_list[i].count = BufferSize;
6912
6913
6914
6915
6916 while( BufferSize ){
6917
6918 pBufEntry = &info->tx_buffer_list[i++];
6919
6920 if ( i == info->tx_buffer_count )
6921 i=0;
6922
6923
6924
6925 if ( BufferSize > DMABUFFERSIZE )
6926 Copycount = DMABUFFERSIZE;
6927 else
6928 Copycount = BufferSize;
6929
6930
6931
6932 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6933 mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
6934 else
6935 memcpy(pBufEntry->virt_addr, Buffer, Copycount);
6936
6937 pBufEntry->count = Copycount;
6938
6939
6940 Buffer += Copycount;
6941 BufferSize -= Copycount;
6942
6943 ++info->tx_dma_buffers_used;
6944 }
6945
6946
6947 info->current_tx_buffer = i;
6948
6949}
6950
6951
6952
6953
6954
6955
6956
6957
6958
6959static bool mgsl_register_test( struct mgsl_struct *info )
6960{
6961 static unsigned short BitPatterns[] =
6962 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
6963 static unsigned int Patterncount = ARRAY_SIZE(BitPatterns);
6964 unsigned int i;
6965 bool rc = true;
6966 unsigned long flags;
6967
6968 spin_lock_irqsave(&info->irq_spinlock,flags);
6969 usc_reset(info);
6970
6971
6972
6973 if ( (usc_InReg( info, SICR ) != 0) ||
6974 (usc_InReg( info, IVR ) != 0) ||
6975 (usc_InDmaReg( info, DIVR ) != 0) ){
6976 rc = false;
6977 }
6978
6979 if ( rc ){
6980
6981
6982
6983 for ( i = 0 ; i < Patterncount ; i++ ) {
6984 usc_OutReg( info, TC0R, BitPatterns[i] );
6985 usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
6986 usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
6987 usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
6988 usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
6989 usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
6990
6991 if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
6992 (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
6993 (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
6994 (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
6995 (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
6996 (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
6997 rc = false;
6998 break;
6999 }
7000 }
7001 }
7002
7003 usc_reset(info);
7004 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7005
7006 return rc;
7007
7008}
7009
7010
7011
7012
7013
7014
7015static bool mgsl_irq_test( struct mgsl_struct *info )
7016{
7017 unsigned long EndTime;
7018 unsigned long flags;
7019
7020 spin_lock_irqsave(&info->irq_spinlock,flags);
7021 usc_reset(info);
7022
7023
7024
7025
7026
7027
7028 info->irq_occurred = false;
7029
7030
7031
7032
7033
7034 usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
7035
7036 usc_EnableMasterIrqBit(info);
7037 usc_EnableInterrupts(info, IO_PIN);
7038 usc_ClearIrqPendingBits(info, IO_PIN);
7039
7040 usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
7041 usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
7042
7043 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7044
7045 EndTime=100;
7046 while( EndTime-- && !info->irq_occurred ) {
7047 msleep_interruptible(10);
7048 }
7049
7050 spin_lock_irqsave(&info->irq_spinlock,flags);
7051 usc_reset(info);
7052 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7053
7054 return info->irq_occurred;
7055
7056}
7057
7058
7059
7060
7061
7062
7063
7064
7065
7066
7067static bool mgsl_dma_test( struct mgsl_struct *info )
7068{
7069 unsigned short FifoLevel;
7070 unsigned long phys_addr;
7071 unsigned int FrameSize;
7072 unsigned int i;
7073 char *TmpPtr;
7074 bool rc = true;
7075 unsigned short status=0;
7076 unsigned long EndTime;
7077 unsigned long flags;
7078 MGSL_PARAMS tmp_params;
7079
7080
7081 memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
7082
7083 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
7084
7085#define TESTFRAMESIZE 40
7086
7087 spin_lock_irqsave(&info->irq_spinlock,flags);
7088
7089
7090
7091 usc_reset(info);
7092 usc_set_sdlc_mode(info);
7093 usc_enable_loopback(info,1);
7094
7095
7096
7097
7098
7099
7100
7101
7102
7103
7104
7105
7106
7107
7108
7109
7110
7111
7112
7113
7114
7115 usc_OutDmaReg( info, RDMR, 0xe200 );
7116
7117 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7118
7119
7120
7121
7122 FrameSize = TESTFRAMESIZE;
7123
7124
7125
7126
7127 info->tx_buffer_list[0].count = FrameSize;
7128 info->tx_buffer_list[0].rcc = FrameSize;
7129 info->tx_buffer_list[0].status = 0x4000;
7130
7131
7132
7133 TmpPtr = info->tx_buffer_list[0].virt_addr;
7134 for (i = 0; i < FrameSize; i++ )
7135 *TmpPtr++ = i;
7136
7137
7138
7139
7140 info->rx_buffer_list[0].status = 0;
7141 info->rx_buffer_list[0].count = FrameSize + 4;
7142
7143
7144
7145 memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
7146
7147
7148
7149
7150 info->tx_buffer_list[1].count = 0;
7151 info->rx_buffer_list[1].count = 0;
7152
7153
7154
7155
7156
7157
7158 spin_lock_irqsave(&info->irq_spinlock,flags);
7159
7160
7161 usc_RTCmd( info, RTCmd_PurgeRxFifo );
7162
7163
7164 phys_addr = info->rx_buffer_list[0].phys_entry;
7165 usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
7166 usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
7167
7168
7169 usc_InDmaReg( info, RDMR );
7170 usc_DmaCmd( info, DmaCmd_InitRxChannel );
7171
7172
7173 usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
7174
7175 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7176
7177
7178
7179
7180
7181
7182
7183 EndTime = jiffies + msecs_to_jiffies(100);
7184
7185 for(;;) {
7186 if (time_after(jiffies, EndTime)) {
7187 rc = false;
7188 break;
7189 }
7190
7191 spin_lock_irqsave(&info->irq_spinlock,flags);
7192 status = usc_InDmaReg( info, RDMR );
7193 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7194
7195 if ( !(status & BIT4) && (status & BIT5) ) {
7196
7197
7198
7199 break;
7200 }
7201 }
7202
7203
7204
7205
7206
7207
7208 spin_lock_irqsave(&info->irq_spinlock,flags);
7209
7210
7211
7212
7213 usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
7214 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7215
7216
7217
7218 phys_addr = info->tx_buffer_list[0].phys_entry;
7219 usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
7220 usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
7221
7222
7223
7224 usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
7225 usc_DmaCmd( info, DmaCmd_InitTxChannel );
7226
7227
7228
7229 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
7230
7231 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7232
7233
7234
7235
7236
7237
7238
7239 EndTime = jiffies + msecs_to_jiffies(100);
7240
7241 for(;;) {
7242 if (time_after(jiffies, EndTime)) {
7243 rc = false;
7244 break;
7245 }
7246
7247 spin_lock_irqsave(&info->irq_spinlock,flags);
7248 FifoLevel = usc_InReg(info, TICR) >> 8;
7249 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7250
7251 if ( FifoLevel < 16 )
7252 break;
7253 else
7254 if ( FrameSize < 32 ) {
7255
7256
7257 if ( FifoLevel <= (32 - FrameSize) )
7258 break;
7259 }
7260 }
7261
7262
7263 if ( rc )
7264 {
7265
7266
7267 spin_lock_irqsave(&info->irq_spinlock,flags);
7268
7269
7270 usc_TCmd( info, TCmd_SendFrame );
7271 usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
7272
7273 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7274
7275
7276
7277
7278
7279
7280
7281 EndTime = jiffies + msecs_to_jiffies(100);
7282
7283
7284
7285 spin_lock_irqsave(&info->irq_spinlock,flags);
7286 status = usc_InReg( info, TCSR );
7287 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7288
7289 while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) {
7290 if (time_after(jiffies, EndTime)) {
7291 rc = false;
7292 break;
7293 }
7294
7295 spin_lock_irqsave(&info->irq_spinlock,flags);
7296 status = usc_InReg( info, TCSR );
7297 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7298 }
7299 }
7300
7301
7302 if ( rc ){
7303
7304 if ( status & (BIT5 + BIT1) )
7305 rc = false;
7306 }
7307
7308 if ( rc ) {
7309
7310
7311
7312 EndTime = jiffies + msecs_to_jiffies(100);
7313
7314
7315 status=info->rx_buffer_list[0].status;
7316 while ( status == 0 ) {
7317 if (time_after(jiffies, EndTime)) {
7318 rc = false;
7319 break;
7320 }
7321 status=info->rx_buffer_list[0].status;
7322 }
7323 }
7324
7325
7326 if ( rc ) {
7327
7328 status = info->rx_buffer_list[0].status;
7329
7330 if ( status & (BIT8 + BIT3 + BIT1) ) {
7331
7332 rc = false;
7333 } else {
7334 if ( memcmp( info->tx_buffer_list[0].virt_addr ,
7335 info->rx_buffer_list[0].virt_addr, FrameSize ) ){
7336 rc = false;
7337 }
7338 }
7339 }
7340
7341 spin_lock_irqsave(&info->irq_spinlock,flags);
7342 usc_reset( info );
7343 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7344
7345
7346 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
7347
7348 return rc;
7349
7350}
7351
7352
7353
7354
7355
7356
7357
7358
7359static int mgsl_adapter_test( struct mgsl_struct *info )
7360{
7361 if ( debug_level >= DEBUG_LEVEL_INFO )
7362 printk( "%s(%d):Testing device %s\n",
7363 __FILE__,__LINE__,info->device_name );
7364
7365 if ( !mgsl_register_test( info ) ) {
7366 info->init_error = DiagStatus_AddressFailure;
7367 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7368 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
7369 return -ENODEV;
7370 }
7371
7372 if ( !mgsl_irq_test( info ) ) {
7373 info->init_error = DiagStatus_IrqFailure;
7374 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7375 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
7376 return -ENODEV;
7377 }
7378
7379 if ( !mgsl_dma_test( info ) ) {
7380 info->init_error = DiagStatus_DmaFailure;
7381 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7382 __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
7383 return -ENODEV;
7384 }
7385
7386 if ( debug_level >= DEBUG_LEVEL_INFO )
7387 printk( "%s(%d):device %s passed diagnostics\n",
7388 __FILE__,__LINE__,info->device_name );
7389
7390 return 0;
7391
7392}
7393
7394
7395
7396
7397
7398
7399
7400
7401static bool mgsl_memory_test( struct mgsl_struct *info )
7402{
7403 static unsigned long BitPatterns[] =
7404 { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7405 unsigned long Patterncount = ARRAY_SIZE(BitPatterns);
7406 unsigned long i;
7407 unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
7408 unsigned long * TestAddr;
7409
7410 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
7411 return true;
7412
7413 TestAddr = (unsigned long *)info->memory_base;
7414
7415
7416
7417 for ( i = 0 ; i < Patterncount ; i++ ) {
7418 *TestAddr = BitPatterns[i];
7419 if ( *TestAddr != BitPatterns[i] )
7420 return false;
7421 }
7422
7423
7424
7425
7426 for ( i = 0 ; i < TestLimit ; i++ ) {
7427 *TestAddr = i * 4;
7428 TestAddr++;
7429 }
7430
7431 TestAddr = (unsigned long *)info->memory_base;
7432
7433 for ( i = 0 ; i < TestLimit ; i++ ) {
7434 if ( *TestAddr != i * 4 )
7435 return false;
7436 TestAddr++;
7437 }
7438
7439 memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
7440
7441 return true;
7442
7443}
7444
7445
7446
7447
7448
7449
7450
7451
7452
7453
7454
7455
7456
7457
7458
7459
7460
7461
7462
7463
7464
7465
7466
7467
7468
7469
7470
7471
7472
7473
7474
7475
7476
7477
7478
7479
7480
7481
7482static void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
7483 unsigned short count )
7484{
7485
7486#define PCI_LOAD_INTERVAL 64
7487
7488 unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
7489 unsigned short Index;
7490 unsigned long Dummy;
7491
7492 for ( Index = 0 ; Index < Intervalcount ; Index++ )
7493 {
7494 memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
7495 Dummy = *((volatile unsigned long *)TargetPtr);
7496 TargetPtr += PCI_LOAD_INTERVAL;
7497 SourcePtr += PCI_LOAD_INTERVAL;
7498 }
7499
7500 memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
7501
7502}
7503
7504static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
7505{
7506 int i;
7507 int linecount;
7508 if (xmit)
7509 printk("%s tx data:\n",info->device_name);
7510 else
7511 printk("%s rx data:\n",info->device_name);
7512
7513 while(count) {
7514 if (count > 16)
7515 linecount = 16;
7516 else
7517 linecount = count;
7518
7519 for(i=0;i<linecount;i++)
7520 printk("%02X ",(unsigned char)data[i]);
7521 for(;i<17;i++)
7522 printk(" ");
7523 for(i=0;i<linecount;i++) {
7524 if (data[i]>=040 && data[i]<=0176)
7525 printk("%c",data[i]);
7526 else
7527 printk(".");
7528 }
7529 printk("\n");
7530
7531 data += linecount;
7532 count -= linecount;
7533 }
7534}
7535
7536
7537
7538
7539
7540
7541
7542
7543
7544static void mgsl_tx_timeout(unsigned long context)
7545{
7546 struct mgsl_struct *info = (struct mgsl_struct*)context;
7547 unsigned long flags;
7548
7549 if ( debug_level >= DEBUG_LEVEL_INFO )
7550 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7551 __FILE__,__LINE__,info->device_name);
7552 if(info->tx_active &&
7553 (info->params.mode == MGSL_MODE_HDLC ||
7554 info->params.mode == MGSL_MODE_RAW) ) {
7555 info->icount.txtimeout++;
7556 }
7557 spin_lock_irqsave(&info->irq_spinlock,flags);
7558 info->tx_active = false;
7559 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
7560
7561 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
7562 usc_loopmode_cancel_transmit( info );
7563
7564 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7565
7566#if SYNCLINK_GENERIC_HDLC
7567 if (info->netcount)
7568 hdlcdev_tx_done(info);
7569 else
7570#endif
7571 mgsl_bh_transmit(info);
7572
7573}
7574
7575
7576
7577
7578
7579static int mgsl_loopmode_send_done( struct mgsl_struct * info )
7580{
7581 unsigned long flags;
7582
7583 spin_lock_irqsave(&info->irq_spinlock,flags);
7584 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
7585 if (info->tx_active)
7586 info->loopmode_send_done_requested = true;
7587 else
7588 usc_loopmode_send_done(info);
7589 }
7590 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7591
7592 return 0;
7593}
7594
7595
7596
7597
7598static void usc_loopmode_send_done( struct mgsl_struct * info )
7599{
7600 info->loopmode_send_done_requested = false;
7601
7602 info->cmr_value &= ~BIT13;
7603 usc_OutReg(info, CMR, info->cmr_value);
7604}
7605
7606
7607
7608static void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
7609{
7610
7611 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7612 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
7613 usc_loopmode_send_done( info );
7614}
7615
7616
7617
7618
7619
7620static void usc_loopmode_insert_request( struct mgsl_struct * info )
7621{
7622 info->loopmode_insert_requested = true;
7623
7624
7625
7626
7627 usc_OutReg( info, RICR,
7628 (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
7629
7630
7631 info->cmr_value |= BIT13;
7632 usc_OutReg(info, CMR, info->cmr_value);
7633}
7634
7635
7636
7637static int usc_loopmode_active( struct mgsl_struct * info)
7638{
7639 return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
7640}
7641
7642#if SYNCLINK_GENERIC_HDLC
7643
7644
7645
7646
7647
7648
7649
7650
7651
7652
7653
7654static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
7655 unsigned short parity)
7656{
7657 struct mgsl_struct *info = dev_to_port(dev);
7658 unsigned char new_encoding;
7659 unsigned short new_crctype;
7660
7661
7662 if (info->port.count)
7663 return -EBUSY;
7664
7665 switch (encoding)
7666 {
7667 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
7668 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
7669 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
7670 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
7671 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
7672 default: return -EINVAL;
7673 }
7674
7675 switch (parity)
7676 {
7677 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
7678 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
7679 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
7680 default: return -EINVAL;
7681 }
7682
7683 info->params.encoding = new_encoding;
7684 info->params.crc_type = new_crctype;
7685
7686
7687 if (info->netcount)
7688 mgsl_program_hw(info);
7689
7690 return 0;
7691}
7692
7693
7694
7695
7696
7697
7698
7699static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
7700 struct net_device *dev)
7701{
7702 struct mgsl_struct *info = dev_to_port(dev);
7703 unsigned long flags;
7704
7705 if (debug_level >= DEBUG_LEVEL_INFO)
7706 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
7707
7708
7709 netif_stop_queue(dev);
7710
7711
7712 info->xmit_cnt = skb->len;
7713 mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
7714
7715
7716 dev->stats.tx_packets++;
7717 dev->stats.tx_bytes += skb->len;
7718
7719
7720 dev_kfree_skb(skb);
7721
7722
7723 dev->trans_start = jiffies;
7724
7725
7726 spin_lock_irqsave(&info->irq_spinlock,flags);
7727 if (!info->tx_active)
7728 usc_start_transmitter(info);
7729 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7730
7731 return NETDEV_TX_OK;
7732}
7733
7734
7735
7736
7737
7738
7739
7740
7741
7742static int hdlcdev_open(struct net_device *dev)
7743{
7744 struct mgsl_struct *info = dev_to_port(dev);
7745 int rc;
7746 unsigned long flags;
7747
7748 if (debug_level >= DEBUG_LEVEL_INFO)
7749 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
7750
7751
7752 if ((rc = hdlc_open(dev)))
7753 return rc;
7754
7755
7756 spin_lock_irqsave(&info->netlock, flags);
7757 if (info->port.count != 0 || info->netcount != 0) {
7758 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
7759 spin_unlock_irqrestore(&info->netlock, flags);
7760 return -EBUSY;
7761 }
7762 info->netcount=1;
7763 spin_unlock_irqrestore(&info->netlock, flags);
7764
7765
7766 if ((rc = startup(info)) != 0) {
7767 spin_lock_irqsave(&info->netlock, flags);
7768 info->netcount=0;
7769 spin_unlock_irqrestore(&info->netlock, flags);
7770 return rc;
7771 }
7772
7773
7774 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
7775 mgsl_program_hw(info);
7776
7777
7778 dev->trans_start = jiffies;
7779 netif_start_queue(dev);
7780
7781
7782 spin_lock_irqsave(&info->irq_spinlock, flags);
7783 usc_get_serial_signals(info);
7784 spin_unlock_irqrestore(&info->irq_spinlock, flags);
7785 if (info->serial_signals & SerialSignal_DCD)
7786 netif_carrier_on(dev);
7787 else
7788 netif_carrier_off(dev);
7789 return 0;
7790}
7791
7792
7793
7794
7795
7796
7797
7798
7799
7800static int hdlcdev_close(struct net_device *dev)
7801{
7802 struct mgsl_struct *info = dev_to_port(dev);
7803 unsigned long flags;
7804
7805 if (debug_level >= DEBUG_LEVEL_INFO)
7806 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
7807
7808 netif_stop_queue(dev);
7809
7810
7811 shutdown(info);
7812
7813 hdlc_close(dev);
7814
7815 spin_lock_irqsave(&info->netlock, flags);
7816 info->netcount=0;
7817 spin_unlock_irqrestore(&info->netlock, flags);
7818
7819 return 0;
7820}
7821
7822
7823
7824
7825
7826
7827
7828
7829
7830
7831static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7832{
7833 const size_t size = sizeof(sync_serial_settings);
7834 sync_serial_settings new_line;
7835 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
7836 struct mgsl_struct *info = dev_to_port(dev);
7837 unsigned int flags;
7838
7839 if (debug_level >= DEBUG_LEVEL_INFO)
7840 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
7841
7842
7843 if (info->port.count)
7844 return -EBUSY;
7845
7846 if (cmd != SIOCWANDEV)
7847 return hdlc_ioctl(dev, ifr, cmd);
7848
7849 switch(ifr->ifr_settings.type) {
7850 case IF_GET_IFACE:
7851
7852 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
7853 if (ifr->ifr_settings.size < size) {
7854 ifr->ifr_settings.size = size;
7855 return -ENOBUFS;
7856 }
7857
7858 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7859 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7860 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7861 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7862
7863 switch (flags){
7864 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
7865 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
7866 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
7867 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
7868 default: new_line.clock_type = CLOCK_DEFAULT;
7869 }
7870
7871 new_line.clock_rate = info->params.clock_speed;
7872 new_line.loopback = info->params.loopback ? 1:0;
7873
7874 if (copy_to_user(line, &new_line, size))
7875 return -EFAULT;
7876 return 0;
7877
7878 case IF_IFACE_SYNC_SERIAL:
7879
7880 if(!capable(CAP_NET_ADMIN))
7881 return -EPERM;
7882 if (copy_from_user(&new_line, line, size))
7883 return -EFAULT;
7884
7885 switch (new_line.clock_type)
7886 {
7887 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
7888 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
7889 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
7890 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
7891 case CLOCK_DEFAULT: flags = info->params.flags &
7892 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7893 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7894 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7895 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
7896 default: return -EINVAL;
7897 }
7898
7899 if (new_line.loopback != 0 && new_line.loopback != 1)
7900 return -EINVAL;
7901
7902 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7903 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7904 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7905 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7906 info->params.flags |= flags;
7907
7908 info->params.loopback = new_line.loopback;
7909
7910 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
7911 info->params.clock_speed = new_line.clock_rate;
7912 else
7913 info->params.clock_speed = 0;
7914
7915
7916 if (info->netcount)
7917 mgsl_program_hw(info);
7918 return 0;
7919
7920 default:
7921 return hdlc_ioctl(dev, ifr, cmd);
7922 }
7923}
7924
7925
7926
7927
7928
7929
7930static void hdlcdev_tx_timeout(struct net_device *dev)
7931{
7932 struct mgsl_struct *info = dev_to_port(dev);
7933 unsigned long flags;
7934
7935 if (debug_level >= DEBUG_LEVEL_INFO)
7936 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
7937
7938 dev->stats.tx_errors++;
7939 dev->stats.tx_aborted_errors++;
7940
7941 spin_lock_irqsave(&info->irq_spinlock,flags);
7942 usc_stop_transmitter(info);
7943 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7944
7945 netif_wake_queue(dev);
7946}
7947
7948
7949
7950
7951
7952
7953
7954static void hdlcdev_tx_done(struct mgsl_struct *info)
7955{
7956 if (netif_queue_stopped(info->netdev))
7957 netif_wake_queue(info->netdev);
7958}
7959
7960
7961
7962
7963
7964
7965
7966
7967
7968static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size)
7969{
7970 struct sk_buff *skb = dev_alloc_skb(size);
7971 struct net_device *dev = info->netdev;
7972
7973 if (debug_level >= DEBUG_LEVEL_INFO)
7974 printk("hdlcdev_rx(%s)\n", dev->name);
7975
7976 if (skb == NULL) {
7977 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
7978 dev->name);
7979 dev->stats.rx_dropped++;
7980 return;
7981 }
7982
7983 memcpy(skb_put(skb, size), buf, size);
7984
7985 skb->protocol = hdlc_type_trans(skb, dev);
7986
7987 dev->stats.rx_packets++;
7988 dev->stats.rx_bytes += size;
7989
7990 netif_rx(skb);
7991}
7992
7993static const struct net_device_ops hdlcdev_ops = {
7994 .ndo_open = hdlcdev_open,
7995 .ndo_stop = hdlcdev_close,
7996 .ndo_change_mtu = hdlc_change_mtu,
7997 .ndo_start_xmit = hdlc_start_xmit,
7998 .ndo_do_ioctl = hdlcdev_ioctl,
7999 .ndo_tx_timeout = hdlcdev_tx_timeout,
8000};
8001
8002
8003
8004
8005
8006
8007
8008
8009
8010static int hdlcdev_init(struct mgsl_struct *info)
8011{
8012 int rc;
8013 struct net_device *dev;
8014 hdlc_device *hdlc;
8015
8016
8017
8018 if (!(dev = alloc_hdlcdev(info))) {
8019 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
8020 return -ENOMEM;
8021 }
8022
8023
8024 dev->base_addr = info->io_base;
8025 dev->irq = info->irq_level;
8026 dev->dma = info->dma_level;
8027
8028
8029 dev->netdev_ops = &hdlcdev_ops;
8030 dev->watchdog_timeo = 10 * HZ;
8031 dev->tx_queue_len = 50;
8032
8033
8034 hdlc = dev_to_hdlc(dev);
8035 hdlc->attach = hdlcdev_attach;
8036 hdlc->xmit = hdlcdev_xmit;
8037
8038
8039 if ((rc = register_hdlc_device(dev))) {
8040 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
8041 free_netdev(dev);
8042 return rc;
8043 }
8044
8045 info->netdev = dev;
8046 return 0;
8047}
8048
8049
8050
8051
8052
8053
8054
8055static void hdlcdev_exit(struct mgsl_struct *info)
8056{
8057 unregister_hdlc_device(info->netdev);
8058 free_netdev(info->netdev);
8059 info->netdev = NULL;
8060}
8061
8062#endif
8063
8064
8065static int __devinit synclink_init_one (struct pci_dev *dev,
8066 const struct pci_device_id *ent)
8067{
8068 struct mgsl_struct *info;
8069
8070 if (pci_enable_device(dev)) {
8071 printk("error enabling pci device %p\n", dev);
8072 return -EIO;
8073 }
8074
8075 if (!(info = mgsl_allocate_device())) {
8076 printk("can't allocate device instance data.\n");
8077 return -EIO;
8078 }
8079
8080
8081
8082 info->io_base = pci_resource_start(dev, 2);
8083 info->irq_level = dev->irq;
8084 info->phys_memory_base = pci_resource_start(dev, 3);
8085
8086
8087
8088
8089
8090 info->phys_lcr_base = pci_resource_start(dev, 0);
8091 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
8092 info->phys_lcr_base &= ~(PAGE_SIZE-1);
8093
8094 info->bus_type = MGSL_BUS_TYPE_PCI;
8095 info->io_addr_size = 8;
8096 info->irq_flags = IRQF_SHARED;
8097
8098 if (dev->device == 0x0210) {
8099
8100 info->misc_ctrl_value = 0x007c4080;
8101 info->hw_version = 1;
8102 } else {
8103
8104
8105
8106
8107
8108 info->misc_ctrl_value = 0x087e4546;
8109 info->hw_version = 0;
8110 }
8111
8112 mgsl_add_device(info);
8113
8114 return 0;
8115}
8116
8117static void __devexit synclink_remove_one (struct pci_dev *dev)
8118{
8119}
8120
8121