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34#include "drmP.h"
35#include "drm.h"
36#include "i830_drm.h"
37#include "i830_drv.h"
38#include <linux/interrupt.h>
39#include <linux/smp_lock.h>
40#include <linux/pagemap.h>
41#include <linux/delay.h>
42#include <linux/slab.h>
43#include <asm/uaccess.h>
44
45#define I830_BUF_FREE 2
46#define I830_BUF_CLIENT 1
47#define I830_BUF_HARDWARE 0
48
49#define I830_BUF_UNMAPPED 0
50#define I830_BUF_MAPPED 1
51
52static struct drm_buf *i830_freelist_get(struct drm_device * dev)
53{
54 struct drm_device_dma *dma = dev->dma;
55 int i;
56 int used;
57
58
59
60 for (i = 0; i < dma->buf_count; i++) {
61 struct drm_buf *buf = dma->buflist[i];
62 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
63
64 used = cmpxchg(buf_priv->in_use, I830_BUF_FREE,
65 I830_BUF_CLIENT);
66 if (used == I830_BUF_FREE)
67 return buf;
68 }
69 return NULL;
70}
71
72
73
74
75
76static int i830_freelist_put(struct drm_device *dev, struct drm_buf *buf)
77{
78 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
79 int used;
80
81
82 used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, I830_BUF_FREE);
83 if (used != I830_BUF_CLIENT) {
84 DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
85 return -EINVAL;
86 }
87
88 return 0;
89}
90
91static int i830_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
92{
93 struct drm_file *priv = filp->private_data;
94 struct drm_device *dev;
95 drm_i830_private_t *dev_priv;
96 struct drm_buf *buf;
97 drm_i830_buf_priv_t *buf_priv;
98
99 lock_kernel();
100 dev = priv->minor->dev;
101 dev_priv = dev->dev_private;
102 buf = dev_priv->mmap_buffer;
103 buf_priv = buf->dev_private;
104
105 vma->vm_flags |= (VM_IO | VM_DONTCOPY);
106 vma->vm_file = filp;
107
108 buf_priv->currently_mapped = I830_BUF_MAPPED;
109 unlock_kernel();
110
111 if (io_remap_pfn_range(vma, vma->vm_start,
112 vma->vm_pgoff,
113 vma->vm_end - vma->vm_start, vma->vm_page_prot))
114 return -EAGAIN;
115 return 0;
116}
117
118static const struct file_operations i830_buffer_fops = {
119 .open = drm_open,
120 .release = drm_release,
121 .unlocked_ioctl = i830_ioctl,
122 .mmap = i830_mmap_buffers,
123 .fasync = drm_fasync,
124 .llseek = noop_llseek,
125};
126
127static int i830_map_buffer(struct drm_buf *buf, struct drm_file *file_priv)
128{
129 struct drm_device *dev = file_priv->minor->dev;
130 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
131 drm_i830_private_t *dev_priv = dev->dev_private;
132 const struct file_operations *old_fops;
133 unsigned long virtual;
134 int retcode = 0;
135
136 if (buf_priv->currently_mapped == I830_BUF_MAPPED)
137 return -EINVAL;
138
139 down_write(¤t->mm->mmap_sem);
140 old_fops = file_priv->filp->f_op;
141 file_priv->filp->f_op = &i830_buffer_fops;
142 dev_priv->mmap_buffer = buf;
143 virtual = do_mmap(file_priv->filp, 0, buf->total, PROT_READ | PROT_WRITE,
144 MAP_SHARED, buf->bus_address);
145 dev_priv->mmap_buffer = NULL;
146 file_priv->filp->f_op = old_fops;
147 if (IS_ERR((void *)virtual)) {
148
149 DRM_ERROR("mmap error\n");
150 retcode = PTR_ERR((void *)virtual);
151 buf_priv->virtual = NULL;
152 } else {
153 buf_priv->virtual = (void __user *)virtual;
154 }
155 up_write(¤t->mm->mmap_sem);
156
157 return retcode;
158}
159
160static int i830_unmap_buffer(struct drm_buf *buf)
161{
162 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
163 int retcode = 0;
164
165 if (buf_priv->currently_mapped != I830_BUF_MAPPED)
166 return -EINVAL;
167
168 down_write(¤t->mm->mmap_sem);
169 retcode = do_munmap(current->mm,
170 (unsigned long)buf_priv->virtual,
171 (size_t) buf->total);
172 up_write(¤t->mm->mmap_sem);
173
174 buf_priv->currently_mapped = I830_BUF_UNMAPPED;
175 buf_priv->virtual = NULL;
176
177 return retcode;
178}
179
180static int i830_dma_get_buffer(struct drm_device *dev, drm_i830_dma_t *d,
181 struct drm_file *file_priv)
182{
183 struct drm_buf *buf;
184 drm_i830_buf_priv_t *buf_priv;
185 int retcode = 0;
186
187 buf = i830_freelist_get(dev);
188 if (!buf) {
189 retcode = -ENOMEM;
190 DRM_DEBUG("retcode=%d\n", retcode);
191 return retcode;
192 }
193
194 retcode = i830_map_buffer(buf, file_priv);
195 if (retcode) {
196 i830_freelist_put(dev, buf);
197 DRM_ERROR("mapbuf failed, retcode %d\n", retcode);
198 return retcode;
199 }
200 buf->file_priv = file_priv;
201 buf_priv = buf->dev_private;
202 d->granted = 1;
203 d->request_idx = buf->idx;
204 d->request_size = buf->total;
205 d->virtual = buf_priv->virtual;
206
207 return retcode;
208}
209
210static int i830_dma_cleanup(struct drm_device *dev)
211{
212 struct drm_device_dma *dma = dev->dma;
213
214
215
216
217
218 if (dev->irq_enabled)
219 drm_irq_uninstall(dev);
220
221 if (dev->dev_private) {
222 int i;
223 drm_i830_private_t *dev_priv =
224 (drm_i830_private_t *) dev->dev_private;
225
226 if (dev_priv->ring.virtual_start)
227 drm_core_ioremapfree(&dev_priv->ring.map, dev);
228 if (dev_priv->hw_status_page) {
229 pci_free_consistent(dev->pdev, PAGE_SIZE,
230 dev_priv->hw_status_page,
231 dev_priv->dma_status_page);
232
233 I830_WRITE(0x02080, 0x1ffff000);
234 }
235
236 kfree(dev->dev_private);
237 dev->dev_private = NULL;
238
239 for (i = 0; i < dma->buf_count; i++) {
240 struct drm_buf *buf = dma->buflist[i];
241 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
242 if (buf_priv->kernel_virtual && buf->total)
243 drm_core_ioremapfree(&buf_priv->map, dev);
244 }
245 }
246 return 0;
247}
248
249int i830_wait_ring(struct drm_device *dev, int n, const char *caller)
250{
251 drm_i830_private_t *dev_priv = dev->dev_private;
252 drm_i830_ring_buffer_t *ring = &(dev_priv->ring);
253 int iters = 0;
254 unsigned long end;
255 unsigned int last_head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
256
257 end = jiffies + (HZ * 3);
258 while (ring->space < n) {
259 ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
260 ring->space = ring->head - (ring->tail + 8);
261 if (ring->space < 0)
262 ring->space += ring->Size;
263
264 if (ring->head != last_head) {
265 end = jiffies + (HZ * 3);
266 last_head = ring->head;
267 }
268
269 iters++;
270 if (time_before(end, jiffies)) {
271 DRM_ERROR("space: %d wanted %d\n", ring->space, n);
272 DRM_ERROR("lockup\n");
273 goto out_wait_ring;
274 }
275 udelay(1);
276 dev_priv->sarea_priv->perf_boxes |= I830_BOX_WAIT;
277 }
278
279out_wait_ring:
280 return iters;
281}
282
283static void i830_kernel_lost_context(struct drm_device *dev)
284{
285 drm_i830_private_t *dev_priv = dev->dev_private;
286 drm_i830_ring_buffer_t *ring = &(dev_priv->ring);
287
288 ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
289 ring->tail = I830_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
290 ring->space = ring->head - (ring->tail + 8);
291 if (ring->space < 0)
292 ring->space += ring->Size;
293
294 if (ring->head == ring->tail)
295 dev_priv->sarea_priv->perf_boxes |= I830_BOX_RING_EMPTY;
296}
297
298static int i830_freelist_init(struct drm_device *dev, drm_i830_private_t *dev_priv)
299{
300 struct drm_device_dma *dma = dev->dma;
301 int my_idx = 36;
302 u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx);
303 int i;
304
305 if (dma->buf_count > 1019) {
306
307 return -EINVAL;
308 }
309
310 for (i = 0; i < dma->buf_count; i++) {
311 struct drm_buf *buf = dma->buflist[i];
312 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
313
314 buf_priv->in_use = hw_status++;
315 buf_priv->my_use_idx = my_idx;
316 my_idx += 4;
317
318 *buf_priv->in_use = I830_BUF_FREE;
319
320 buf_priv->map.offset = buf->bus_address;
321 buf_priv->map.size = buf->total;
322 buf_priv->map.type = _DRM_AGP;
323 buf_priv->map.flags = 0;
324 buf_priv->map.mtrr = 0;
325
326 drm_core_ioremap(&buf_priv->map, dev);
327 buf_priv->kernel_virtual = buf_priv->map.handle;
328 }
329 return 0;
330}
331
332static int i830_dma_initialize(struct drm_device *dev,
333 drm_i830_private_t *dev_priv,
334 drm_i830_init_t *init)
335{
336 struct drm_map_list *r_list;
337
338 memset(dev_priv, 0, sizeof(drm_i830_private_t));
339
340 list_for_each_entry(r_list, &dev->maplist, head) {
341 if (r_list->map &&
342 r_list->map->type == _DRM_SHM &&
343 r_list->map->flags & _DRM_CONTAINS_LOCK) {
344 dev_priv->sarea_map = r_list->map;
345 break;
346 }
347 }
348
349 if (!dev_priv->sarea_map) {
350 dev->dev_private = (void *)dev_priv;
351 i830_dma_cleanup(dev);
352 DRM_ERROR("can not find sarea!\n");
353 return -EINVAL;
354 }
355 dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
356 if (!dev_priv->mmio_map) {
357 dev->dev_private = (void *)dev_priv;
358 i830_dma_cleanup(dev);
359 DRM_ERROR("can not find mmio map!\n");
360 return -EINVAL;
361 }
362 dev->agp_buffer_token = init->buffers_offset;
363 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
364 if (!dev->agp_buffer_map) {
365 dev->dev_private = (void *)dev_priv;
366 i830_dma_cleanup(dev);
367 DRM_ERROR("can not find dma buffer map!\n");
368 return -EINVAL;
369 }
370
371 dev_priv->sarea_priv = (drm_i830_sarea_t *)
372 ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset);
373
374 dev_priv->ring.Start = init->ring_start;
375 dev_priv->ring.End = init->ring_end;
376 dev_priv->ring.Size = init->ring_size;
377
378 dev_priv->ring.map.offset = dev->agp->base + init->ring_start;
379 dev_priv->ring.map.size = init->ring_size;
380 dev_priv->ring.map.type = _DRM_AGP;
381 dev_priv->ring.map.flags = 0;
382 dev_priv->ring.map.mtrr = 0;
383
384 drm_core_ioremap(&dev_priv->ring.map, dev);
385
386 if (dev_priv->ring.map.handle == NULL) {
387 dev->dev_private = (void *)dev_priv;
388 i830_dma_cleanup(dev);
389 DRM_ERROR("can not ioremap virtual address for"
390 " ring buffer\n");
391 return -ENOMEM;
392 }
393
394 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
395
396 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
397
398 dev_priv->w = init->w;
399 dev_priv->h = init->h;
400 dev_priv->pitch = init->pitch;
401 dev_priv->back_offset = init->back_offset;
402 dev_priv->depth_offset = init->depth_offset;
403 dev_priv->front_offset = init->front_offset;
404
405 dev_priv->front_di1 = init->front_offset | init->pitch_bits;
406 dev_priv->back_di1 = init->back_offset | init->pitch_bits;
407 dev_priv->zi1 = init->depth_offset | init->pitch_bits;
408
409 DRM_DEBUG("front_di1 %x\n", dev_priv->front_di1);
410 DRM_DEBUG("back_offset %x\n", dev_priv->back_offset);
411 DRM_DEBUG("back_di1 %x\n", dev_priv->back_di1);
412 DRM_DEBUG("pitch_bits %x\n", init->pitch_bits);
413
414 dev_priv->cpp = init->cpp;
415
416
417
418
419 dev_priv->back_pitch = init->back_pitch;
420 dev_priv->depth_pitch = init->depth_pitch;
421 dev_priv->do_boxes = 0;
422 dev_priv->use_mi_batchbuffer_start = 0;
423
424
425 dev_priv->hw_status_page =
426 pci_alloc_consistent(dev->pdev, PAGE_SIZE,
427 &dev_priv->dma_status_page);
428 if (!dev_priv->hw_status_page) {
429 dev->dev_private = (void *)dev_priv;
430 i830_dma_cleanup(dev);
431 DRM_ERROR("Can not allocate hardware status page\n");
432 return -ENOMEM;
433 }
434 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
435 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
436
437 I830_WRITE(0x02080, dev_priv->dma_status_page);
438 DRM_DEBUG("Enabled hardware status page\n");
439
440
441 if (i830_freelist_init(dev, dev_priv) != 0) {
442 dev->dev_private = (void *)dev_priv;
443 i830_dma_cleanup(dev);
444 DRM_ERROR("Not enough space in the status page for"
445 " the freelist\n");
446 return -ENOMEM;
447 }
448 dev->dev_private = (void *)dev_priv;
449
450 return 0;
451}
452
453static int i830_dma_init(struct drm_device *dev, void *data,
454 struct drm_file *file_priv)
455{
456 drm_i830_private_t *dev_priv;
457 drm_i830_init_t *init = data;
458 int retcode = 0;
459
460 switch (init->func) {
461 case I830_INIT_DMA:
462 dev_priv = kmalloc(sizeof(drm_i830_private_t), GFP_KERNEL);
463 if (dev_priv == NULL)
464 return -ENOMEM;
465 retcode = i830_dma_initialize(dev, dev_priv, init);
466 break;
467 case I830_CLEANUP_DMA:
468 retcode = i830_dma_cleanup(dev);
469 break;
470 default:
471 retcode = -EINVAL;
472 break;
473 }
474
475 return retcode;
476}
477
478#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
479#define ST1_ENABLE (1<<16)
480#define ST1_MASK (0xffff)
481
482
483
484
485static void i830EmitContextVerified(struct drm_device *dev, unsigned int *code)
486{
487 drm_i830_private_t *dev_priv = dev->dev_private;
488 int i, j = 0;
489 unsigned int tmp;
490 RING_LOCALS;
491
492 BEGIN_LP_RING(I830_CTX_SETUP_SIZE + 4);
493
494 for (i = 0; i < I830_CTXREG_BLENDCOLR0; i++) {
495 tmp = code[i];
496 if ((tmp & (7 << 29)) == CMD_3D &&
497 (tmp & (0x1f << 24)) < (0x1d << 24)) {
498 OUT_RING(tmp);
499 j++;
500 } else {
501 DRM_ERROR("Skipping %d\n", i);
502 }
503 }
504
505 OUT_RING(STATE3D_CONST_BLEND_COLOR_CMD);
506 OUT_RING(code[I830_CTXREG_BLENDCOLR]);
507 j += 2;
508
509 for (i = I830_CTXREG_VF; i < I830_CTXREG_MCSB0; i++) {
510 tmp = code[i];
511 if ((tmp & (7 << 29)) == CMD_3D &&
512 (tmp & (0x1f << 24)) < (0x1d << 24)) {
513 OUT_RING(tmp);
514 j++;
515 } else {
516 DRM_ERROR("Skipping %d\n", i);
517 }
518 }
519
520 OUT_RING(STATE3D_MAP_COORD_SETBIND_CMD);
521 OUT_RING(code[I830_CTXREG_MCSB1]);
522 j += 2;
523
524 if (j & 1)
525 OUT_RING(0);
526
527 ADVANCE_LP_RING();
528}
529
530static void i830EmitTexVerified(struct drm_device *dev, unsigned int *code)
531{
532 drm_i830_private_t *dev_priv = dev->dev_private;
533 int i, j = 0;
534 unsigned int tmp;
535 RING_LOCALS;
536
537 if (code[I830_TEXREG_MI0] == GFX_OP_MAP_INFO ||
538 (code[I830_TEXREG_MI0] & ~(0xf * LOAD_TEXTURE_MAP0)) ==
539 (STATE3D_LOAD_STATE_IMMEDIATE_2 | 4)) {
540
541 BEGIN_LP_RING(I830_TEX_SETUP_SIZE);
542
543 OUT_RING(code[I830_TEXREG_MI0]);
544 OUT_RING(code[I830_TEXREG_MI1]);
545 OUT_RING(code[I830_TEXREG_MI2]);
546 OUT_RING(code[I830_TEXREG_MI3]);
547 OUT_RING(code[I830_TEXREG_MI4]);
548 OUT_RING(code[I830_TEXREG_MI5]);
549
550 for (i = 6; i < I830_TEX_SETUP_SIZE; i++) {
551 tmp = code[i];
552 OUT_RING(tmp);
553 j++;
554 }
555
556 if (j & 1)
557 OUT_RING(0);
558
559 ADVANCE_LP_RING();
560 } else
561 printk("rejected packet %x\n", code[0]);
562}
563
564static void i830EmitTexBlendVerified(struct drm_device *dev,
565 unsigned int *code, unsigned int num)
566{
567 drm_i830_private_t *dev_priv = dev->dev_private;
568 int i, j = 0;
569 unsigned int tmp;
570 RING_LOCALS;
571
572 if (!num)
573 return;
574
575 BEGIN_LP_RING(num + 1);
576
577 for (i = 0; i < num; i++) {
578 tmp = code[i];
579 OUT_RING(tmp);
580 j++;
581 }
582
583 if (j & 1)
584 OUT_RING(0);
585
586 ADVANCE_LP_RING();
587}
588
589static void i830EmitTexPalette(struct drm_device *dev,
590 unsigned int *palette, int number, int is_shared)
591{
592 drm_i830_private_t *dev_priv = dev->dev_private;
593 int i;
594 RING_LOCALS;
595
596 return;
597
598 BEGIN_LP_RING(258);
599
600 if (is_shared == 1) {
601 OUT_RING(CMD_OP_MAP_PALETTE_LOAD |
602 MAP_PALETTE_NUM(0) | MAP_PALETTE_BOTH);
603 } else {
604 OUT_RING(CMD_OP_MAP_PALETTE_LOAD | MAP_PALETTE_NUM(number));
605 }
606 for (i = 0; i < 256; i++)
607 OUT_RING(palette[i]);
608 OUT_RING(0);
609
610
611}
612
613
614
615static void i830EmitDestVerified(struct drm_device *dev, unsigned int *code)
616{
617 drm_i830_private_t *dev_priv = dev->dev_private;
618 unsigned int tmp;
619 RING_LOCALS;
620
621 BEGIN_LP_RING(I830_DEST_SETUP_SIZE + 10);
622
623 tmp = code[I830_DESTREG_CBUFADDR];
624 if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
625 if (((int)outring) & 8) {
626 OUT_RING(0);
627 OUT_RING(0);
628 }
629
630 OUT_RING(CMD_OP_DESTBUFFER_INFO);
631 OUT_RING(BUF_3D_ID_COLOR_BACK |
632 BUF_3D_PITCH(dev_priv->back_pitch * dev_priv->cpp) |
633 BUF_3D_USE_FENCE);
634 OUT_RING(tmp);
635 OUT_RING(0);
636
637 OUT_RING(CMD_OP_DESTBUFFER_INFO);
638 OUT_RING(BUF_3D_ID_DEPTH | BUF_3D_USE_FENCE |
639 BUF_3D_PITCH(dev_priv->depth_pitch * dev_priv->cpp));
640 OUT_RING(dev_priv->zi1);
641 OUT_RING(0);
642 } else {
643 DRM_ERROR("bad di1 %x (allow %x or %x)\n",
644 tmp, dev_priv->front_di1, dev_priv->back_di1);
645 }
646
647
648
649
650 OUT_RING(GFX_OP_DESTBUFFER_VARS);
651 OUT_RING(code[I830_DESTREG_DV1]);
652
653 OUT_RING(GFX_OP_DRAWRECT_INFO);
654 OUT_RING(code[I830_DESTREG_DR1]);
655 OUT_RING(code[I830_DESTREG_DR2]);
656 OUT_RING(code[I830_DESTREG_DR3]);
657 OUT_RING(code[I830_DESTREG_DR4]);
658
659
660 tmp = code[I830_DESTREG_SENABLE];
661 if ((tmp & ~0x3) == GFX_OP_SCISSOR_ENABLE) {
662 OUT_RING(tmp);
663 } else {
664 DRM_ERROR("bad scissor enable\n");
665 OUT_RING(0);
666 }
667
668 OUT_RING(GFX_OP_SCISSOR_RECT);
669 OUT_RING(code[I830_DESTREG_SR1]);
670 OUT_RING(code[I830_DESTREG_SR2]);
671 OUT_RING(0);
672
673 ADVANCE_LP_RING();
674}
675
676static void i830EmitStippleVerified(struct drm_device *dev, unsigned int *code)
677{
678 drm_i830_private_t *dev_priv = dev->dev_private;
679 RING_LOCALS;
680
681 BEGIN_LP_RING(2);
682 OUT_RING(GFX_OP_STIPPLE);
683 OUT_RING(code[1]);
684 ADVANCE_LP_RING();
685}
686
687static void i830EmitState(struct drm_device *dev)
688{
689 drm_i830_private_t *dev_priv = dev->dev_private;
690 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
691 unsigned int dirty = sarea_priv->dirty;
692
693 DRM_DEBUG("%s %x\n", __func__, dirty);
694
695 if (dirty & I830_UPLOAD_BUFFERS) {
696 i830EmitDestVerified(dev, sarea_priv->BufferState);
697 sarea_priv->dirty &= ~I830_UPLOAD_BUFFERS;
698 }
699
700 if (dirty & I830_UPLOAD_CTX) {
701 i830EmitContextVerified(dev, sarea_priv->ContextState);
702 sarea_priv->dirty &= ~I830_UPLOAD_CTX;
703 }
704
705 if (dirty & I830_UPLOAD_TEX0) {
706 i830EmitTexVerified(dev, sarea_priv->TexState[0]);
707 sarea_priv->dirty &= ~I830_UPLOAD_TEX0;
708 }
709
710 if (dirty & I830_UPLOAD_TEX1) {
711 i830EmitTexVerified(dev, sarea_priv->TexState[1]);
712 sarea_priv->dirty &= ~I830_UPLOAD_TEX1;
713 }
714
715 if (dirty & I830_UPLOAD_TEXBLEND0) {
716 i830EmitTexBlendVerified(dev, sarea_priv->TexBlendState[0],
717 sarea_priv->TexBlendStateWordsUsed[0]);
718 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND0;
719 }
720
721 if (dirty & I830_UPLOAD_TEXBLEND1) {
722 i830EmitTexBlendVerified(dev, sarea_priv->TexBlendState[1],
723 sarea_priv->TexBlendStateWordsUsed[1]);
724 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND1;
725 }
726
727 if (dirty & I830_UPLOAD_TEX_PALETTE_SHARED) {
728 i830EmitTexPalette(dev, sarea_priv->Palette[0], 0, 1);
729 } else {
730 if (dirty & I830_UPLOAD_TEX_PALETTE_N(0)) {
731 i830EmitTexPalette(dev, sarea_priv->Palette[0], 0, 0);
732 sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(0);
733 }
734 if (dirty & I830_UPLOAD_TEX_PALETTE_N(1)) {
735 i830EmitTexPalette(dev, sarea_priv->Palette[1], 1, 0);
736 sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(1);
737 }
738
739
740
741#if 0
742 if (dirty & I830_UPLOAD_TEX_PALETTE_N(2)) {
743 i830EmitTexPalette(dev, sarea_priv->Palette2[0], 0, 0);
744 sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(2);
745 }
746 if (dirty & I830_UPLOAD_TEX_PALETTE_N(3)) {
747 i830EmitTexPalette(dev, sarea_priv->Palette2[1], 1, 0);
748 sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(2);
749 }
750#endif
751 }
752
753
754
755 if (dirty & I830_UPLOAD_STIPPLE) {
756 i830EmitStippleVerified(dev, sarea_priv->StippleState);
757 sarea_priv->dirty &= ~I830_UPLOAD_STIPPLE;
758 }
759
760 if (dirty & I830_UPLOAD_TEX2) {
761 i830EmitTexVerified(dev, sarea_priv->TexState2);
762 sarea_priv->dirty &= ~I830_UPLOAD_TEX2;
763 }
764
765 if (dirty & I830_UPLOAD_TEX3) {
766 i830EmitTexVerified(dev, sarea_priv->TexState3);
767 sarea_priv->dirty &= ~I830_UPLOAD_TEX3;
768 }
769
770 if (dirty & I830_UPLOAD_TEXBLEND2) {
771 i830EmitTexBlendVerified(dev,
772 sarea_priv->TexBlendState2,
773 sarea_priv->TexBlendStateWordsUsed2);
774
775 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND2;
776 }
777
778 if (dirty & I830_UPLOAD_TEXBLEND3) {
779 i830EmitTexBlendVerified(dev,
780 sarea_priv->TexBlendState3,
781 sarea_priv->TexBlendStateWordsUsed3);
782 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND3;
783 }
784}
785
786
787
788
789
790static void i830_fill_box(struct drm_device *dev,
791 int x, int y, int w, int h, int r, int g, int b)
792{
793 drm_i830_private_t *dev_priv = dev->dev_private;
794 u32 color;
795 unsigned int BR13, CMD;
796 RING_LOCALS;
797
798 BR13 = (0xF0 << 16) | (dev_priv->pitch * dev_priv->cpp) | (1 << 24);
799 CMD = XY_COLOR_BLT_CMD;
800 x += dev_priv->sarea_priv->boxes[0].x1;
801 y += dev_priv->sarea_priv->boxes[0].y1;
802
803 if (dev_priv->cpp == 4) {
804 BR13 |= (1 << 25);
805 CMD |= (XY_COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB);
806 color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
807 } else {
808 color = (((r & 0xf8) << 8) |
809 ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
810 }
811
812 BEGIN_LP_RING(6);
813 OUT_RING(CMD);
814 OUT_RING(BR13);
815 OUT_RING((y << 16) | x);
816 OUT_RING(((y + h) << 16) | (x + w));
817
818 if (dev_priv->current_page == 1)
819 OUT_RING(dev_priv->front_offset);
820 else
821 OUT_RING(dev_priv->back_offset);
822
823 OUT_RING(color);
824 ADVANCE_LP_RING();
825}
826
827static void i830_cp_performance_boxes(struct drm_device *dev)
828{
829 drm_i830_private_t *dev_priv = dev->dev_private;
830
831
832
833 if (dev_priv->sarea_priv->perf_boxes & I830_BOX_FLIP)
834 i830_fill_box(dev, 4, 4, 8, 8, 255, 0, 255);
835
836
837
838 if (dev_priv->sarea_priv->perf_boxes & I830_BOX_WAIT)
839 i830_fill_box(dev, 16, 4, 8, 8, 255, 0, 0);
840
841
842
843 if (dev_priv->sarea_priv->perf_boxes & I830_BOX_LOST_CONTEXT)
844 i830_fill_box(dev, 28, 4, 8, 8, 0, 0, 255);
845
846
847
848 if (dev_priv->sarea_priv->perf_boxes & I830_BOX_TEXTURE_LOAD)
849 i830_fill_box(dev, 40, 4, 8, 8, 255, 255, 0);
850
851
852
853 if (!(dev_priv->sarea_priv->perf_boxes & I830_BOX_RING_EMPTY))
854 i830_fill_box(dev, 64, 4, 8, 8, 0, 255, 0);
855
856
857
858
859 if (dev_priv->dma_used) {
860 int bar = dev_priv->dma_used / 10240;
861 if (bar > 100)
862 bar = 100;
863 if (bar < 1)
864 bar = 1;
865 i830_fill_box(dev, 4, 16, bar, 4, 196, 128, 128);
866 dev_priv->dma_used = 0;
867 }
868
869 dev_priv->sarea_priv->perf_boxes = 0;
870}
871
872static void i830_dma_dispatch_clear(struct drm_device *dev, int flags,
873 unsigned int clear_color,
874 unsigned int clear_zval,
875 unsigned int clear_depthmask)
876{
877 drm_i830_private_t *dev_priv = dev->dev_private;
878 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
879 int nbox = sarea_priv->nbox;
880 struct drm_clip_rect *pbox = sarea_priv->boxes;
881 int pitch = dev_priv->pitch;
882 int cpp = dev_priv->cpp;
883 int i;
884 unsigned int BR13, CMD, D_CMD;
885 RING_LOCALS;
886
887 if (dev_priv->current_page == 1) {
888 unsigned int tmp = flags;
889
890 flags &= ~(I830_FRONT | I830_BACK);
891 if (tmp & I830_FRONT)
892 flags |= I830_BACK;
893 if (tmp & I830_BACK)
894 flags |= I830_FRONT;
895 }
896
897 i830_kernel_lost_context(dev);
898
899 switch (cpp) {
900 case 2:
901 BR13 = (0xF0 << 16) | (pitch * cpp) | (1 << 24);
902 D_CMD = CMD = XY_COLOR_BLT_CMD;
903 break;
904 case 4:
905 BR13 = (0xF0 << 16) | (pitch * cpp) | (1 << 24) | (1 << 25);
906 CMD = (XY_COLOR_BLT_CMD | XY_COLOR_BLT_WRITE_ALPHA |
907 XY_COLOR_BLT_WRITE_RGB);
908 D_CMD = XY_COLOR_BLT_CMD;
909 if (clear_depthmask & 0x00ffffff)
910 D_CMD |= XY_COLOR_BLT_WRITE_RGB;
911 if (clear_depthmask & 0xff000000)
912 D_CMD |= XY_COLOR_BLT_WRITE_ALPHA;
913 break;
914 default:
915 BR13 = (0xF0 << 16) | (pitch * cpp) | (1 << 24);
916 D_CMD = CMD = XY_COLOR_BLT_CMD;
917 break;
918 }
919
920 if (nbox > I830_NR_SAREA_CLIPRECTS)
921 nbox = I830_NR_SAREA_CLIPRECTS;
922
923 for (i = 0; i < nbox; i++, pbox++) {
924 if (pbox->x1 > pbox->x2 ||
925 pbox->y1 > pbox->y2 ||
926 pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
927 continue;
928
929 if (flags & I830_FRONT) {
930 DRM_DEBUG("clear front\n");
931 BEGIN_LP_RING(6);
932 OUT_RING(CMD);
933 OUT_RING(BR13);
934 OUT_RING((pbox->y1 << 16) | pbox->x1);
935 OUT_RING((pbox->y2 << 16) | pbox->x2);
936 OUT_RING(dev_priv->front_offset);
937 OUT_RING(clear_color);
938 ADVANCE_LP_RING();
939 }
940
941 if (flags & I830_BACK) {
942 DRM_DEBUG("clear back\n");
943 BEGIN_LP_RING(6);
944 OUT_RING(CMD);
945 OUT_RING(BR13);
946 OUT_RING((pbox->y1 << 16) | pbox->x1);
947 OUT_RING((pbox->y2 << 16) | pbox->x2);
948 OUT_RING(dev_priv->back_offset);
949 OUT_RING(clear_color);
950 ADVANCE_LP_RING();
951 }
952
953 if (flags & I830_DEPTH) {
954 DRM_DEBUG("clear depth\n");
955 BEGIN_LP_RING(6);
956 OUT_RING(D_CMD);
957 OUT_RING(BR13);
958 OUT_RING((pbox->y1 << 16) | pbox->x1);
959 OUT_RING((pbox->y2 << 16) | pbox->x2);
960 OUT_RING(dev_priv->depth_offset);
961 OUT_RING(clear_zval);
962 ADVANCE_LP_RING();
963 }
964 }
965}
966
967static void i830_dma_dispatch_swap(struct drm_device *dev)
968{
969 drm_i830_private_t *dev_priv = dev->dev_private;
970 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
971 int nbox = sarea_priv->nbox;
972 struct drm_clip_rect *pbox = sarea_priv->boxes;
973 int pitch = dev_priv->pitch;
974 int cpp = dev_priv->cpp;
975 int i;
976 unsigned int CMD, BR13;
977 RING_LOCALS;
978
979 DRM_DEBUG("swapbuffers\n");
980
981 i830_kernel_lost_context(dev);
982
983 if (dev_priv->do_boxes)
984 i830_cp_performance_boxes(dev);
985
986 switch (cpp) {
987 case 2:
988 BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24);
989 CMD = XY_SRC_COPY_BLT_CMD;
990 break;
991 case 4:
992 BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24) | (1 << 25);
993 CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA |
994 XY_SRC_COPY_BLT_WRITE_RGB);
995 break;
996 default:
997 BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24);
998 CMD = XY_SRC_COPY_BLT_CMD;
999 break;
1000 }
1001
1002 if (nbox > I830_NR_SAREA_CLIPRECTS)
1003 nbox = I830_NR_SAREA_CLIPRECTS;
1004
1005 for (i = 0; i < nbox; i++, pbox++) {
1006 if (pbox->x1 > pbox->x2 ||
1007 pbox->y1 > pbox->y2 ||
1008 pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
1009 continue;
1010
1011 DRM_DEBUG("dispatch swap %d,%d-%d,%d!\n",
1012 pbox->x1, pbox->y1, pbox->x2, pbox->y2);
1013
1014 BEGIN_LP_RING(8);
1015 OUT_RING(CMD);
1016 OUT_RING(BR13);
1017 OUT_RING((pbox->y1 << 16) | pbox->x1);
1018 OUT_RING((pbox->y2 << 16) | pbox->x2);
1019
1020 if (dev_priv->current_page == 0)
1021 OUT_RING(dev_priv->front_offset);
1022 else
1023 OUT_RING(dev_priv->back_offset);
1024
1025 OUT_RING((pbox->y1 << 16) | pbox->x1);
1026 OUT_RING(BR13 & 0xffff);
1027
1028 if (dev_priv->current_page == 0)
1029 OUT_RING(dev_priv->back_offset);
1030 else
1031 OUT_RING(dev_priv->front_offset);
1032
1033 ADVANCE_LP_RING();
1034 }
1035}
1036
1037static void i830_dma_dispatch_flip(struct drm_device *dev)
1038{
1039 drm_i830_private_t *dev_priv = dev->dev_private;
1040 RING_LOCALS;
1041
1042 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
1043 __func__,
1044 dev_priv->current_page,
1045 dev_priv->sarea_priv->pf_current_page);
1046
1047 i830_kernel_lost_context(dev);
1048
1049 if (dev_priv->do_boxes) {
1050 dev_priv->sarea_priv->perf_boxes |= I830_BOX_FLIP;
1051 i830_cp_performance_boxes(dev);
1052 }
1053
1054 BEGIN_LP_RING(2);
1055 OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
1056 OUT_RING(0);
1057 ADVANCE_LP_RING();
1058
1059 BEGIN_LP_RING(6);
1060 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
1061 OUT_RING(0);
1062 if (dev_priv->current_page == 0) {
1063 OUT_RING(dev_priv->back_offset);
1064 dev_priv->current_page = 1;
1065 } else {
1066 OUT_RING(dev_priv->front_offset);
1067 dev_priv->current_page = 0;
1068 }
1069 OUT_RING(0);
1070 ADVANCE_LP_RING();
1071
1072 BEGIN_LP_RING(2);
1073 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
1074 OUT_RING(0);
1075 ADVANCE_LP_RING();
1076
1077 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
1078}
1079
1080static void i830_dma_dispatch_vertex(struct drm_device *dev,
1081 struct drm_buf *buf, int discard, int used)
1082{
1083 drm_i830_private_t *dev_priv = dev->dev_private;
1084 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
1085 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
1086 struct drm_clip_rect *box = sarea_priv->boxes;
1087 int nbox = sarea_priv->nbox;
1088 unsigned long address = (unsigned long)buf->bus_address;
1089 unsigned long start = address - dev->agp->base;
1090 int i = 0, u;
1091 RING_LOCALS;
1092
1093 i830_kernel_lost_context(dev);
1094
1095 if (nbox > I830_NR_SAREA_CLIPRECTS)
1096 nbox = I830_NR_SAREA_CLIPRECTS;
1097
1098 if (discard) {
1099 u = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT,
1100 I830_BUF_HARDWARE);
1101 if (u != I830_BUF_CLIENT)
1102 DRM_DEBUG("xxxx 2\n");
1103 }
1104
1105 if (used > 4 * 1023)
1106 used = 0;
1107
1108 if (sarea_priv->dirty)
1109 i830EmitState(dev);
1110
1111 DRM_DEBUG("dispatch vertex addr 0x%lx, used 0x%x nbox %d\n",
1112 address, used, nbox);
1113
1114 dev_priv->counter++;
1115 DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter);
1116 DRM_DEBUG("i830_dma_dispatch\n");
1117 DRM_DEBUG("start : %lx\n", start);
1118 DRM_DEBUG("used : %d\n", used);
1119 DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4);
1120
1121 if (buf_priv->currently_mapped == I830_BUF_MAPPED) {
1122 u32 *vp = buf_priv->kernel_virtual;
1123
1124 vp[0] = (GFX_OP_PRIMITIVE |
1125 sarea_priv->vertex_prim | ((used / 4) - 2));
1126
1127 if (dev_priv->use_mi_batchbuffer_start) {
1128 vp[used / 4] = MI_BATCH_BUFFER_END;
1129 used += 4;
1130 }
1131
1132 if (used & 4) {
1133 vp[used / 4] = 0;
1134 used += 4;
1135 }
1136
1137 i830_unmap_buffer(buf);
1138 }
1139
1140 if (used) {
1141 do {
1142 if (i < nbox) {
1143 BEGIN_LP_RING(6);
1144 OUT_RING(GFX_OP_DRAWRECT_INFO);
1145 OUT_RING(sarea_priv->
1146 BufferState[I830_DESTREG_DR1]);
1147 OUT_RING(box[i].x1 | (box[i].y1 << 16));
1148 OUT_RING(box[i].x2 | (box[i].y2 << 16));
1149 OUT_RING(sarea_priv->
1150 BufferState[I830_DESTREG_DR4]);
1151 OUT_RING(0);
1152 ADVANCE_LP_RING();
1153 }
1154
1155 if (dev_priv->use_mi_batchbuffer_start) {
1156 BEGIN_LP_RING(2);
1157 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
1158 OUT_RING(start | MI_BATCH_NON_SECURE);
1159 ADVANCE_LP_RING();
1160 } else {
1161 BEGIN_LP_RING(4);
1162 OUT_RING(MI_BATCH_BUFFER);
1163 OUT_RING(start | MI_BATCH_NON_SECURE);
1164 OUT_RING(start + used - 4);
1165 OUT_RING(0);
1166 ADVANCE_LP_RING();
1167 }
1168
1169 } while (++i < nbox);
1170 }
1171
1172 if (discard) {
1173 dev_priv->counter++;
1174
1175 (void)cmpxchg(buf_priv->in_use, I830_BUF_CLIENT,
1176 I830_BUF_HARDWARE);
1177
1178 BEGIN_LP_RING(8);
1179 OUT_RING(CMD_STORE_DWORD_IDX);
1180 OUT_RING(20);
1181 OUT_RING(dev_priv->counter);
1182 OUT_RING(CMD_STORE_DWORD_IDX);
1183 OUT_RING(buf_priv->my_use_idx);
1184 OUT_RING(I830_BUF_FREE);
1185 OUT_RING(CMD_REPORT_HEAD);
1186 OUT_RING(0);
1187 ADVANCE_LP_RING();
1188 }
1189}
1190
1191static void i830_dma_quiescent(struct drm_device *dev)
1192{
1193 drm_i830_private_t *dev_priv = dev->dev_private;
1194 RING_LOCALS;
1195
1196 i830_kernel_lost_context(dev);
1197
1198 BEGIN_LP_RING(4);
1199 OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
1200 OUT_RING(CMD_REPORT_HEAD);
1201 OUT_RING(0);
1202 OUT_RING(0);
1203 ADVANCE_LP_RING();
1204
1205 i830_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
1206}
1207
1208static int i830_flush_queue(struct drm_device *dev)
1209{
1210 drm_i830_private_t *dev_priv = dev->dev_private;
1211 struct drm_device_dma *dma = dev->dma;
1212 int i, ret = 0;
1213 RING_LOCALS;
1214
1215 i830_kernel_lost_context(dev);
1216
1217 BEGIN_LP_RING(2);
1218 OUT_RING(CMD_REPORT_HEAD);
1219 OUT_RING(0);
1220 ADVANCE_LP_RING();
1221
1222 i830_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
1223
1224 for (i = 0; i < dma->buf_count; i++) {
1225 struct drm_buf *buf = dma->buflist[i];
1226 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
1227
1228 int used = cmpxchg(buf_priv->in_use, I830_BUF_HARDWARE,
1229 I830_BUF_FREE);
1230
1231 if (used == I830_BUF_HARDWARE)
1232 DRM_DEBUG("reclaimed from HARDWARE\n");
1233 if (used == I830_BUF_CLIENT)
1234 DRM_DEBUG("still on client\n");
1235 }
1236
1237 return ret;
1238}
1239
1240
1241static void i830_reclaim_buffers(struct drm_device *dev, struct drm_file *file_priv)
1242{
1243 struct drm_device_dma *dma = dev->dma;
1244 int i;
1245
1246 if (!dma)
1247 return;
1248 if (!dev->dev_private)
1249 return;
1250 if (!dma->buflist)
1251 return;
1252
1253 i830_flush_queue(dev);
1254
1255 for (i = 0; i < dma->buf_count; i++) {
1256 struct drm_buf *buf = dma->buflist[i];
1257 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
1258
1259 if (buf->file_priv == file_priv && buf_priv) {
1260 int used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT,
1261 I830_BUF_FREE);
1262
1263 if (used == I830_BUF_CLIENT)
1264 DRM_DEBUG("reclaimed from client\n");
1265 if (buf_priv->currently_mapped == I830_BUF_MAPPED)
1266 buf_priv->currently_mapped = I830_BUF_UNMAPPED;
1267 }
1268 }
1269}
1270
1271static int i830_flush_ioctl(struct drm_device *dev, void *data,
1272 struct drm_file *file_priv)
1273{
1274 LOCK_TEST_WITH_RETURN(dev, file_priv);
1275
1276 i830_flush_queue(dev);
1277 return 0;
1278}
1279
1280static int i830_dma_vertex(struct drm_device *dev, void *data,
1281 struct drm_file *file_priv)
1282{
1283 struct drm_device_dma *dma = dev->dma;
1284 drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
1285 u32 *hw_status = dev_priv->hw_status_page;
1286 drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *)
1287 dev_priv->sarea_priv;
1288 drm_i830_vertex_t *vertex = data;
1289
1290 LOCK_TEST_WITH_RETURN(dev, file_priv);
1291
1292 DRM_DEBUG("i830 dma vertex, idx %d used %d discard %d\n",
1293 vertex->idx, vertex->used, vertex->discard);
1294
1295 if (vertex->idx < 0 || vertex->idx > dma->buf_count)
1296 return -EINVAL;
1297
1298 i830_dma_dispatch_vertex(dev,
1299 dma->buflist[vertex->idx],
1300 vertex->discard, vertex->used);
1301
1302 sarea_priv->last_enqueue = dev_priv->counter - 1;
1303 sarea_priv->last_dispatch = (int)hw_status[5];
1304
1305 return 0;
1306}
1307
1308static int i830_clear_bufs(struct drm_device *dev, void *data,
1309 struct drm_file *file_priv)
1310{
1311 drm_i830_clear_t *clear = data;
1312
1313 LOCK_TEST_WITH_RETURN(dev, file_priv);
1314
1315
1316 if (!dev->dev_private)
1317 return -EINVAL;
1318
1319 i830_dma_dispatch_clear(dev, clear->flags,
1320 clear->clear_color,
1321 clear->clear_depth, clear->clear_depthmask);
1322 return 0;
1323}
1324
1325static int i830_swap_bufs(struct drm_device *dev, void *data,
1326 struct drm_file *file_priv)
1327{
1328 DRM_DEBUG("i830_swap_bufs\n");
1329
1330 LOCK_TEST_WITH_RETURN(dev, file_priv);
1331
1332 i830_dma_dispatch_swap(dev);
1333 return 0;
1334}
1335
1336
1337
1338static void i830_do_init_pageflip(struct drm_device *dev)
1339{
1340 drm_i830_private_t *dev_priv = dev->dev_private;
1341
1342 DRM_DEBUG("%s\n", __func__);
1343 dev_priv->page_flipping = 1;
1344 dev_priv->current_page = 0;
1345 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
1346}
1347
1348static int i830_do_cleanup_pageflip(struct drm_device *dev)
1349{
1350 drm_i830_private_t *dev_priv = dev->dev_private;
1351
1352 DRM_DEBUG("%s\n", __func__);
1353 if (dev_priv->current_page != 0)
1354 i830_dma_dispatch_flip(dev);
1355
1356 dev_priv->page_flipping = 0;
1357 return 0;
1358}
1359
1360static int i830_flip_bufs(struct drm_device *dev, void *data,
1361 struct drm_file *file_priv)
1362{
1363 drm_i830_private_t *dev_priv = dev->dev_private;
1364
1365 DRM_DEBUG("%s\n", __func__);
1366
1367 LOCK_TEST_WITH_RETURN(dev, file_priv);
1368
1369 if (!dev_priv->page_flipping)
1370 i830_do_init_pageflip(dev);
1371
1372 i830_dma_dispatch_flip(dev);
1373 return 0;
1374}
1375
1376static int i830_getage(struct drm_device *dev, void *data,
1377 struct drm_file *file_priv)
1378{
1379 drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
1380 u32 *hw_status = dev_priv->hw_status_page;
1381 drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *)
1382 dev_priv->sarea_priv;
1383
1384 sarea_priv->last_dispatch = (int)hw_status[5];
1385 return 0;
1386}
1387
1388static int i830_getbuf(struct drm_device *dev, void *data,
1389 struct drm_file *file_priv)
1390{
1391 int retcode = 0;
1392 drm_i830_dma_t *d = data;
1393 drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
1394 u32 *hw_status = dev_priv->hw_status_page;
1395 drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *)
1396 dev_priv->sarea_priv;
1397
1398 DRM_DEBUG("getbuf\n");
1399
1400 LOCK_TEST_WITH_RETURN(dev, file_priv);
1401
1402 d->granted = 0;
1403
1404 retcode = i830_dma_get_buffer(dev, d, file_priv);
1405
1406 DRM_DEBUG("i830_dma: %d returning %d, granted = %d\n",
1407 task_pid_nr(current), retcode, d->granted);
1408
1409 sarea_priv->last_dispatch = (int)hw_status[5];
1410
1411 return retcode;
1412}
1413
1414static int i830_copybuf(struct drm_device *dev, void *data,
1415 struct drm_file *file_priv)
1416{
1417
1418 return 0;
1419}
1420
1421static int i830_docopy(struct drm_device *dev, void *data,
1422 struct drm_file *file_priv)
1423{
1424 return 0;
1425}
1426
1427static int i830_getparam(struct drm_device *dev, void *data,
1428 struct drm_file *file_priv)
1429{
1430 drm_i830_private_t *dev_priv = dev->dev_private;
1431 drm_i830_getparam_t *param = data;
1432 int value;
1433
1434 if (!dev_priv) {
1435 DRM_ERROR("%s called with no initialization\n", __func__);
1436 return -EINVAL;
1437 }
1438
1439 switch (param->param) {
1440 case I830_PARAM_IRQ_ACTIVE:
1441 value = dev->irq_enabled;
1442 break;
1443 default:
1444 return -EINVAL;
1445 }
1446
1447 if (copy_to_user(param->value, &value, sizeof(int))) {
1448 DRM_ERROR("copy_to_user\n");
1449 return -EFAULT;
1450 }
1451
1452 return 0;
1453}
1454
1455static int i830_setparam(struct drm_device *dev, void *data,
1456 struct drm_file *file_priv)
1457{
1458 drm_i830_private_t *dev_priv = dev->dev_private;
1459 drm_i830_setparam_t *param = data;
1460
1461 if (!dev_priv) {
1462 DRM_ERROR("%s called with no initialization\n", __func__);
1463 return -EINVAL;
1464 }
1465
1466 switch (param->param) {
1467 case I830_SETPARAM_USE_MI_BATCHBUFFER_START:
1468 dev_priv->use_mi_batchbuffer_start = param->value;
1469 break;
1470 default:
1471 return -EINVAL;
1472 }
1473
1474 return 0;
1475}
1476
1477int i830_driver_load(struct drm_device *dev, unsigned long flags)
1478{
1479
1480 dev->counters += 4;
1481 dev->types[6] = _DRM_STAT_IRQ;
1482 dev->types[7] = _DRM_STAT_PRIMARY;
1483 dev->types[8] = _DRM_STAT_SECONDARY;
1484 dev->types[9] = _DRM_STAT_DMA;
1485
1486 return 0;
1487}
1488
1489void i830_driver_lastclose(struct drm_device *dev)
1490{
1491 i830_dma_cleanup(dev);
1492}
1493
1494void i830_driver_preclose(struct drm_device *dev, struct drm_file *file_priv)
1495{
1496 if (dev->dev_private) {
1497 drm_i830_private_t *dev_priv = dev->dev_private;
1498 if (dev_priv->page_flipping)
1499 i830_do_cleanup_pageflip(dev);
1500 }
1501}
1502
1503void i830_driver_reclaim_buffers_locked(struct drm_device *dev, struct drm_file *file_priv)
1504{
1505 i830_reclaim_buffers(dev, file_priv);
1506}
1507
1508int i830_driver_dma_quiescent(struct drm_device *dev)
1509{
1510 i830_dma_quiescent(dev);
1511 return 0;
1512}
1513
1514
1515
1516
1517
1518long i830_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1519{
1520 int ret;
1521 lock_kernel();
1522 ret = drm_ioctl(file, cmd, arg);
1523 unlock_kernel();
1524 return ret;
1525}
1526
1527struct drm_ioctl_desc i830_ioctls[] = {
1528 DRM_IOCTL_DEF_DRV(I830_INIT, i830_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1529 DRM_IOCTL_DEF_DRV(I830_VERTEX, i830_dma_vertex, DRM_AUTH|DRM_UNLOCKED),
1530 DRM_IOCTL_DEF_DRV(I830_CLEAR, i830_clear_bufs, DRM_AUTH|DRM_UNLOCKED),
1531 DRM_IOCTL_DEF_DRV(I830_FLUSH, i830_flush_ioctl, DRM_AUTH|DRM_UNLOCKED),
1532 DRM_IOCTL_DEF_DRV(I830_GETAGE, i830_getage, DRM_AUTH|DRM_UNLOCKED),
1533 DRM_IOCTL_DEF_DRV(I830_GETBUF, i830_getbuf, DRM_AUTH|DRM_UNLOCKED),
1534 DRM_IOCTL_DEF_DRV(I830_SWAP, i830_swap_bufs, DRM_AUTH|DRM_UNLOCKED),
1535 DRM_IOCTL_DEF_DRV(I830_COPY, i830_copybuf, DRM_AUTH|DRM_UNLOCKED),
1536 DRM_IOCTL_DEF_DRV(I830_DOCOPY, i830_docopy, DRM_AUTH|DRM_UNLOCKED),
1537 DRM_IOCTL_DEF_DRV(I830_FLIP, i830_flip_bufs, DRM_AUTH|DRM_UNLOCKED),
1538 DRM_IOCTL_DEF_DRV(I830_IRQ_EMIT, i830_irq_emit, DRM_AUTH|DRM_UNLOCKED),
1539 DRM_IOCTL_DEF_DRV(I830_IRQ_WAIT, i830_irq_wait, DRM_AUTH|DRM_UNLOCKED),
1540 DRM_IOCTL_DEF_DRV(I830_GETPARAM, i830_getparam, DRM_AUTH|DRM_UNLOCKED),
1541 DRM_IOCTL_DEF_DRV(I830_SETPARAM, i830_setparam, DRM_AUTH|DRM_UNLOCKED),
1542};
1543
1544int i830_max_ioctl = DRM_ARRAY_SIZE(i830_ioctls);
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557int i830_driver_device_is_agp(struct drm_device *dev)
1558{
1559 return 1;
1560}
1561
