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32#ifndef _I830_DRV_H_
33#define _I830_DRV_H_
34
35
36
37
38#define DRIVER_AUTHOR "VA Linux Systems Inc."
39
40#define DRIVER_NAME "i830"
41#define DRIVER_DESC "Intel 830M"
42#define DRIVER_DATE "20021108"
43
44
45
46
47
48
49
50
51
52
53
54#define DRIVER_MAJOR 1
55#define DRIVER_MINOR 3
56#define DRIVER_PATCHLEVEL 2
57
58
59
60
61
62
63#define USE_IRQS 0
64
65typedef struct drm_i830_buf_priv {
66 u32 *in_use;
67 int my_use_idx;
68 int currently_mapped;
69 void __user *virtual;
70 void *kernel_virtual;
71 drm_local_map_t map;
72} drm_i830_buf_priv_t;
73
74typedef struct _drm_i830_ring_buffer {
75 int tail_mask;
76 unsigned long Start;
77 unsigned long End;
78 unsigned long Size;
79 u8 *virtual_start;
80 int head;
81 int tail;
82 int space;
83 drm_local_map_t map;
84} drm_i830_ring_buffer_t;
85
86typedef struct drm_i830_private {
87 struct drm_local_map *sarea_map;
88 struct drm_local_map *mmio_map;
89
90 drm_i830_sarea_t *sarea_priv;
91 drm_i830_ring_buffer_t ring;
92
93 void *hw_status_page;
94 unsigned long counter;
95
96 dma_addr_t dma_status_page;
97
98 struct drm_buf *mmap_buffer;
99
100 u32 front_di1, back_di1, zi1;
101
102 int back_offset;
103 int depth_offset;
104 int front_offset;
105 int w, h;
106 int pitch;
107 int back_pitch;
108 int depth_pitch;
109 unsigned int cpp;
110
111 int do_boxes;
112 int dma_used;
113
114 int current_page;
115 int page_flipping;
116
117 wait_queue_head_t irq_queue;
118 atomic_t irq_received;
119 atomic_t irq_emitted;
120
121 int use_mi_batchbuffer_start;
122
123} drm_i830_private_t;
124
125long i830_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
126extern struct drm_ioctl_desc i830_ioctls[];
127extern int i830_max_ioctl;
128
129
130extern int i830_irq_emit(struct drm_device *dev, void *data,
131 struct drm_file *file_priv);
132extern int i830_irq_wait(struct drm_device *dev, void *data,
133 struct drm_file *file_priv);
134
135extern irqreturn_t i830_driver_irq_handler(DRM_IRQ_ARGS);
136extern void i830_driver_irq_preinstall(struct drm_device *dev);
137extern void i830_driver_irq_postinstall(struct drm_device *dev);
138extern void i830_driver_irq_uninstall(struct drm_device *dev);
139extern int i830_driver_load(struct drm_device *, unsigned long flags);
140extern void i830_driver_preclose(struct drm_device *dev,
141 struct drm_file *file_priv);
142extern void i830_driver_lastclose(struct drm_device *dev);
143extern void i830_driver_reclaim_buffers_locked(struct drm_device *dev,
144 struct drm_file *file_priv);
145extern int i830_driver_dma_quiescent(struct drm_device *dev);
146extern int i830_driver_device_is_agp(struct drm_device *dev);
147
148#define I830_READ(reg) DRM_READ32(dev_priv->mmio_map, reg)
149#define I830_WRITE(reg, val) DRM_WRITE32(dev_priv->mmio_map, reg, val)
150#define I830_READ16(reg) DRM_READ16(dev_priv->mmio_map, reg)
151#define I830_WRITE16(reg, val) DRM_WRITE16(dev_priv->mmio_map, reg, val)
152
153#define I830_VERBOSE 0
154
155#define RING_LOCALS unsigned int outring, ringmask, outcount; \
156 volatile char *virt;
157
158#define BEGIN_LP_RING(n) do { \
159 if (I830_VERBOSE) \
160 printk("BEGIN_LP_RING(%d)\n", (n)); \
161 if (dev_priv->ring.space < n*4) \
162 i830_wait_ring(dev, n*4, __func__); \
163 outcount = 0; \
164 outring = dev_priv->ring.tail; \
165 ringmask = dev_priv->ring.tail_mask; \
166 virt = dev_priv->ring.virtual_start; \
167} while (0)
168
169#define OUT_RING(n) do { \
170 if (I830_VERBOSE) \
171 printk(" OUT_RING %x\n", (int)(n)); \
172 *(volatile unsigned int *)(virt + outring) = n; \
173 outcount++; \
174 outring += 4; \
175 outring &= ringmask; \
176} while (0)
177
178#define ADVANCE_LP_RING() do { \
179 if (I830_VERBOSE) \
180 printk("ADVANCE_LP_RING %x\n", outring); \
181 dev_priv->ring.tail = outring; \
182 dev_priv->ring.space -= outcount * 4; \
183 I830_WRITE(LP_RING + RING_TAIL, outring); \
184} while (0)
185
186extern int i830_wait_ring(struct drm_device *dev, int n, const char *caller);
187
188#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
189#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
190#define CMD_REPORT_HEAD (7<<23)
191#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
192#define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
193
194#define STATE3D_LOAD_STATE_IMMEDIATE_2 ((0x3<<29)|(0x1d<<24)|(0x03<<16))
195#define LOAD_TEXTURE_MAP0 (1<<11)
196
197#define INST_PARSER_CLIENT 0x00000000
198#define INST_OP_FLUSH 0x02000000
199#define INST_FLUSH_MAP_CACHE 0x00000001
200
201#define BB1_START_ADDR_MASK (~0x7)
202#define BB1_PROTECTED (1<<0)
203#define BB1_UNPROTECTED (0<<0)
204#define BB2_END_ADDR_MASK (~0x7)
205
206#define I830REG_HWSTAM 0x02098
207#define I830REG_INT_IDENTITY_R 0x020a4
208#define I830REG_INT_MASK_R 0x020a8
209#define I830REG_INT_ENABLE_R 0x020a0
210
211#define I830_IRQ_RESERVED ((1<<13)|(3<<2))
212
213#define LP_RING 0x2030
214#define HP_RING 0x2040
215#define RING_TAIL 0x00
216#define TAIL_ADDR 0x001FFFF8
217#define RING_HEAD 0x04
218#define HEAD_WRAP_COUNT 0xFFE00000
219#define HEAD_WRAP_ONE 0x00200000
220#define HEAD_ADDR 0x001FFFFC
221#define RING_START 0x08
222#define START_ADDR 0x0xFFFFF000
223#define RING_LEN 0x0C
224#define RING_NR_PAGES 0x001FF000
225#define RING_REPORT_MASK 0x00000006
226#define RING_REPORT_64K 0x00000002
227#define RING_REPORT_128K 0x00000004
228#define RING_NO_REPORT 0x00000000
229#define RING_VALID_MASK 0x00000001
230#define RING_VALID 0x00000001
231#define RING_INVALID 0x00000000
232
233#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
234#define SC_UPDATE_SCISSOR (0x1<<1)
235#define SC_ENABLE_MASK (0x1<<0)
236#define SC_ENABLE (0x1<<0)
237
238#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
239#define SCI_YMIN_MASK (0xffff<<16)
240#define SCI_XMIN_MASK (0xffff<<0)
241#define SCI_YMAX_MASK (0xffff<<16)
242#define SCI_XMAX_MASK (0xffff<<0)
243
244#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
245#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
246#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
247#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
248#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
249#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
250#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
251#define GFX_OP_PRIMITIVE ((0x3<<29)|(0x1f<<24))
252
253#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
254
255#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
256#define ASYNC_FLIP (1<<22)
257
258#define CMD_3D (0x3<<29)
259#define STATE3D_CONST_BLEND_COLOR_CMD (CMD_3D|(0x1d<<24)|(0x88<<16))
260#define STATE3D_MAP_COORD_SETBIND_CMD (CMD_3D|(0x1d<<24)|(0x02<<16))
261
262#define BR00_BITBLT_CLIENT 0x40000000
263#define BR00_OP_COLOR_BLT 0x10000000
264#define BR00_OP_SRC_COPY_BLT 0x10C00000
265#define BR13_SOLID_PATTERN 0x80000000
266
267#define BUF_3D_ID_COLOR_BACK (0x3<<24)
268#define BUF_3D_ID_DEPTH (0x7<<24)
269#define BUF_3D_USE_FENCE (1<<23)
270#define BUF_3D_PITCH(x) (((x)/4)<<2)
271
272#define CMD_OP_MAP_PALETTE_LOAD ((3<<29)|(0x1d<<24)|(0x82<<16)|255)
273#define MAP_PALETTE_NUM(x) ((x<<8) & (1<<8))
274#define MAP_PALETTE_BOTH (1<<11)
275
276#define XY_COLOR_BLT_CMD ((2<<29)|(0x50<<22)|0x4)
277#define XY_COLOR_BLT_WRITE_ALPHA (1<<21)
278#define XY_COLOR_BLT_WRITE_RGB (1<<20)
279
280#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
281#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
282#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
283
284#define MI_BATCH_BUFFER ((0x30<<23)|1)
285#define MI_BATCH_BUFFER_START (0x31<<23)
286#define MI_BATCH_BUFFER_END (0xA<<23)
287#define MI_BATCH_NON_SECURE (1)
288
289#define MI_WAIT_FOR_EVENT ((0x3<<23))
290#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
291#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
292
293#define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
294
295#endif
296