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30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include "i915_reg.h"
34#include "intel_bios.h"
35#include "intel_ringbuffer.h"
36#include <linux/io-mapping.h>
37#include <linux/i2c.h>
38#include <drm/intel-gtt.h>
39
40
41
42
43#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
44
45#define DRIVER_NAME "i915"
46#define DRIVER_DESC "Intel Graphics"
47#define DRIVER_DATE "20080730"
48
49enum pipe {
50 PIPE_A = 0,
51 PIPE_B,
52};
53
54enum plane {
55 PLANE_A = 0,
56 PLANE_B,
57};
58
59#define I915_NUM_PIPE 2
60
61#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
62
63
64
65
66
67
68
69
70
71
72
73#define DRIVER_MAJOR 1
74#define DRIVER_MINOR 6
75#define DRIVER_PATCHLEVEL 0
76
77#define WATCH_COHERENCY 0
78#define WATCH_EXEC 0
79#define WATCH_RELOC 0
80#define WATCH_LISTS 0
81#define WATCH_PWRITE 0
82
83#define I915_GEM_PHYS_CURSOR_0 1
84#define I915_GEM_PHYS_CURSOR_1 2
85#define I915_GEM_PHYS_OVERLAY_REGS 3
86#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
87
88struct drm_i915_gem_phys_object {
89 int id;
90 struct page **page_list;
91 drm_dma_handle_t *handle;
92 struct drm_i915_gem_object *cur_obj;
93};
94
95struct mem_block {
96 struct mem_block *next;
97 struct mem_block *prev;
98 int start;
99 int size;
100 struct drm_file *file_priv;
101};
102
103struct opregion_header;
104struct opregion_acpi;
105struct opregion_swsci;
106struct opregion_asle;
107
108struct intel_opregion {
109 struct opregion_header *header;
110 struct opregion_acpi *acpi;
111 struct opregion_swsci *swsci;
112 struct opregion_asle *asle;
113 void *vbt;
114};
115#define OPREGION_SIZE (8*1024)
116
117struct intel_overlay;
118struct intel_overlay_error_state;
119
120struct drm_i915_master_private {
121 drm_local_map_t *sarea;
122 struct _drm_i915_sarea *sarea_priv;
123};
124#define I915_FENCE_REG_NONE -1
125
126struct drm_i915_fence_reg {
127 struct list_head lru_list;
128 struct drm_i915_gem_object *obj;
129 uint32_t setup_seqno;
130};
131
132struct sdvo_device_mapping {
133 u8 initialized;
134 u8 dvo_port;
135 u8 slave_addr;
136 u8 dvo_wiring;
137 u8 i2c_pin;
138 u8 i2c_speed;
139 u8 ddc_pin;
140};
141
142struct intel_display_error_state;
143
144struct drm_i915_error_state {
145 u32 eir;
146 u32 pgtbl_er;
147 u32 pipeastat;
148 u32 pipebstat;
149 u32 ipeir;
150 u32 ipehr;
151 u32 instdone;
152 u32 acthd;
153 u32 error;
154 u32 bcs_acthd;
155 u32 bcs_ipehr;
156 u32 bcs_ipeir;
157 u32 bcs_instdone;
158 u32 bcs_seqno;
159 u32 vcs_acthd;
160 u32 vcs_ipehr;
161 u32 vcs_ipeir;
162 u32 vcs_instdone;
163 u32 vcs_seqno;
164 u32 instpm;
165 u32 instps;
166 u32 instdone1;
167 u32 seqno;
168 u64 bbaddr;
169 u64 fence[16];
170 struct timeval time;
171 struct drm_i915_error_object {
172 int page_count;
173 u32 gtt_offset;
174 u32 *pages[0];
175 } *ringbuffer, *batchbuffer[I915_NUM_RINGS];
176 struct drm_i915_error_buffer {
177 u32 size;
178 u32 name;
179 u32 seqno;
180 u32 gtt_offset;
181 u32 read_domains;
182 u32 write_domain;
183 s32 fence_reg:5;
184 s32 pinned:2;
185 u32 tiling:2;
186 u32 dirty:1;
187 u32 purgeable:1;
188 u32 ring:4;
189 u32 agp_type:1;
190 } *active_bo, *pinned_bo;
191 u32 active_bo_count, pinned_bo_count;
192 struct intel_overlay_error_state *overlay;
193 struct intel_display_error_state *display;
194};
195
196struct drm_i915_display_funcs {
197 void (*dpms)(struct drm_crtc *crtc, int mode);
198 bool (*fbc_enabled)(struct drm_device *dev);
199 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
200 void (*disable_fbc)(struct drm_device *dev);
201 int (*get_display_clock_speed)(struct drm_device *dev);
202 int (*get_fifo_size)(struct drm_device *dev, int plane);
203 void (*update_wm)(struct drm_device *dev, int planea_clock,
204 int planeb_clock, int sr_hdisplay, int sr_htotal,
205 int pixel_size);
206
207
208
209
210
211
212};
213
214struct intel_device_info {
215 u8 gen;
216 u8 is_mobile : 1;
217 u8 is_i85x : 1;
218 u8 is_i915g : 1;
219 u8 is_i945gm : 1;
220 u8 is_g33 : 1;
221 u8 need_gfx_hws : 1;
222 u8 is_g4x : 1;
223 u8 is_pineview : 1;
224 u8 is_broadwater : 1;
225 u8 is_crestline : 1;
226 u8 has_fbc : 1;
227 u8 has_pipe_cxsr : 1;
228 u8 has_hotplug : 1;
229 u8 cursor_needs_physical : 1;
230 u8 has_overlay : 1;
231 u8 overlay_needs_physical : 1;
232 u8 supports_tv : 1;
233 u8 has_bsd_ring : 1;
234 u8 has_blt_ring : 1;
235};
236
237enum no_fbc_reason {
238 FBC_NO_OUTPUT,
239 FBC_STOLEN_TOO_SMALL,
240 FBC_UNSUPPORTED_MODE,
241 FBC_MODE_TOO_LARGE,
242 FBC_BAD_PLANE,
243 FBC_NOT_TILED,
244 FBC_MULTIPLE_PIPES,
245};
246
247enum intel_pch {
248 PCH_IBX,
249 PCH_CPT,
250};
251
252#define QUIRK_PIPEA_FORCE (1<<0)
253
254struct intel_fbdev;
255
256typedef struct drm_i915_private {
257 struct drm_device *dev;
258
259 const struct intel_device_info *info;
260
261 int has_gem;
262 int relative_constants_mode;
263
264 void __iomem *regs;
265
266 struct intel_gmbus {
267 struct i2c_adapter adapter;
268 struct i2c_adapter *force_bit;
269 u32 reg0;
270 } *gmbus;
271
272 struct pci_dev *bridge_dev;
273 struct intel_ring_buffer ring[I915_NUM_RINGS];
274 uint32_t next_seqno;
275
276 drm_dma_handle_t *status_page_dmah;
277 dma_addr_t dma_status_page;
278 uint32_t counter;
279 drm_local_map_t hws_map;
280 struct drm_i915_gem_object *pwrctx;
281 struct drm_i915_gem_object *renderctx;
282
283 struct resource mch_res;
284
285 unsigned int cpp;
286 int back_offset;
287 int front_offset;
288 int current_page;
289 int page_flipping;
290
291 atomic_t irq_received;
292 u32 trace_irq_seqno;
293
294
295 spinlock_t irq_lock;
296
297 u32 pipestat[2];
298 u32 irq_mask;
299 u32 gt_irq_mask;
300 u32 pch_irq_mask;
301
302 u32 hotplug_supported_mask;
303 struct work_struct hotplug_work;
304
305 int tex_lru_log_granularity;
306 int allow_batchbuffer;
307 struct mem_block *agp_heap;
308 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
309 int vblank_pipe;
310 int num_pipe;
311
312
313#define DRM_I915_HANGCHECK_PERIOD 1500
314 struct timer_list hangcheck_timer;
315 int hangcheck_count;
316 uint32_t last_acthd;
317 uint32_t last_instdone;
318 uint32_t last_instdone1;
319
320 unsigned long cfb_size;
321 unsigned long cfb_pitch;
322 unsigned long cfb_offset;
323 int cfb_fence;
324 int cfb_plane;
325 int cfb_y;
326
327 int irq_enabled;
328
329 struct intel_opregion opregion;
330
331
332 struct intel_overlay *overlay;
333
334
335 int backlight_level;
336 bool backlight_enabled;
337 struct drm_display_mode *panel_fixed_mode;
338 struct drm_display_mode *lfp_lvds_vbt_mode;
339 struct drm_display_mode *sdvo_lvds_vbt_mode;
340
341
342 unsigned int int_tv_support:1;
343 unsigned int lvds_dither:1;
344 unsigned int lvds_vbt:1;
345 unsigned int int_crt_support:1;
346 unsigned int lvds_use_ssc:1;
347 int lvds_ssc_freq;
348 struct {
349 int rate;
350 int lanes;
351 int preemphasis;
352 int vswing;
353
354 bool initialized;
355 bool support;
356 int bpp;
357 struct edp_power_seq pps;
358 } edp;
359 bool no_aux_handshake;
360
361 struct notifier_block lid_notifier;
362
363 int crt_ddc_pin;
364 struct drm_i915_fence_reg fence_regs[16];
365 int fence_reg_start;
366 int num_fence_regs;
367
368 unsigned int fsb_freq, mem_freq, is_ddr3;
369
370 spinlock_t error_lock;
371 struct drm_i915_error_state *first_error;
372 struct work_struct error_work;
373 struct completion error_completion;
374 struct workqueue_struct *wq;
375
376
377 struct drm_i915_display_funcs display;
378
379
380 enum intel_pch pch_type;
381
382 unsigned long quirks;
383
384
385 bool modeset_on_lid;
386 u8 saveLBB;
387 u32 saveDSPACNTR;
388 u32 saveDSPBCNTR;
389 u32 saveDSPARB;
390 u32 saveHWS;
391 u32 savePIPEACONF;
392 u32 savePIPEBCONF;
393 u32 savePIPEASRC;
394 u32 savePIPEBSRC;
395 u32 saveFPA0;
396 u32 saveFPA1;
397 u32 saveDPLL_A;
398 u32 saveDPLL_A_MD;
399 u32 saveHTOTAL_A;
400 u32 saveHBLANK_A;
401 u32 saveHSYNC_A;
402 u32 saveVTOTAL_A;
403 u32 saveVBLANK_A;
404 u32 saveVSYNC_A;
405 u32 saveBCLRPAT_A;
406 u32 saveTRANSACONF;
407 u32 saveTRANS_HTOTAL_A;
408 u32 saveTRANS_HBLANK_A;
409 u32 saveTRANS_HSYNC_A;
410 u32 saveTRANS_VTOTAL_A;
411 u32 saveTRANS_VBLANK_A;
412 u32 saveTRANS_VSYNC_A;
413 u32 savePIPEASTAT;
414 u32 saveDSPASTRIDE;
415 u32 saveDSPASIZE;
416 u32 saveDSPAPOS;
417 u32 saveDSPAADDR;
418 u32 saveDSPASURF;
419 u32 saveDSPATILEOFF;
420 u32 savePFIT_PGM_RATIOS;
421 u32 saveBLC_HIST_CTL;
422 u32 saveBLC_PWM_CTL;
423 u32 saveBLC_PWM_CTL2;
424 u32 saveBLC_CPU_PWM_CTL;
425 u32 saveBLC_CPU_PWM_CTL2;
426 u32 saveFPB0;
427 u32 saveFPB1;
428 u32 saveDPLL_B;
429 u32 saveDPLL_B_MD;
430 u32 saveHTOTAL_B;
431 u32 saveHBLANK_B;
432 u32 saveHSYNC_B;
433 u32 saveVTOTAL_B;
434 u32 saveVBLANK_B;
435 u32 saveVSYNC_B;
436 u32 saveBCLRPAT_B;
437 u32 saveTRANSBCONF;
438 u32 saveTRANS_HTOTAL_B;
439 u32 saveTRANS_HBLANK_B;
440 u32 saveTRANS_HSYNC_B;
441 u32 saveTRANS_VTOTAL_B;
442 u32 saveTRANS_VBLANK_B;
443 u32 saveTRANS_VSYNC_B;
444 u32 savePIPEBSTAT;
445 u32 saveDSPBSTRIDE;
446 u32 saveDSPBSIZE;
447 u32 saveDSPBPOS;
448 u32 saveDSPBADDR;
449 u32 saveDSPBSURF;
450 u32 saveDSPBTILEOFF;
451 u32 saveVGA0;
452 u32 saveVGA1;
453 u32 saveVGA_PD;
454 u32 saveVGACNTRL;
455 u32 saveADPA;
456 u32 saveLVDS;
457 u32 savePP_ON_DELAYS;
458 u32 savePP_OFF_DELAYS;
459 u32 saveDVOA;
460 u32 saveDVOB;
461 u32 saveDVOC;
462 u32 savePP_ON;
463 u32 savePP_OFF;
464 u32 savePP_CONTROL;
465 u32 savePP_DIVISOR;
466 u32 savePFIT_CONTROL;
467 u32 save_palette_a[256];
468 u32 save_palette_b[256];
469 u32 saveDPFC_CB_BASE;
470 u32 saveFBC_CFB_BASE;
471 u32 saveFBC_LL_BASE;
472 u32 saveFBC_CONTROL;
473 u32 saveFBC_CONTROL2;
474 u32 saveIER;
475 u32 saveIIR;
476 u32 saveIMR;
477 u32 saveDEIER;
478 u32 saveDEIMR;
479 u32 saveGTIER;
480 u32 saveGTIMR;
481 u32 saveFDI_RXA_IMR;
482 u32 saveFDI_RXB_IMR;
483 u32 saveCACHE_MODE_0;
484 u32 saveMI_ARB_STATE;
485 u32 saveSWF0[16];
486 u32 saveSWF1[16];
487 u32 saveSWF2[3];
488 u8 saveMSR;
489 u8 saveSR[8];
490 u8 saveGR[25];
491 u8 saveAR_INDEX;
492 u8 saveAR[21];
493 u8 saveDACMASK;
494 u8 saveCR[37];
495 uint64_t saveFENCE[16];
496 u32 saveCURACNTR;
497 u32 saveCURAPOS;
498 u32 saveCURABASE;
499 u32 saveCURBCNTR;
500 u32 saveCURBPOS;
501 u32 saveCURBBASE;
502 u32 saveCURSIZE;
503 u32 saveDP_B;
504 u32 saveDP_C;
505 u32 saveDP_D;
506 u32 savePIPEA_GMCH_DATA_M;
507 u32 savePIPEB_GMCH_DATA_M;
508 u32 savePIPEA_GMCH_DATA_N;
509 u32 savePIPEB_GMCH_DATA_N;
510 u32 savePIPEA_DP_LINK_M;
511 u32 savePIPEB_DP_LINK_M;
512 u32 savePIPEA_DP_LINK_N;
513 u32 savePIPEB_DP_LINK_N;
514 u32 saveFDI_RXA_CTL;
515 u32 saveFDI_TXA_CTL;
516 u32 saveFDI_RXB_CTL;
517 u32 saveFDI_TXB_CTL;
518 u32 savePFA_CTL_1;
519 u32 savePFB_CTL_1;
520 u32 savePFA_WIN_SZ;
521 u32 savePFB_WIN_SZ;
522 u32 savePFA_WIN_POS;
523 u32 savePFB_WIN_POS;
524 u32 savePCH_DREF_CONTROL;
525 u32 saveDISP_ARB_CTL;
526 u32 savePIPEA_DATA_M1;
527 u32 savePIPEA_DATA_N1;
528 u32 savePIPEA_LINK_M1;
529 u32 savePIPEA_LINK_N1;
530 u32 savePIPEB_DATA_M1;
531 u32 savePIPEB_DATA_N1;
532 u32 savePIPEB_LINK_M1;
533 u32 savePIPEB_LINK_N1;
534 u32 saveMCHBAR_RENDER_STANDBY;
535
536 struct {
537
538 const struct intel_gtt *gtt;
539
540 struct drm_mm stolen;
541
542 struct drm_mm gtt_space;
543
544
545 struct list_head gtt_list;
546
547
548 unsigned long gtt_start;
549 unsigned long gtt_mappable_end;
550 unsigned long gtt_end;
551
552 struct io_mapping *gtt_mapping;
553 int gtt_mtrr;
554
555 struct shrinker inactive_shrinker;
556
557
558
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561
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563
564
565
566 struct list_head active_list;
567
568
569
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575
576
577 struct list_head flushing_list;
578
579
580
581
582
583
584
585
586
587
588
589 struct list_head inactive_list;
590
591
592
593
594
595 struct list_head pinned_list;
596
597
598 struct list_head fence_list;
599
600
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603
604
605
606 struct list_head deferred_free_list;
607
608
609
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611
612
613
614
615 struct delayed_work retire_work;
616
617
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619
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621
622
623
624
625 int suspended;
626
627
628
629
630
631
632
633
634 atomic_t wedged;
635
636
637 uint32_t bit_6_swizzle_x;
638
639 uint32_t bit_6_swizzle_y;
640
641
642 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
643
644
645 size_t gtt_total;
646 size_t mappable_gtt_total;
647 size_t object_memory;
648 u32 object_count;
649 } mm;
650 struct sdvo_device_mapping sdvo_mappings[2];
651
652 unsigned int lvds_border_bits;
653
654 u32 pch_pf_pos, pch_pf_size;
655
656 struct drm_crtc *plane_to_crtc_mapping[2];
657 struct drm_crtc *pipe_to_crtc_mapping[2];
658 wait_queue_head_t pending_flip_queue;
659 bool flip_pending_is_done;
660
661
662 bool render_reclock_avail;
663 bool lvds_downclock_avail;
664
665 int lvds_downclock;
666 struct work_struct idle_work;
667 struct timer_list idle_timer;
668 bool busy;
669 u16 orig_clock;
670 int child_dev_num;
671 struct child_device_config *child_dev;
672 struct drm_connector *int_lvds_connector;
673
674 bool mchbar_need_disable;
675
676 u8 cur_delay;
677 u8 min_delay;
678 u8 max_delay;
679 u8 fmax;
680 u8 fstart;
681
682 u64 last_count1;
683 unsigned long last_time1;
684 u64 last_count2;
685 struct timespec last_time2;
686 unsigned long gfx_power;
687 int c_m;
688 int r_t;
689 u8 corr;
690 spinlock_t *mchdev_lock;
691
692 enum no_fbc_reason no_fbc_reason;
693
694 struct drm_mm_node *compressed_fb;
695 struct drm_mm_node *compressed_llb;
696
697 unsigned long last_gpu_reset;
698
699
700 struct intel_fbdev *fbdev;
701} drm_i915_private_t;
702
703struct drm_i915_gem_object {
704 struct drm_gem_object base;
705
706
707 struct drm_mm_node *gtt_space;
708 struct list_head gtt_list;
709
710
711 struct list_head ring_list;
712 struct list_head mm_list;
713
714 struct list_head gpu_write_list;
715
716 struct list_head exec_list;
717
718
719
720
721
722
723 unsigned int active : 1;
724
725
726
727
728
729 unsigned int dirty : 1;
730
731
732
733
734
735 unsigned int pending_gpu_write : 1;
736
737
738
739
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741
742
743
744 signed int fence_reg : 5;
745
746
747
748
749 unsigned int madv : 2;
750
751
752
753
754 unsigned int tiling_mode : 2;
755 unsigned int tiling_changed : 1;
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757
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764
765
766 unsigned int pin_count : 4;
767#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
768
769
770
771
772
773 unsigned int map_and_fenceable : 1;
774
775
776
777
778
779
780 unsigned int fault_mappable : 1;
781 unsigned int pin_mappable : 1;
782
783
784
785
786 unsigned int pending_fenced_gpu_access:1;
787 unsigned int fenced_gpu_access:1;
788
789 struct page **pages;
790
791
792
793
794 struct scatterlist *sg_list;
795 int num_sg;
796
797
798
799
800 struct hlist_node exec_node;
801 unsigned long exec_handle;
802 struct drm_i915_gem_exec_object2 *exec_entry;
803
804
805
806
807
808
809 uint32_t gtt_offset;
810
811
812 uint32_t last_rendering_seqno;
813 struct intel_ring_buffer *ring;
814
815
816 uint32_t last_fenced_seqno;
817 struct intel_ring_buffer *last_fenced_ring;
818
819
820 uint32_t stride;
821
822
823 unsigned long *bit_17;
824
825
826 uint32_t agp_type;
827
828
829
830
831
832 uint8_t *page_cpu_valid;
833
834
835 uint32_t user_pin_count;
836 struct drm_file *pin_filp;
837
838
839 struct drm_i915_gem_phys_object *phys_obj;
840
841
842
843
844
845
846 atomic_t pending_flip;
847};
848
849#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
850
851
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855
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857
858
859
860
861struct drm_i915_gem_request {
862
863 struct intel_ring_buffer *ring;
864
865
866 uint32_t seqno;
867
868
869 unsigned long emitted_jiffies;
870
871
872 struct list_head list;
873
874 struct drm_i915_file_private *file_priv;
875
876 struct list_head client_list;
877};
878
879struct drm_i915_file_private {
880 struct {
881 struct spinlock lock;
882 struct list_head request_list;
883 } mm;
884};
885
886enum intel_chip_family {
887 CHIP_I8XX = 0x01,
888 CHIP_I9XX = 0x02,
889 CHIP_I915 = 0x04,
890 CHIP_I965 = 0x08,
891};
892
893#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
894
895#define IS_I830(dev) ((dev)->pci_device == 0x3577)
896#define IS_845G(dev) ((dev)->pci_device == 0x2562)
897#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
898#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
899#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
900#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
901#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
902#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
903#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
904#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
905#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
906#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
907#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
908#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
909#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
910#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
911#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
912#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
913#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
914
915#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
916#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
917#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
918#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
919#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
920
921#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
922#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
923#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
924
925#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
926#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
927
928
929
930
931#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
932 IS_I915GM(dev)))
933#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
934#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
935#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
936#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
937#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
938#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
939
940#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
941
942#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
943#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
944#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
945
946#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
947#define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
948
949#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
950#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
951#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
952
953#include "i915_trace.h"
954
955extern struct drm_ioctl_desc i915_ioctls[];
956extern int i915_max_ioctl;
957extern unsigned int i915_fbpercrtc;
958extern unsigned int i915_powersave;
959extern unsigned int i915_semaphores;
960extern unsigned int i915_lvds_downclock;
961extern unsigned int i915_panel_use_ssc;
962extern unsigned int i915_enable_rc6;
963
964extern int i915_suspend(struct drm_device *dev, pm_message_t state);
965extern int i915_resume(struct drm_device *dev);
966extern void i915_save_display(struct drm_device *dev);
967extern void i915_restore_display(struct drm_device *dev);
968extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
969extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
970
971
972extern void i915_kernel_lost_context(struct drm_device * dev);
973extern int i915_driver_load(struct drm_device *, unsigned long flags);
974extern int i915_driver_unload(struct drm_device *);
975extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
976extern void i915_driver_lastclose(struct drm_device * dev);
977extern void i915_driver_preclose(struct drm_device *dev,
978 struct drm_file *file_priv);
979extern void i915_driver_postclose(struct drm_device *dev,
980 struct drm_file *file_priv);
981extern int i915_driver_device_is_agp(struct drm_device * dev);
982extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
983 unsigned long arg);
984extern int i915_emit_box(struct drm_device *dev,
985 struct drm_clip_rect *box,
986 int DR1, int DR4);
987extern int i915_reset(struct drm_device *dev, u8 flags);
988extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
989extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
990extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
991extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
992
993
994
995void i915_hangcheck_elapsed(unsigned long data);
996void i915_handle_error(struct drm_device *dev, bool wedged);
997extern int i915_irq_emit(struct drm_device *dev, void *data,
998 struct drm_file *file_priv);
999extern int i915_irq_wait(struct drm_device *dev, void *data,
1000 struct drm_file *file_priv);
1001void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
1002extern void i915_enable_interrupt (struct drm_device *dev);
1003
1004extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
1005extern void i915_driver_irq_preinstall(struct drm_device * dev);
1006extern int i915_driver_irq_postinstall(struct drm_device *dev);
1007extern void i915_driver_irq_uninstall(struct drm_device * dev);
1008extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1009 struct drm_file *file_priv);
1010extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1011 struct drm_file *file_priv);
1012extern int i915_enable_vblank(struct drm_device *dev, int crtc);
1013extern void i915_disable_vblank(struct drm_device *dev, int crtc);
1014extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
1015extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
1016extern int i915_vblank_swap(struct drm_device *dev, void *data,
1017 struct drm_file *file_priv);
1018
1019void
1020i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1021
1022void
1023i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1024
1025void intel_enable_asle (struct drm_device *dev);
1026int i915_get_vblank_timestamp(struct drm_device *dev, int crtc,
1027 int *max_error,
1028 struct timeval *vblank_time,
1029 unsigned flags);
1030
1031int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
1032 int *vpos, int *hpos);
1033
1034#ifdef CONFIG_DEBUG_FS
1035extern void i915_destroy_error_state(struct drm_device *dev);
1036#else
1037#define i915_destroy_error_state(x)
1038#endif
1039
1040
1041
1042extern int i915_mem_alloc(struct drm_device *dev, void *data,
1043 struct drm_file *file_priv);
1044extern int i915_mem_free(struct drm_device *dev, void *data,
1045 struct drm_file *file_priv);
1046extern int i915_mem_init_heap(struct drm_device *dev, void *data,
1047 struct drm_file *file_priv);
1048extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
1049 struct drm_file *file_priv);
1050extern void i915_mem_takedown(struct mem_block **heap);
1051extern void i915_mem_release(struct drm_device * dev,
1052 struct drm_file *file_priv, struct mem_block *heap);
1053
1054int i915_gem_check_is_wedged(struct drm_device *dev);
1055int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1056 struct drm_file *file_priv);
1057int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1058 struct drm_file *file_priv);
1059int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1060 struct drm_file *file_priv);
1061int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1062 struct drm_file *file_priv);
1063int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1064 struct drm_file *file_priv);
1065int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1066 struct drm_file *file_priv);
1067int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1068 struct drm_file *file_priv);
1069int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1070 struct drm_file *file_priv);
1071int i915_gem_execbuffer(struct drm_device *dev, void *data,
1072 struct drm_file *file_priv);
1073int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1074 struct drm_file *file_priv);
1075int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1076 struct drm_file *file_priv);
1077int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1078 struct drm_file *file_priv);
1079int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1080 struct drm_file *file_priv);
1081int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1082 struct drm_file *file_priv);
1083int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1084 struct drm_file *file_priv);
1085int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1086 struct drm_file *file_priv);
1087int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1088 struct drm_file *file_priv);
1089int i915_gem_set_tiling(struct drm_device *dev, void *data,
1090 struct drm_file *file_priv);
1091int i915_gem_get_tiling(struct drm_device *dev, void *data,
1092 struct drm_file *file_priv);
1093int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1094 struct drm_file *file_priv);
1095void i915_gem_load(struct drm_device *dev);
1096int i915_gem_init_object(struct drm_gem_object *obj);
1097int __must_check i915_gem_flush_ring(struct drm_device *dev,
1098 struct intel_ring_buffer *ring,
1099 uint32_t invalidate_domains,
1100 uint32_t flush_domains);
1101struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1102 size_t size);
1103void i915_gem_free_object(struct drm_gem_object *obj);
1104int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1105 uint32_t alignment,
1106 bool map_and_fenceable);
1107void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1108int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1109void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1110void i915_gem_lastclose(struct drm_device *dev);
1111
1112int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1113int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1114 bool interruptible);
1115void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1116 struct intel_ring_buffer *ring,
1117 u32 seqno);
1118
1119
1120
1121
1122static inline bool
1123i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1124{
1125 return (int32_t)(seq1 - seq2) >= 0;
1126}
1127
1128static inline u32
1129i915_gem_next_request_seqno(struct drm_device *dev,
1130 struct intel_ring_buffer *ring)
1131{
1132 drm_i915_private_t *dev_priv = dev->dev_private;
1133 return ring->outstanding_lazy_request = dev_priv->next_seqno;
1134}
1135
1136int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
1137 struct intel_ring_buffer *pipelined,
1138 bool interruptible);
1139int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1140
1141void i915_gem_retire_requests(struct drm_device *dev);
1142void i915_gem_reset(struct drm_device *dev);
1143void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1144int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1145 uint32_t read_domains,
1146 uint32_t write_domain);
1147int __must_check i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj,
1148 bool interruptible);
1149int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);
1150void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1151void i915_gem_do_init(struct drm_device *dev,
1152 unsigned long start,
1153 unsigned long mappable_end,
1154 unsigned long end);
1155int __must_check i915_gpu_idle(struct drm_device *dev);
1156int __must_check i915_gem_idle(struct drm_device *dev);
1157int __must_check i915_add_request(struct drm_device *dev,
1158 struct drm_file *file_priv,
1159 struct drm_i915_gem_request *request,
1160 struct intel_ring_buffer *ring);
1161int __must_check i915_do_wait_request(struct drm_device *dev,
1162 uint32_t seqno,
1163 bool interruptible,
1164 struct intel_ring_buffer *ring);
1165int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1166int __must_check
1167i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1168 bool write);
1169int __must_check
1170i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
1171 struct intel_ring_buffer *pipelined);
1172int i915_gem_attach_phys_object(struct drm_device *dev,
1173 struct drm_i915_gem_object *obj,
1174 int id,
1175 int align);
1176void i915_gem_detach_phys_object(struct drm_device *dev,
1177 struct drm_i915_gem_object *obj);
1178void i915_gem_free_all_phys_object(struct drm_device *dev);
1179void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1180
1181uint32_t
1182i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj);
1183
1184
1185void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1186int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
1187void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1188
1189
1190int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1191 unsigned alignment, bool mappable);
1192int __must_check i915_gem_evict_everything(struct drm_device *dev,
1193 bool purgeable_only);
1194int __must_check i915_gem_evict_inactive(struct drm_device *dev,
1195 bool purgeable_only);
1196
1197
1198void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1199void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1200void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1201
1202
1203void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1204 const char *where, uint32_t mark);
1205#if WATCH_LISTS
1206int i915_verify_lists(struct drm_device *dev);
1207#else
1208#define i915_verify_lists(dev) 0
1209#endif
1210void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1211 int handle);
1212void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1213 const char *where, uint32_t mark);
1214
1215
1216int i915_debugfs_init(struct drm_minor *minor);
1217void i915_debugfs_cleanup(struct drm_minor *minor);
1218
1219
1220extern int i915_save_state(struct drm_device *dev);
1221extern int i915_restore_state(struct drm_device *dev);
1222
1223
1224extern int i915_save_state(struct drm_device *dev);
1225extern int i915_restore_state(struct drm_device *dev);
1226
1227
1228extern int intel_setup_gmbus(struct drm_device *dev);
1229extern void intel_teardown_gmbus(struct drm_device *dev);
1230extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1231extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1232extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1233{
1234 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1235}
1236extern void intel_i2c_reset(struct drm_device *dev);
1237
1238
1239extern int intel_opregion_setup(struct drm_device *dev);
1240#ifdef CONFIG_ACPI
1241extern void intel_opregion_init(struct drm_device *dev);
1242extern void intel_opregion_fini(struct drm_device *dev);
1243extern void intel_opregion_asle_intr(struct drm_device *dev);
1244extern void intel_opregion_gse_intr(struct drm_device *dev);
1245extern void intel_opregion_enable_asle(struct drm_device *dev);
1246#else
1247static inline void intel_opregion_init(struct drm_device *dev) { return; }
1248static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1249static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1250static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1251static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1252#endif
1253
1254
1255#ifdef CONFIG_ACPI
1256extern void intel_register_dsm_handler(void);
1257extern void intel_unregister_dsm_handler(void);
1258#else
1259static inline void intel_register_dsm_handler(void) { return; }
1260static inline void intel_unregister_dsm_handler(void) { return; }
1261#endif
1262
1263
1264extern void intel_modeset_init(struct drm_device *dev);
1265extern void intel_modeset_cleanup(struct drm_device *dev);
1266extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1267extern void i8xx_disable_fbc(struct drm_device *dev);
1268extern void g4x_disable_fbc(struct drm_device *dev);
1269extern void ironlake_disable_fbc(struct drm_device *dev);
1270extern void intel_disable_fbc(struct drm_device *dev);
1271extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
1272extern bool intel_fbc_enabled(struct drm_device *dev);
1273extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1274extern void ironlake_enable_rc6(struct drm_device *dev);
1275extern void gen6_set_rps(struct drm_device *dev, u8 val);
1276extern void intel_detect_pch (struct drm_device *dev);
1277extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1278
1279
1280#ifdef CONFIG_DEBUG_FS
1281extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1282extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1283
1284extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1285extern void intel_display_print_error_state(struct seq_file *m,
1286 struct drm_device *dev,
1287 struct intel_display_error_state *error);
1288#endif
1289
1290#define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1291
1292#define BEGIN_LP_RING(n) \
1293 intel_ring_begin(LP_RING(dev_priv), (n))
1294
1295#define OUT_RING(x) \
1296 intel_ring_emit(LP_RING(dev_priv), x)
1297
1298#define ADVANCE_LP_RING() \
1299 intel_ring_advance(LP_RING(dev_priv))
1300
1301
1302
1303
1304
1305
1306
1307#define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
1308 if (LP_RING(dev->dev_private)->obj == NULL) \
1309 LOCK_TEST_WITH_RETURN(dev, file); \
1310} while (0)
1311
1312
1313#define __i915_read(x, y) \
1314static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1315 u##x val = read##y(dev_priv->regs + reg); \
1316 trace_i915_reg_rw('R', reg, val, sizeof(val)); \
1317 return val; \
1318}
1319__i915_read(8, b)
1320__i915_read(16, w)
1321__i915_read(32, l)
1322__i915_read(64, q)
1323#undef __i915_read
1324
1325#define __i915_write(x, y) \
1326static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1327 trace_i915_reg_rw('W', reg, val, sizeof(val)); \
1328 write##y(val, dev_priv->regs + reg); \
1329}
1330__i915_write(8, b)
1331__i915_write(16, w)
1332__i915_write(32, l)
1333__i915_write(64, q)
1334#undef __i915_write
1335
1336#define I915_READ8(reg) i915_read8(dev_priv, (reg))
1337#define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1338
1339#define I915_READ16(reg) i915_read16(dev_priv, (reg))
1340#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1341#define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1342#define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1343
1344#define I915_READ(reg) i915_read32(dev_priv, (reg))
1345#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1346#define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1347#define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1348
1349#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1350#define I915_READ64(reg) i915_read64(dev_priv, (reg))
1351
1352#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1353#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1354
1355
1356
1357
1358
1359
1360void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1361void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1362void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1363
1364static inline u32 i915_gt_read(struct drm_i915_private *dev_priv, u32 reg)
1365{
1366 u32 val;
1367
1368 if (dev_priv->info->gen >= 6) {
1369 __gen6_gt_force_wake_get(dev_priv);
1370 val = I915_READ(reg);
1371 __gen6_gt_force_wake_put(dev_priv);
1372 } else
1373 val = I915_READ(reg);
1374
1375 return val;
1376}
1377
1378static inline void i915_gt_write(struct drm_i915_private *dev_priv,
1379 u32 reg, u32 val)
1380{
1381 if (dev_priv->info->gen >= 6)
1382 __gen6_gt_wait_for_fifo(dev_priv);
1383 I915_WRITE(reg, val);
1384}
1385
1386static inline void
1387i915_write(struct drm_i915_private *dev_priv, u32 reg, u64 val, int len)
1388{
1389
1390 trace_i915_reg_rw('W', reg, val, len);
1391 switch (len) {
1392 case 8:
1393 writeq(val, dev_priv->regs + reg);
1394 break;
1395 case 4:
1396 writel(val, dev_priv->regs + reg);
1397 break;
1398 case 2:
1399 writew(val, dev_priv->regs + reg);
1400 break;
1401 case 1:
1402 writeb(val, dev_priv->regs + reg);
1403 break;
1404 }
1405}
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422#define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
1423 (LP_RING(dev_priv)->status_page.page_addr))[reg])
1424#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1425#define I915_GEM_HWS_INDEX 0x20
1426#define I915_BREADCRUMB_INDEX 0x21
1427
1428#endif
1429