/*
 * Copyright 2005-2006 Erik Waling
 * Copyright 2006 Stephane Marchesin
 * Copyright 2007-2009 Stuart Bennett
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include "drmP.h"
#define NV_DEBUG_NOTRACE
#include "nouveau_drv.h"
#include "nouveau_hw.h"
#include "nouveau_encoder.h"

#include <linux/io-mapping.h>

/* these defines are made up */
#define NV_CIO_CRE_44_HEADA 0x0
#define NV_CIO_CRE_44_HEADB 0x3
#define FEATURE_MOBILE 0x10     /* also FEATURE_QUADRO for BMP */
#define LEGACY_I2C_CRT 0x80
#define LEGACY_I2C_PANEL 0x81
#define LEGACY_I2C_TV 0x82

#define EDID1_LEN 128

#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
#define LOG_OLD_VALUE(x)

struct init_exec {
        bool execute;
        bool repeat;
};

static bool nv_cksum(const uint8_t *data, unsigned int length)
{
        /*
         * There's a few checksums in the BIOS, so here's a generic checking
         * function.
         */
        int i;
        uint8_t sum = 0;

        for (i = 0; i < length; i++)
                sum += data[i];

        if (sum)
                return true;

        return false;
}

static int
score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable)
{
        if (!(data[0] == 0x55 && data[1] == 0xAA)) {
                NV_TRACEWARN(dev, "... BIOS signature not found\n");
                return 0;
        }

        if (nv_cksum(data, data[2] * 512)) {
                NV_TRACEWARN(dev, "... BIOS checksum invalid\n");
                /* if a ro image is somewhat bad, it's probably all rubbish */
                return writeable ? 2 : 1;
        } else
                NV_TRACE(dev, "... appears to be valid\n");

        return 3;
}

static void load_vbios_prom(struct drm_device *dev, uint8_t *data)
{
        struct drm_nouveau_private *dev_priv = dev->dev_private;
        uint32_t pci_nv_20, save_pci_nv_20;
        int pcir_ptr;
        int i;

        if (dev_priv->card_type >= NV_50)
                pci_nv_20 = 0x88050;
        else
                pci_nv_20 = NV_PBUS_PCI_NV_20;

        /* enable ROM access */
        save_pci_nv_20 = nvReadMC(dev, pci_nv_20);
        nvWriteMC(dev, pci_nv_20,
                  save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);

        /* bail if no rom signature */
        if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 ||
            nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
                goto out;

        /* additional check (see note below) - read PCI record header */
        pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
                   nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
        if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' ||
            nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' ||
            nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' ||
            nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R')
                goto out;

        /* on some 6600GT/6800LE prom reads are messed up.  nvclock alleges a
         * a good read may be obtained by waiting or re-reading (cargocult: 5x)
         * each byte.  we'll hope pramin has something usable instead
         */
        for (i = 0; i < NV_PROM_SIZE; i++)
                data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);

out:
        /* disable ROM access */
        nvWriteMC(dev, pci_nv_20,
                  save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
}

static void load_vbios_pramin(struct drm_device *dev, uint8_t *data)
{
        struct drm_nouveau_private *dev_priv = dev->dev_private;
        uint32_t old_bar0_pramin = 0;
        int i;

        if (dev_priv->card_type >= NV_50) {
                uint32_t vbios_vram = (nv_rd32(dev, 0x619f04) & ~0xff) << 8;

                if (!vbios_vram)
                        vbios_vram = (nv_rd32(dev, 0x1700) << 16) + 0xf0000;

                old_bar0_pramin = nv_rd32(dev, 0x1700);
                nv_wr32(dev, 0x1700, vbios_vram >> 16);
        }

        /* bail if no rom signature */
        if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 ||
            nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa)
                goto out;

        for (i = 0; i < NV_PROM_SIZE; i++)
                data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);

out:
        if (dev_priv->card_type >= NV_50)
                nv_wr32(dev, 0x1700, old_bar0_pramin);
}

static void load_vbios_pci(struct drm_device *dev, uint8_t *data)
{
        void __iomem *rom = NULL;
        size_t rom_len;
        int ret;

        ret = pci_enable_rom(dev->pdev);
        if (ret)
                return;

        rom = pci_map_rom(dev->pdev, &rom_len);
        if (!rom)
                goto out;
        memcpy_fromio(data, rom, rom_len);
        pci_unmap_rom(dev->pdev, rom);

out:
        pci_disable_rom(dev->pdev);
}

static void load_vbios_acpi(struct drm_device *dev, uint8_t *data)
{
        int i;
        int ret;
        int size = 64 * 1024;

        if (!nouveau_acpi_rom_supported(dev->pdev))
                return;

        for (i = 0; i < (size / ROM_BIOS_PAGE); i++) {
                ret = nouveau_acpi_get_bios_chunk(data,
                                                  (i * ROM_BIOS_PAGE),
                                                  ROM_BIOS_PAGE);
                if (ret <= 0)
                        break;
        }
        return;
}

struct methods {
        const char desc[8];
        void (*loadbios)(struct drm_device *, uint8_t *);
        const bool rw;
};

static struct methods shadow_methods[] = {
        { "PRAMIN", load_vbios_pramin, true },
        { "PROM", load_vbios_prom, false },
        { "PCIROM", load_vbios_pci, true },
        { "ACPI", load_vbios_acpi, true },
};
#define NUM_SHADOW_METHODS ARRAY_SIZE(shadow_methods)

static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
{
        struct methods *methods = shadow_methods;
        int testscore = 3;
        int scores[NUM_SHADOW_METHODS], i;

        if (nouveau_vbios) {
                for (i = 0; i < NUM_SHADOW_METHODS; i++)
                        if (!strcasecmp(nouveau_vbios, methods[i].desc))
                                break;

                if (i < NUM_SHADOW_METHODS) {
                        NV_INFO(dev, "Attempting to use BIOS image from %s\n",
                                methods[i].desc);

                        methods[i].loadbios(dev, data);
                        if (score_vbios(dev, data, methods[i].rw))
                                return true;
                }

                NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
        }

        for (i = 0; i < NUM_SHADOW_METHODS; i++) {
                NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
                         methods[i].desc);
                data[0] = data[1] = 0;  /* avoid reuse of previous image */
                methods[i].loadbios(dev, data);
                scores[i] = score_vbios(dev, data, methods[i].rw);
                if (scores[i] == testscore)
                        return true;
        }

        while (--testscore > 0) {
                for (i = 0; i < NUM_SHADOW_METHODS; i++) {
                        if (scores[i] == testscore) {
                                NV_TRACE(dev, "Using BIOS image from %s\n",
                                         methods[i].desc);
                                methods[i].loadbios(dev, data);
                                return true;
                        }
                }
        }

        NV_ERROR(dev, "No valid BIOS image found\n");
        return false;
}

struct init_tbl_entry {
        char *name;
        uint8_t id;
        /* Return:
         *  > 0: success, length of opcode
         *    0: success, but abort further parsing of table (INIT_DONE etc)
         *  < 0: failure, table parsing will be aborted
         */
        int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
};

static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *);

#define MACRO_INDEX_SIZE        2
#define MACRO_SIZE              8
#define CONDITION_SIZE          12
#define IO_FLAG_CONDITION_SIZE  9
#define IO_CONDITION_SIZE       5
#define MEM_INIT_SIZE           66

static void still_alive(void)
{
#if 0
        sync();
        msleep(2);
#endif
}

static uint32_t
munge_reg(struct nvbios *bios, uint32_t reg)
{
        struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
        struct dcb_entry *dcbent = bios->display.output;

        if (dev_priv->card_type < NV_50)
                return reg;

        if (reg & 0x40000000) {
                BUG_ON(!dcbent);

                reg += (ffs(dcbent->or) - 1) * 0x800;
                if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
                        reg += 0x00000080;
        }

        reg &= ~0x60000000;
        return reg;
}

static int
valid_reg(struct nvbios *bios, uint32_t reg)
{
        struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
        struct drm_device *dev = bios->dev;

        /* C51 has misaligned regs on purpose. Marvellous */
        if (reg & 0x2 ||
            (reg & 0x1 && dev_priv->vbios.chip_version != 0x51))
                NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);

        /* warn on C51 regs that haven't been verified accessible in tracing */
        if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 &&
            reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
                NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
                        reg);

        if (reg >= (8*1024*1024)) {
                NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
                return 0;
        }

        return 1;
}

static bool
valid_idx_port(struct nvbios *bios, uint16_t port)
{
        struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
        struct drm_device *dev = bios->dev;

        /*
         * If adding more ports here, the read/write functions below will need
         * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
         * used for the port in question
         */
        if (dev_priv->card_type < NV_50) {
                if (port == NV_CIO_CRX__COLOR)
                        return true;
                if (port == NV_VIO_SRX)
                        return true;
        } else {
                if (port == NV_CIO_CRX__COLOR)
                        return true;
        }

        NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
                 port);

        return false;
}

static bool
valid_port(struct nvbios *bios, uint16_t port)
{
        struct drm_device *dev = bios->dev;

        /*
         * If adding more ports here, the read/write functions below will need
         * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
         * used for the port in question
         */
        if (port == NV_VIO_VSE2)
                return true;

        NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);

        return false;
}

static uint32_t
bios_rd32(struct nvbios *bios, uint32_t reg)
{
        uint32_t data;

        reg = munge_reg(bios, reg);
        if (!valid_reg(bios, reg))
                return 0;

        /*
         * C51 sometimes uses regs with bit0 set in the address. For these
         * cases there should exist a translation in a BIOS table to an IO
         * port address which the BIOS uses for accessing the reg
         *
         * These only seem to appear for the power control regs to a flat panel,
         * and the GPIO regs at 0x60081*.  In C51 mmio traces the normal regs
         * for 0x1308 and 0x1310 are used - hence the mask below.  An S3
         * suspend-resume mmio trace from a C51 will be required to see if this
         * is true for the power microcode in 0x14.., or whether the direct IO
         * port access method is needed
         */
        if (reg & 0x1)
                reg &= ~0x1;

        data = nv_rd32(bios->dev, reg);

        BIOSLOG(bios, " Read:  Reg: 0x%08X, Data: 0x%08X\n", reg, data);

        return data;
}

static void
bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
{
        struct drm_nouveau_private *dev_priv = bios->dev->dev_private;

        reg = munge_reg(bios, reg);
        if (!valid_reg(bios, reg))
                return;

        /* see note in bios_rd32 */
        if (reg & 0x1)
                reg &= 0xfffffffe;

        LOG_OLD_VALUE(bios_rd32(bios, reg));
        BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);

        if (dev_priv->vbios.execute) {
                still_alive();
                nv_wr32(bios->dev, reg, data);
        }
}

static uint8_t
bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
{
        struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
        struct drm_device *dev = bios->dev;
        uint8_t data;

        if (!valid_idx_port(bios, port))
                return 0;

        if (dev_priv->card_type < NV_50) {
                if (port == NV_VIO_SRX)
                        data = NVReadVgaSeq(dev, bios->state.crtchead, index);
                else    /* assume NV_CIO_CRX__COLOR */
                        data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
        } else {
                uint32_t data32;

                data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
                data = (data32 >> ((index & 3) << 3)) & 0xff;
        }

        BIOSLOG(bios, " Indexed IO read:  Port: 0x%04X, Index: 0x%02X, "
                      "Head: 0x%02X, Data: 0x%02X\n",
                port, index, bios->state.crtchead, data);
        return data;
}

static void
bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
{
        struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
        struct drm_device *dev = bios->dev;

        if (!valid_idx_port(bios, port))
                return;

        /*
         * The current head is maintained in the nvbios member  state.crtchead.
         * We trap changes to CR44 and update the head variable and hence the
         * register set written.
         * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
         * of the write, and to head1 after the write
         */
        if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
            data != NV_CIO_CRE_44_HEADB)
                bios->state.crtchead = 0;

        LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
        BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
                      "Head: 0x%02X, Data: 0x%02X\n",
                port, index, bios->state.crtchead, data);

        if (bios->execute && dev_priv->card_type < NV_50) {
                still_alive();
                if (port == NV_VIO_SRX)
                        NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
                else    /* assume NV_CIO_CRX__COLOR */
                        NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
        } else
        if (bios->execute) {
                uint32_t data32, shift = (index & 3) << 3;

                still_alive();

                data32  = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
                data32 &= ~(0xff << shift);
                data32 |= (data << shift);
                bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
        }

        if (port == NV_CIO_CRX__COLOR &&
            index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
                bios->state.crtchead = 1;
}

static uint8_t
bios_port_rd(struct nvbios *bios, uint16_t port)
{
        uint8_t data, head = bios->state.crtchead;

        if (!valid_port(bios, port))
                return 0;

        data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);

        BIOSLOG(bios, " IO read:  Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
                port, head, data);

        return data;
}

static void
bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
{
        int head = bios->state.crtchead;

        if (!valid_port(bios, port))
                return;

        LOG_OLD_VALUE(bios_port_rd(bios, port));
        BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
                port, head, data);

        if (!bios->execute)
                return;

        still_alive();
        NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
}

static bool
io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
{
        /*
         * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
         * for the CRTC index; 1 byte for the mask to apply to the value
         * retrieved from the CRTC; 1 byte for the shift right to apply to the
         * masked CRTC value; 2 bytes for the offset to the flag array, to
         * which the shifted value is added; 1 byte for the mask applied to the
         * value read from the flag array; and 1 byte for the value to compare
         * against the masked byte from the flag table.
         */

        uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
        uint16_t crtcport = ROM16(bios->data[condptr]);
        uint8_t crtcindex = bios->data[condptr + 2];
        uint8_t mask = bios->data[condptr + 3];
        uint8_t shift = bios->data[condptr + 4];
        uint16_t flagarray = ROM16(bios->data[condptr + 5]);
        uint8_t flagarraymask = bios->data[condptr + 7];
        uint8_t cmpval = bios->data[condptr + 8];
        uint8_t data;

        BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
                      "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
                      "Cmpval: 0x%02X\n",
                offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);

        data = bios_idxprt_rd(bios, crtcport, crtcindex);

        data = bios->data[flagarray + ((data & mask) >> shift)];
        data &= flagarraymask;

        BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
                offset, data, cmpval);

        return (data == cmpval);
}

static bool
bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
{
        /*
         * The condition table entry has 4 bytes for the address of the
         * register to check, 4 bytes for a mask to apply to the register and
         * 4 for a test comparison value
         */

        uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
        uint32_t reg = ROM32(bios->data[condptr]);
        uint32_t mask = ROM32(bios->data[condptr + 4]);
        uint32_t cmpval = ROM32(bios->data[condptr + 8]);
        uint32_t data;

        BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
                offset, cond, reg, mask);

        data = bios_rd32(bios, reg) & mask;

        BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
                offset, data, cmpval);

        return (data == cmpval);
}

static bool
io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
{
        /*
         * The IO condition entry has 2 bytes for the IO port address; 1 byte
         * for the index to write to io_port; 1 byte for the mask to apply to
         * the byte read from io_port+1; and 1 byte for the value to compare
         * against the masked byte.
         */

        uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
        uint16_t io_port = ROM16(bios->data[condptr]);
        uint8_t port_index = bios->data[condptr + 2];
        uint8_t mask = bios->data[condptr + 3];
        uint8_t cmpval = bios->data[condptr + 4];

        uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;

        BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
                offset, data, cmpval);

        return (data == cmpval);
}

static int
nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
{
        struct drm_nouveau_private *dev_priv = dev->dev_private;
        uint32_t reg0 = nv_rd32(dev, reg + 0);
        uint32_t reg1 = nv_rd32(dev, reg + 4);
        struct nouveau_pll_vals pll;
        struct pll_lims pll_limits;
        int ret;

        ret = get_pll_limits(dev, reg, &pll_limits);
        if (ret)
                return ret;

        clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
        if (!clk)
                return -ERANGE;

        reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16);
        reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1;

        if (dev_priv->vbios.execute) {
                still_alive();
                nv_wr32(dev, reg + 4, reg1);
                nv_wr32(dev, reg + 0, reg0);
        }

        return 0;
}

static int
setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk)
{
        struct drm_device *dev = bios->dev;
        struct drm_nouveau_private *dev_priv = dev->dev_private;
        /* clk in kHz */
        struct pll_lims pll_lim;
        struct nouveau_pll_vals pllvals;
        int ret;

        if (dev_priv->card_type >= NV_50)
                return nv50_pll_set(dev, reg, clk);

        /* high regs (such as in the mac g5 table) are not -= 4 */
        ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim);
        if (ret)
                return ret;

        clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals);
        if (!clk)
                return -ERANGE;

        if (bios->execute) {
                still_alive();
                nouveau_hw_setpll(dev, reg, &pllvals);
        }

        return 0;
}

static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
{
        struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct nvbios *bios = &dev_priv->vbios;

        /*
         * For the results of this function to be correct, CR44 must have been
         * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
         * and the DCB table parsed, before the script calling the function is
         * run.  run_digital_op_script is example of how to do such setup
         */

        uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);

        if (dcb_entry > bios->dcb.entries) {
                NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
                                "(%02X)\n", dcb_entry);
                dcb_entry = 0x7f;       /* unused / invalid marker */
        }

        return dcb_entry;
}

static int
read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c)
{
        uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4;
        int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES;
        int recordoffset = 0, rdofs = 1, wrofs = 0;
        uint8_t port_type = 0;

        if (!i2ctable)
                return -EINVAL;

        if (dcb_version >= 0x30) {
                if (i2ctable[0] != dcb_version) /* necessary? */
                        NV_WARN(dev,
                                "DCB I2C table version mismatch (%02X vs %02X)\n",
                                i2ctable[0], dcb_version);
                dcb_i2c_ver = i2ctable[0];
                headerlen = i2ctable[1];
                if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES)
                        i2c_entries = i2ctable[2];
                else
                        NV_WARN(dev,
                                "DCB I2C table has more entries than indexable "
                                "(%d entries, max %d)\n", i2ctable[2],
                                DCB_MAX_NUM_I2C_ENTRIES);
                entry_len = i2ctable[3];
                /* [4] is i2c_default_indices, read in parse_dcb_table() */
        }
        /*
         * It's your own fault if you call this function on a DCB 1.1 BIOS --
         * the test below is for DCB 1.2
         */
        if (dcb_version < 0x14) {
                recordoffset = 2;
                rdofs = 0;
                wrofs = 1;
        }

        if (index == 0xf)
                return 0;
        if (index >= i2c_entries) {
                NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n",
                         index, i2ctable[2]);
                return -ENOENT;
        }
        if (i2ctable[headerlen + entry_len * index + 3] == 0xff) {
                NV_ERROR(dev, "DCB I2C entry invalid\n");
                return -EINVAL;
        }

        if (dcb_i2c_ver >= 0x30) {
                port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index];

                /*
                 * Fixup for chips using same address offset for read and
                 * write.
                 */
                if (port_type == 4)     /* seen on C51 */
                        rdofs = wrofs = 1;
                if (port_type >= 5)     /* G80+ */
                        rdofs = wrofs = 0;
        }

        if (dcb_i2c_ver >= 0x40) {
                if (port_type != 5 && port_type != 6)
                        NV_WARN(dev, "DCB I2C table has port type %d\n", port_type);

                i2c->entry = ROM32(i2ctable[headerlen + recordoffset + entry_len * index]);
        }

        i2c->port_type = port_type;
        i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index];
        i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index];

        return 0;
}

static struct nouveau_i2c_chan *
init_i2c_device_find(struct drm_device *dev, int i2c_index)
{
        struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct dcb_table *dcb = &dev_priv->vbios.dcb;

        if (i2c_index == 0xff) {
                /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
                int idx = dcb_entry_idx_from_crtchead(dev), shift = 0;
                int default_indices = dcb->i2c_default_indices;

                if (idx != 0x7f && dcb->entry[idx].i2c_upper_default)
                        shift = 4;

                i2c_index = (default_indices >> shift) & 0xf;
        }
        if (i2c_index == 0x80)  /* g80+ */
                i2c_index = dcb->i2c_default_indices & 0xf;
        else
        if (i2c_index == 0x81)
                i2c_index = (dcb->i2c_default_indices & 0xf0) >> 4;

        if (i2c_index >= DCB_MAX_NUM_I2C_ENTRIES) {
                NV_ERROR(dev, "invalid i2c_index 0x%x\n", i2c_index);
                return NULL;
        }

        /* Make sure i2c table entry has been parsed, it may not
         * have been if this is a bus not referenced by a DCB encoder
         */
        read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
                           i2c_index, &dcb->i2c[i2c_index]);

        return nouveau_i2c_find(dev, i2c_index);
}

static uint32_t
get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
{
        /*
         * For mlv < 0x80, it is an index into a table of TMDS base addresses.
         * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
         * CR58 for CR57 = 0 to index a table of offsets to the basic
         * 0x6808b0 address.
         * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
         * CR58 for CR57 = 0 to index a table of offsets to the basic
         * 0x6808b0 address, and then flip the offset by 8.
         */

        struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct nvbios *bios = &dev_priv->vbios;
        const int pramdac_offset[13] = {
                0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
        const uint32_t pramdac_table[4] = {
                0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };

        if (mlv >= 0x80) {
                int dcb_entry, dacoffset;

                /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
                dcb_entry = dcb_entry_idx_from_crtchead(dev);
                if (dcb_entry == 0x7f)
                        return 0;
                dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or];
                if (mlv == 0x81)
                        dacoffset ^= 8;
                return 0x6808b0 + dacoffset;
        } else {
                if (mlv >= ARRAY_SIZE(pramdac_table)) {
                        NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
                                                                        mlv);
                        return 0;
                }
                return pramdac_table[mlv];
        }
}

static int
init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
                      struct init_exec *iexec)
{
        /*
         * INIT_IO_RESTRICT_PROG   opcode: 0x32 ('2')
         *
         * offset      (8  bit): opcode
         * offset + 1  (16 bit): CRTC port
         * offset + 3  (8  bit): CRTC index
         * offset + 4  (8  bit): mask
         * offset + 5  (8  bit): shift
         * offset + 6  (8  bit): count
         * offset + 7  (32 bit): register
         * offset + 11 (32 bit): configuration 1
         * ...
         *
         * Starting at offset + 11 there are "count" 32 bit values.
         * To find out which value to use read index "CRTC index" on "CRTC
         * port", AND this value with "mask" and then bit shift right "shift"
         * bits.  Read the appropriate value using this index and write to
         * "register"
         */

        uint16_t crtcport = ROM16(bios->data[offset + 1]);
        uint8_t crtcindex = bios->data[offset + 3];
        uint8_t mask = bios->data[offset + 4];
        uint8_t shift = bios->data[offset + 5];
        uint8_t count = bios->data[offset + 6];
        uint32_t reg = ROM32(bios->data[offset + 7]);
        uint8_t config;
        uint32_t configval;
        int len = 11 + count * 4;

        if (!iexec->execute)
                return len;

        BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
                      "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
                offset, crtcport, crtcindex, mask, shift, count, reg);

        config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
        if (config > count) {
                NV_ERROR(bios->dev,
                         "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
                         offset, config, count);
                return len;
        }

        configval = ROM32(bios->data[offset + 11 + config * 4]);

        BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);

        bios_wr32(bios, reg, configval);

        return len;
}

static int
init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_REPEAT   opcode: 0x33 ('3')
         *
         * offset      (8 bit): opcode
         * offset + 1  (8 bit): count
         *
         * Execute script following this opcode up to INIT_REPEAT_END
         * "count" times
         */

        uint8_t count = bios->data[offset + 1];
        uint8_t i;

        /* no iexec->execute check by design */

        BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
                offset, count);

        iexec->repeat = true;

        /*
         * count - 1, as the script block will execute once when we leave this
         * opcode -- this is compatible with bios behaviour as:
         * a) the block is always executed at least once, even if count == 0
         * b) the bios interpreter skips to the op following INIT_END_REPEAT,
         * while we don't
         */
        for (i = 0; i < count - 1; i++)
                parse_init_table(bios, offset + 2, iexec);

        iexec->repeat = false;

        return 2;
}

static int
init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
                     struct init_exec *iexec)
{
        /*
         * INIT_IO_RESTRICT_PLL   opcode: 0x34 ('4')
         *
         * offset      (8  bit): opcode
         * offset + 1  (16 bit): CRTC port
         * offset + 3  (8  bit): CRTC index
         * offset + 4  (8  bit): mask
         * offset + 5  (8  bit): shift
         * offset + 6  (8  bit): IO flag condition index
         * offset + 7  (8  bit): count
         * offset + 8  (32 bit): register
         * offset + 12 (16 bit): frequency 1
         * ...
         *
         * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
         * Set PLL register "register" to coefficients for frequency n,
         * selected by reading index "CRTC index" of "CRTC port" ANDed with
         * "mask" and shifted right by "shift".
         *
         * If "IO flag condition index" > 0, and condition met, double
         * frequency before setting it.
         */

        uint16_t crtcport = ROM16(bios->data[offset + 1]);
        uint8_t crtcindex = bios->data[offset + 3];
        uint8_t mask = bios->data[offset + 4];
        uint8_t shift = bios->data[offset + 5];
        int8_t io_flag_condition_idx = bios->data[offset + 6];
        uint8_t count = bios->data[offset + 7];
        uint32_t reg = ROM32(bios->data[offset + 8]);
        uint8_t config;

        uint16_t freq;
        int len = 12 + count * 2;

        if (!iexec->execute)
                return len;

        BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
                      "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
                      "Count: 0x%02X, Reg: 0x%08X\n",
                offset, crtcport, crtcindex, mask, shift,
                io_flag_condition_idx, count, reg);

        config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
        if (config > count) {
                NV_ERROR(bios->dev,
                         "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
                         offset, config, count);
                return len;
        }

        freq = ROM16(bios->data[offset + 12 + config * 2]);

        if (io_flag_condition_idx > 0) {
                if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
                        BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
                                      "frequency doubled\n", offset);
                        freq *= 2;
                } else
                        BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
                                      "frequency unchanged\n", offset);
        }

        BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
                offset, reg, config, freq);

        setPLL(bios, reg, freq * 10);

        return len;
}

static int
init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_END_REPEAT   opcode: 0x36 ('6')
         *
         * offset      (8 bit): opcode
         *
         * Marks the end of the block for INIT_REPEAT to repeat
         */

        /* no iexec->execute check by design */

        /*
         * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
         * we're not in repeat mode
         */
        if (iexec->repeat)
                return 0;

        return 1;
}

static int
init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_COPY   opcode: 0x37 ('7')
         *
         * offset      (8  bit): opcode
         * offset + 1  (32 bit): register
         * offset + 5  (8  bit): shift
         * offset + 6  (8  bit): srcmask
         * offset + 7  (16 bit): CRTC port
         * offset + 9  (8 bit): CRTC index
         * offset + 10  (8 bit): mask
         *
         * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
         * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
         * port
         */

        uint32_t reg = ROM32(bios->data[offset + 1]);
        uint8_t shift = bios->data[offset + 5];
        uint8_t srcmask = bios->data[offset + 6];
        uint16_t crtcport = ROM16(bios->data[offset + 7]);
        uint8_t crtcindex = bios->data[offset + 9];
        uint8_t mask = bios->data[offset + 10];
        uint32_t data;
        uint8_t crtcdata;

        if (!iexec->execute)
                return 11;

        BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
                      "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
                offset, reg, shift, srcmask, crtcport, crtcindex, mask);

        data = bios_rd32(bios, reg);

        if (shift < 0x80)
                data >>= shift;
        else
                data <<= (0x100 - shift);

        data &= srcmask;

        crtcdata  = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
        crtcdata |= (uint8_t)data;
        bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);

        return 11;
}

static int
init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_NOT   opcode: 0x38 ('8')
         *
         * offset      (8  bit): opcode
         *
         * Invert the current execute / no-execute condition (i.e. "else")
         */
        if (iexec->execute)
                BIOSLOG(bios, "0x%04X: ------ Skipping following commands  ------\n", offset);
        else
                BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);

        iexec->execute = !iexec->execute;
        return 1;
}

static int
init_io_flag_condition(struct nvbios *bios, uint16_t offset,
                       struct init_exec *iexec)
{
        /*
         * INIT_IO_FLAG_CONDITION   opcode: 0x39 ('9')
         *
         * offset      (8 bit): opcode
         * offset + 1  (8 bit): condition number
         *
         * Check condition "condition number" in the IO flag condition table.
         * If condition not met skip subsequent opcodes until condition is
         * inverted (INIT_NOT), or we hit INIT_RESUME
         */

        uint8_t cond = bios->data[offset + 1];

        if (!iexec->execute)
                return 2;

        if (io_flag_condition_met(bios, offset, cond))
                BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
        else {
                BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
                iexec->execute = false;
        }

        return 2;
}

static int
init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_DP_CONDITION   opcode: 0x3A ('')
         *
         * offset      (8 bit): opcode
         * offset + 1  (8 bit): "sub" opcode
         * offset + 2  (8 bit): unknown
         *
         */

        struct bit_displayport_encoder_table *dpe = NULL;
        struct dcb_entry *dcb = bios->display.output;
        struct drm_device *dev = bios->dev;
        uint8_t cond = bios->data[offset + 1];
        int dummy;

        BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond);

        if (!iexec->execute)
                return 3;

        dpe = nouveau_bios_dp_table(dev, dcb, &dummy);
        if (!dpe) {
                NV_ERROR(dev, "0x%04X: INIT_3A: no encoder table!!\n", offset);
                return 3;
        }

        switch (cond) {
        case 0:
        {
                struct dcb_connector_table_entry *ent =
                        &bios->dcb.connector.entry[dcb->connector];

                if (ent->type != DCB_CONNECTOR_eDP)
                        iexec->execute = false;
        }
                break;
        case 1:
        case 2:
                if (!(dpe->unknown & cond))
                        iexec->execute = false;
                break;
        case 5:
        {
                struct nouveau_i2c_chan *auxch;
                int ret;

                auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index);
                if (!auxch) {
                        NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset);
                        return 3;
                }

                ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1);
                if (ret) {
                        NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret);
                        return 3;
                }

                if (!(cond & 1))
                        iexec->execute = false;
        }
                break;
        default:
                NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond);
                break;
        }

        if (iexec->execute)
                BIOSLOG(bios, "0x%04X: continuing to execute\n", offset);
        else
                BIOSLOG(bios, "0x%04X: skipping following commands\n", offset);

        return 3;
}

static int
init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_3B   opcode: 0x3B ('')
         *
         * offset      (8 bit): opcode
         * offset + 1  (8 bit): crtc index
         *
         */

        uint8_t or = ffs(bios->display.output->or) - 1;
        uint8_t index = bios->data[offset + 1];
        uint8_t data;

        if (!iexec->execute)
                return 2;

        data = bios_idxprt_rd(bios, 0x3d4, index);
        bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or));
        return 2;
}

static int
init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_3C   opcode: 0x3C ('')
         *
         * offset      (8 bit): opcode
         * offset + 1  (8 bit): crtc index
         *
         */

        uint8_t or = ffs(bios->display.output->or) - 1;
        uint8_t index = bios->data[offset + 1];
        uint8_t data;

        if (!iexec->execute)
                return 2;

        data = bios_idxprt_rd(bios, 0x3d4, index);
        bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or));
        return 2;
}

static int
init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
                      struct init_exec *iexec)
{
        /*
         * INIT_INDEX_ADDRESS_LATCHED   opcode: 0x49 ('I')
         *
         * offset      (8  bit): opcode
         * offset + 1  (32 bit): control register
         * offset + 5  (32 bit): data register
         * offset + 9  (32 bit): mask
         * offset + 13 (32 bit): data
         * offset + 17 (8  bit): count
         * offset + 18 (8  bit): address 1
         * offset + 19 (8  bit): data 1
         * ...
         *
         * For each of "count" address and data pairs, write "data n" to
         * "data register", read the current value of "control register",
         * and write it back once ANDed with "mask", ORed with "data",
         * and ORed with "address n"
         */

        uint32_t controlreg = ROM32(bios->data[offset + 1]);
        uint32_t datareg = ROM32(bios->data[offset + 5]);
        uint32_t mask = ROM32(bios->data[offset + 9]);
        uint32_t data = ROM32(bios->data[offset + 13]);
        uint8_t count = bios->data[offset + 17];
        int len = 18 + count * 2;
        uint32_t value;
        int i;

        if (!iexec->execute)
                return len;

        BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
                      "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
                offset, controlreg, datareg, mask, data, count);

        for (i = 0; i < count; i++) {
                uint8_t instaddress = bios->data[offset + 18 + i * 2];
                uint8_t instdata = bios->data[offset + 19 + i * 2];

                BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
                        offset, instaddress, instdata);

                bios_wr32(bios, datareg, instdata);
                value  = bios_rd32(bios, controlreg) & mask;
                value |= data;
                value |= instaddress;
                bios_wr32(bios, controlreg, value);
        }

        return len;
}

static int
init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
                      struct init_exec *iexec)
{
        /*
         * INIT_IO_RESTRICT_PLL2   opcode: 0x4A ('J')
         *
         * offset      (8  bit): opcode
         * offset + 1  (16 bit): CRTC port
         * offset + 3  (8  bit): CRTC index
         * offset + 4  (8  bit): mask
         * offset + 5  (8  bit): shift
         * offset + 6  (8  bit): count
         * offset + 7  (32 bit): register
         * offset + 11 (32 bit): frequency 1
         * ...
         *
         * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
         * Set PLL register "register" to coefficients for frequency n,
         * selected by reading index "CRTC index" of "CRTC port" ANDed with
         * "mask" and shifted right by "shift".
         */

        uint16_t crtcport = ROM16(bios->data[offset + 1]);
        uint8_t crtcindex = bios->data[offset + 3];
        uint8_t mask = bios->data[offset + 4];
        uint8_t shift = bios->data[offset + 5];
        uint8_t count = bios->data[offset + 6];
        uint32_t reg = ROM32(bios->data[offset + 7]);
        int len = 11 + count * 4;
        uint8_t config;
        uint32_t freq;

        if (!iexec->execute)
                return len;

        BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
                      "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
                offset, crtcport, crtcindex, mask, shift, count, reg);

        if (!reg)
                return len;

        config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
        if (config > count) {
                NV_ERROR(bios->dev,
                         "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
                         offset, config, count);
                return len;
        }

        freq = ROM32(bios->data[offset + 11 + config * 4]);

        BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
                offset, reg, config, freq);

        setPLL(bios, reg, freq);

        return len;
}

static int
init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_PLL2   opcode: 0x4B ('K')
         *
         * offset      (8  bit): opcode
         * offset + 1  (32 bit): register
         * offset + 5  (32 bit): freq
         *
         * Set PLL register "register" to coefficients for frequency "freq"
         */

        uint32_t reg = ROM32(bios->data[offset + 1]);
        uint32_t freq = ROM32(bios->data[offset + 5]);

        if (!iexec->execute)
                return 9;

        BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
                offset, reg, freq);

        setPLL(bios, reg, freq);
        return 9;
}

static int
init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_I2C_BYTE   opcode: 0x4C ('L')
         *
         * offset      (8 bit): opcode
         * offset + 1  (8 bit): DCB I2C table entry index
         * offset + 2  (8 bit): I2C slave address
         * offset + 3  (8 bit): count
         * offset + 4  (8 bit): I2C register 1
         * offset + 5  (8 bit): mask 1
         * offset + 6  (8 bit): data 1
         * ...
         *
         * For each of "count" registers given by "I2C register n" on the device
         * addressed by "I2C slave address" on the I2C bus given by
         * "DCB I2C table entry index", read the register, AND the result with
         * "mask n" and OR it with "data n" before writing it back to the device
         */

        struct drm_device *dev = bios->dev;
        uint8_t i2c_index = bios->data[offset + 1];
        uint8_t i2c_address = bios->data[offset + 2] >> 1;
        uint8_t count = bios->data[offset + 3];
        struct nouveau_i2c_chan *chan;
        int len = 4 + count * 3;
        int ret, i;

        if (!iexec->execute)
                return len;

        BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
                      "Count: 0x%02X\n",
                offset, i2c_index, i2c_address, count);

        chan = init_i2c_device_find(dev, i2c_index);
        if (!chan) {
                NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
                return len;
        }

        for (i = 0; i < count; i++) {
                uint8_t reg = bios->data[offset + 4 + i * 3];
                uint8_t mask = bios->data[offset + 5 + i * 3];
                uint8_t data = bios->data[offset + 6 + i * 3];
                union i2c_smbus_data val;

                ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
                                     I2C_SMBUS_READ, reg,
                                     I2C_SMBUS_BYTE_DATA, &val);
                if (ret < 0) {
                        NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret);
                        return len;
                }

                BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
                              "Mask: 0x%02X, Data: 0x%02X\n",
                        offset, reg, val.byte, mask, data);

                if (!bios->execute)
                        continue;

                val.byte &= mask;
                val.byte |= data;
                ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
                                     I2C_SMBUS_WRITE, reg,
                                     I2C_SMBUS_BYTE_DATA, &val);
                if (ret < 0) {
                        NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
                        return len;
                }
        }

        return len;
}

static int
init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_ZM_I2C_BYTE   opcode: 0x4D ('M')
         *
         * offset      (8 bit): opcode
         * offset + 1  (8 bit): DCB I2C table entry index
         * offset + 2  (8 bit): I2C slave address
         * offset + 3  (8 bit): count
         * offset + 4  (8 bit): I2C register 1
         * offset + 5  (8 bit): data 1
         * ...
         *
         * For each of "count" registers given by "I2C register n" on the device
         * addressed by "I2C slave address" on the I2C bus given by
         * "DCB I2C table entry index", set the register to "data n"
         */

        struct drm_device *dev = bios->dev;
        uint8_t i2c_index = bios->data[offset + 1];
        uint8_t i2c_address = bios->data[offset + 2] >> 1;
        uint8_t count = bios->data[offset + 3];
        struct nouveau_i2c_chan *chan;
        int len = 4 + count * 2;
        int ret, i;

        if (!iexec->execute)
                return len;

        BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
                      "Count: 0x%02X\n",
                offset, i2c_index, i2c_address, count);

        chan = init_i2c_device_find(dev, i2c_index);
        if (!chan) {
                NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
                return len;
        }

        for (i = 0; i < count; i++) {
                uint8_t reg = bios->data[offset + 4 + i * 2];
                union i2c_smbus_data val;

                val.byte = bios->data[offset + 5 + i * 2];

                BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
                        offset, reg, val.byte);

                if (!bios->execute)
                        continue;

                ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
                                     I2C_SMBUS_WRITE, reg,
                                     I2C_SMBUS_BYTE_DATA, &val);
                if (ret < 0) {
                        NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
                        return len;
                }
        }

        return len;
}

static int
init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_ZM_I2C   opcode: 0x4E ('N')
         *
         * offset      (8 bit): opcode
         * offset + 1  (8 bit): DCB I2C table entry index
         * offset + 2  (8 bit): I2C slave address
         * offset + 3  (8 bit): count
         * offset + 4  (8 bit): data 1
         * ...
         *
         * Send "count" bytes ("data n") to the device addressed by "I2C slave
         * address" on the I2C bus given by "DCB I2C table entry index"
         */

        struct drm_device *dev = bios->dev;
        uint8_t i2c_index = bios->data[offset + 1];
        uint8_t i2c_address = bios->data[offset + 2] >> 1;
        uint8_t count = bios->data[offset + 3];
        int len = 4 + count;
        struct nouveau_i2c_chan *chan;
        struct i2c_msg msg;
        uint8_t data[256];
        int ret, i;

        if (!iexec->execute)
                return len;

        BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
                      "Count: 0x%02X\n",
                offset, i2c_index, i2c_address, count);

        chan = init_i2c_device_find(dev, i2c_index);
        if (!chan) {
                NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
                return len;
        }

        for (i = 0; i < count; i++) {
                data[i] = bios->data[offset + 4 + i];

                BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
        }

        if (bios->execute) {
                msg.addr = i2c_address;
                msg.flags = 0;
                msg.len = count;
                msg.buf = data;
                ret = i2c_transfer(&chan->adapter, &msg, 1);
                if (ret != 1) {
                        NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
                        return len;
                }
        }

        return len;
}

static int
init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_TMDS   opcode: 0x4F ('O')       (non-canon name)
         *
         * offset      (8 bit): opcode
         * offset + 1  (8 bit): magic lookup value
         * offset + 2  (8 bit): TMDS address
         * offset + 3  (8 bit): mask
         * offset + 4  (8 bit): data
         *
         * Read the data reg for TMDS address "TMDS address", AND it with mask
         * and OR it with data, then write it back
         * "magic lookup value" determines which TMDS base address register is
         * used -- see get_tmds_index_reg()
         */

        struct drm_device *dev = bios->dev;
        uint8_t mlv = bios->data[offset + 1];
        uint32_t tmdsaddr = bios->data[offset + 2];
        uint8_t mask = bios->data[offset + 3];
        uint8_t data = bios->data[offset + 4];
        uint32_t reg, value;

        if (!iexec->execute)
                return 5;

        BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
                      "Mask: 0x%02X, Data: 0x%02X\n",
                offset, mlv, tmdsaddr, mask, data);

        reg = get_tmds_index_reg(bios->dev, mlv);
        if (!reg) {
                NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
                return 5;
        }

        bios_wr32(bios, reg,
                  tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
        value = (bios_rd32(bios, reg + 4) & mask) | data;
        bios_wr32(bios, reg + 4, value);
        bios_wr32(bios, reg, tmdsaddr);

        return 5;
}

static int
init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
                   struct init_exec *iexec)
{
        /*
         * INIT_ZM_TMDS_GROUP   opcode: 0x50 ('P')      (non-canon name)
         *
         * offset      (8 bit): opcode
         * offset + 1  (8 bit): magic lookup value
         * offset + 2  (8 bit): count
         * offset + 3  (8 bit): addr 1
         * offset + 4  (8 bit): data 1
         * ...
         *
         * For each of "count" TMDS address and data pairs write "data n" to
         * "addr n".  "magic lookup value" determines which TMDS base address
         * register is used -- see get_tmds_index_reg()
         */

        struct drm_device *dev = bios->dev;
        uint8_t mlv = bios->data[offset + 1];
        uint8_t count = bios->data[offset + 2];
        int len = 3 + count * 2;
        uint32_t reg;
        int i;

        if (!iexec->execute)
                return len;

        BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
                offset, mlv, count);

        reg = get_tmds_index_reg(bios->dev, mlv);
        if (!reg) {
                NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
                return len;
        }

        for (i = 0; i < count; i++) {
                uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
                uint8_t tmdsdata = bios->data[offset + 4 + i * 2];

                bios_wr32(bios, reg + 4, tmdsdata);
                bios_wr32(bios, reg, tmdsaddr);
        }

        return len;
}

static int
init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
                      struct init_exec *iexec)
{
        /*
         * INIT_CR_INDEX_ADDRESS_LATCHED   opcode: 0x51 ('Q')
         *
         * offset      (8 bit): opcode
         * offset + 1  (8 bit): CRTC index1
         * offset + 2  (8 bit): CRTC index2
         * offset + 3  (8 bit): baseaddr
         * offset + 4  (8 bit): count
         * offset + 5  (8 bit): data 1
         * ...
         *
         * For each of "count" address and data pairs, write "baseaddr + n" to
         * "CRTC index1" and "data n" to "CRTC index2"
         * Once complete, restore initial value read from "CRTC index1"
         */
        uint8_t crtcindex1 = bios->data[offset + 1];
        uint8_t crtcindex2 = bios->data[offset + 2];
        uint8_t baseaddr = bios->data[offset + 3];
        uint8_t count = bios->data[offset + 4];
        int len = 5 + count;
        uint8_t oldaddr, data;
        int i;

        if (!iexec->execute)
                return len;

        BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
                      "BaseAddr: 0x%02X, Count: 0x%02X\n",
                offset, crtcindex1, crtcindex2, baseaddr, count);

        oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);

        for (i = 0; i < count; i++) {
                bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
                                     baseaddr + i);
                data = bios->data[offset + 5 + i];
                bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
        }

        bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);

        return len;
}

static int
init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_CR   opcode: 0x52 ('R')
         *
         * offset      (8  bit): opcode
         * offset + 1  (8  bit): CRTC index
         * offset + 2  (8  bit): mask
         * offset + 3  (8  bit): data
         *
         * Assign the value of at "CRTC index" ANDed with mask and ORed with
         * data back to "CRTC index"
         */

        uint8_t crtcindex = bios->data[offset + 1];
        uint8_t mask = bios->data[offset + 2];
        uint8_t data = bios->data[offset + 3];
        uint8_t value;

        if (!iexec->execute)
                return 4;

        BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
                offset, crtcindex, mask, data);

        value  = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
        value |= data;
        bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);

        return 4;
}

static int
init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_ZM_CR   opcode: 0x53 ('S')
         *
         * offset      (8 bit): opcode
         * offset + 1  (8 bit): CRTC index
         * offset + 2  (8 bit): value
         *
         * Assign "value" to CRTC register with index "CRTC index".
         */

        uint8_t crtcindex = ROM32(bios->data[offset + 1]);
        uint8_t data = bios->data[offset + 2];

        if (!iexec->execute)
                return 3;

        bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);

        return 3;
}

static int
init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_ZM_CR_GROUP   opcode: 0x54 ('T')
         *
         * offset      (8 bit): opcode
         * offset + 1  (8 bit): count
         * offset + 2  (8 bit): CRTC index 1
         * offset + 3  (8 bit): value 1
         * ...
         *
         * For "count", assign "value n" to CRTC register with index
         * "CRTC index n".
         */

        uint8_t count = bios->data[offset + 1];
        int len = 2 + count * 2;
        int i;

        if (!iexec->execute)
                return len;

        for (i = 0; i < count; i++)
                init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);

        return len;
}

static int
init_condition_time(struct nvbios *bios, uint16_t offset,
                    struct init_exec *iexec)
{
        /*
         * INIT_CONDITION_TIME   opcode: 0x56 ('V')
         *
         * offset      (8 bit): opcode
         * offset + 1  (8 bit): condition number
         * offset + 2  (8 bit): retries / 50
         *
         * Check condition "condition number" in the condition table.
         * Bios code then sleeps for 2ms if the condition is not met, and
         * repeats up to "retries" times, but on one C51 this has proved
         * insufficient.  In mmiotraces the driver sleeps for 20ms, so we do
         * this, and bail after "retries" times, or 2s, whichever is less.
         * If still not met after retries, clear execution flag for this table.
         */

        uint8_t cond = bios->data[offset + 1];
        uint16_t retries = bios->data[offset + 2] * 50;
        unsigned cnt;

        if (!iexec->execute)
                return 3;

        if (retries > 100)
                retries = 100;

        BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
                offset, cond, retries);

        if (!bios->execute) /* avoid 2s delays when "faking" execution */
                retries = 1;

        for (cnt = 0; cnt < retries; cnt++) {
                if (bios_condition_met(bios, offset, cond)) {
                        BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
                                                                offset);
                        break;
                } else {
                        BIOSLOG(bios, "0x%04X: "
                                "Condition not met, sleeping for 20ms\n",
                                                                offset);
                        msleep(20);
                }
        }

        if (!bios_condition_met(bios, offset, cond)) {
                NV_WARN(bios->dev,
                        "0x%04X: Condition still not met after %dms, "
                        "skipping following opcodes\n", offset, 20 * retries);
                iexec->execute = false;
        }

        return 3;
}

static int
init_ltime(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_LTIME   opcode: 0x57 ('V')
         *
         * offset      (8  bit): opcode
         * offset + 1  (16 bit): time
         *
         * Sleep for "time" milliseconds.
         */

        unsigned time = ROM16(bios->data[offset + 1]);

        if (!iexec->execute)
                return 3;

        BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X milliseconds\n",
                offset, time);

        msleep(time);

        return 3;
}

static int
init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
                     struct init_exec *iexec)
{
        /*
         * INIT_ZM_REG_SEQUENCE   opcode: 0x58 ('X')
         *
         * offset      (8  bit): opcode
         * offset + 1  (32 bit): base register
         * offset + 5  (8  bit): count
         * offset + 6  (32 bit): value 1
         * ...
         *
         * Starting at offset + 6 there are "count" 32 bit values.
         * For "count" iterations set "base register" + 4 * current_iteration
         * to "value current_iteration"
         */

        uint32_t basereg = ROM32(bios->data[offset + 1]);
        uint32_t count = bios->data[offset + 5];
        int len = 6 + count * 4;
        int i;

        if (!iexec->execute)
                return len;

        BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
                offset, basereg, count);

        for (i = 0; i < count; i++) {
                uint32_t reg = basereg + i * 4;
                uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);

                bios_wr32(bios, reg, data);
        }

        return len;
}

static int
init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_SUB_DIRECT   opcode: 0x5B ('[')
         *
         * offset      (8  bit): opcode
         * offset + 1  (16 bit): subroutine offset (in bios)
         *
         * Calls a subroutine that will execute commands until INIT_DONE
         * is found.
         */

        uint16_t sub_offset = ROM16(bios->data[offset + 1]);

        if (!iexec->execute)

                return 3;

        BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
                offset, sub_offset);

        parse_init_table(bios, sub_offset, iexec);

        BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);

        return 3;
}

static int
init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_I2C_IF   opcode: 0x5E ('^')
         *
         * offset      (8 bit): opcode
         * offset + 1  (8 bit): DCB I2C table entry index
         * offset + 2  (8 bit): I2C slave address
         * offset + 3  (8 bit): I2C register
         * offset + 4  (8 bit): mask
         * offset + 5  (8 bit): data
         *
         * Read the register given by "I2C register" on the device addressed
         * by "I2C slave address" on the I2C bus given by "DCB I2C table
         * entry index". Compare the result AND "mask" to "data".
         * If they're not equal, skip subsequent opcodes until condition is
         * inverted (INIT_NOT), or we hit INIT_RESUME
         */

        uint8_t i2c_index = bios->data[offset + 1];
        uint8_t i2c_address = bios->data[offset + 2] >> 1;
        uint8_t reg = bios->data[offset + 3];
        uint8_t mask = bios->data[offset + 4];
        uint8_t data = bios->data[offset + 5];
        struct nouveau_i2c_chan *chan;
        union i2c_smbus_data val;
        int ret;

        /* no execute check by design */

        BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
                offset, i2c_index, i2c_address);

        chan = init_i2c_device_find(bios->dev, i2c_index);
        if (!chan)
                return -ENODEV;

        ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
                             I2C_SMBUS_READ, reg,
                             I2C_SMBUS_BYTE_DATA, &val);
        if (ret < 0) {
                BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: [no device], "
                              "Mask: 0x%02X, Data: 0x%02X\n",
                        offset, reg, mask, data);
                iexec->execute = 0;
                return 6;
        }

        BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
                      "Mask: 0x%02X, Data: 0x%02X\n",
                offset, reg, val.byte, mask, data);

        iexec->execute = ((val.byte & mask) == data);

        return 6;
}

static int
init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_COPY_NV_REG   opcode: 0x5F ('_')
         *
         * offset      (8  bit): opcode
         * offset + 1  (32 bit): src reg
         * offset + 5  (8  bit): shift
         * offset + 6  (32 bit): src mask
         * offset + 10 (32 bit): xor
         * offset + 14 (32 bit): dst reg
         * offset + 18 (32 bit): dst mask
         *
         * Shift REGVAL("src reg") right by (signed) "shift", AND result with
         * "src mask", then XOR with "xor". Write this OR'd with
         * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
         */

        uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
        uint8_t shift = bios->data[offset + 5];
        uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
        uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
        uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
        uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
        uint32_t srcvalue, dstvalue;

        if (!iexec->execute)
                return 22;

        BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
                      "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
                offset, srcreg, shift, srcmask, xor, dstreg, dstmask);

        srcvalue = bios_rd32(bios, srcreg);

        if (shift < 0x80)
                srcvalue >>= shift;
        else
                srcvalue <<= (0x100 - shift);

        srcvalue = (srcvalue & srcmask) ^ xor;

        dstvalue = bios_rd32(bios, dstreg) & dstmask;

        bios_wr32(bios, dstreg, dstvalue | srcvalue);

        return 22;
}

static int
init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_ZM_INDEX_IO   opcode: 0x62 ('b')
         *
         * offset      (8  bit): opcode
         * offset + 1  (16 bit): CRTC port
         * offset + 3  (8  bit): CRTC index
         * offset + 4  (8  bit): data
         *
         * Write "data" to index "CRTC index" of "CRTC port"
         */
        uint16_t crtcport = ROM16(bios->data[offset + 1]);
        uint8_t crtcindex = bios->data[offset + 3];
        uint8_t data = bios->data[offset + 4];

        if (!iexec->execute)
                return 5;

        bios_idxprt_wr(bios, crtcport, crtcindex, data);

        return 5;
}

static inline void
bios_md32(struct nvbios *bios, uint32_t reg,
          uint32_t mask, uint32_t val)
{
        bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val);
}

static uint32_t
peek_fb(struct drm_device *dev, struct io_mapping *fb,
        uint32_t off)
{
        uint32_t val = 0;

        if (off < pci_resource_len(dev->pdev, 1)) {
                uint8_t __iomem *p =
                        io_mapping_map_atomic_wc(fb, off & PAGE_MASK);

                val = ioread32(p + (off & ~PAGE_MASK));

                io_mapping_unmap_atomic(p);
        }

        return val;
}

static void
poke_fb(struct drm_device *dev, struct io_mapping *fb,
        uint32_t off, uint32_t val)
{
        if (off < pci_resource_len(dev->pdev, 1)) {
                uint8_t __iomem *p =
                        io_mapping_map_atomic_wc(fb, off & PAGE_MASK);

                iowrite32(val, p + (off & ~PAGE_MASK));
                wmb();

                io_mapping_unmap_atomic(p);
        }
}

static inline bool
read_back_fb(struct drm_device *dev, struct io_mapping *fb,
             uint32_t off, uint32_t val)
{
        poke_fb(dev, fb, off, val);
        return val == peek_fb(dev, fb, off);
}

static int
nv04_init_compute_mem(struct nvbios *bios)
{
        struct drm_device *dev = bios->dev;
        uint32_t patt = 0xdeadbeef;
        struct io_mapping *fb;
        int i;

        /* Map the framebuffer aperture */
        fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
                                  pci_resource_len(dev->pdev, 1));
        if (!fb)
                return -ENOMEM;

        /* Sequencer and refresh off */
        NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
        bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);

        bios_md32(bios, NV04_PFB_BOOT_0, ~0,
                  NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
                  NV04_PFB_BOOT_0_RAM_WIDTH_128 |
                  NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);

        for (i = 0; i < 4; i++)
                poke_fb(dev, fb, 4 * i, patt);

        poke_fb(dev, fb, 0x400000, patt + 1);

        if (peek_fb(dev, fb, 0) == patt + 1) {
                bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
                          NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
                bios_md32(bios, NV04_PFB_DEBUG_0,
                          NV04_PFB_DEBUG_0_REFRESH_OFF, 0);

                for (i = 0; i < 4; i++)
                        poke_fb(dev, fb, 4 * i, patt);

                if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff))
                        bios_md32(bios, NV04_PFB_BOOT_0,
                                  NV04_PFB_BOOT_0_RAM_WIDTH_128 |
                                  NV04_PFB_BOOT_0_RAM_AMOUNT,
                                  NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);

        } else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) !=
                   (patt & 0xffff0000)) {
                bios_md32(bios, NV04_PFB_BOOT_0,
                          NV04_PFB_BOOT_0_RAM_WIDTH_128 |
                          NV04_PFB_BOOT_0_RAM_AMOUNT,
                          NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);

        } else if (peek_fb(dev, fb, 0) != patt) {
                if (read_back_fb(dev, fb, 0x800000, patt))
                        bios_md32(bios, NV04_PFB_BOOT_0,
                                  NV04_PFB_BOOT_0_RAM_AMOUNT,
                                  NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
                else
                        bios_md32(bios, NV04_PFB_BOOT_0,
                                  NV04_PFB_BOOT_0_RAM_AMOUNT,
                                  NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);

                bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
                          NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);

        } else if (!read_back_fb(dev, fb, 0x800000, patt)) {
                bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
                          NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);

        }

        /* Refresh on, sequencer on */
        bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
        NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);

        io_mapping_free(fb);
        return 0;
}

static const uint8_t *
nv05_memory_config(struct nvbios *bios)
{
        /* Defaults for BIOSes lacking a memory config table */
        static const uint8_t default_config_tab[][2] = {
                { 0x24, 0x00 },
                { 0x28, 0x00 },
                { 0x24, 0x01 },
                { 0x1f, 0x00 },
                { 0x0f, 0x00 },
                { 0x17, 0x00 },
                { 0x06, 0x00 },
                { 0x00, 0x00 }
        };
        int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) &
                 NV_PEXTDEV_BOOT_0_RAMCFG) >> 2;

        if (bios->legacy.mem_init_tbl_ptr)
                return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i];
        else
                return default_config_tab[i];
}

static int
nv05_init_compute_mem(struct nvbios *bios)
{
        struct drm_device *dev = bios->dev;
        const uint8_t *ramcfg = nv05_memory_config(bios);
        uint32_t patt = 0xdeadbeef;
        struct io_mapping *fb;
        int i, v;

        /* Map the framebuffer aperture */
        fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
                                  pci_resource_len(dev->pdev, 1));
        if (!fb)
                return -ENOMEM;

        /* Sequencer off */
        NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);

        if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
                goto out;

        bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);

        /* If present load the hardcoded scrambling table */
        if (bios->legacy.mem_init_tbl_ptr) {
                uint32_t *scramble_tab = (uint32_t *)&bios->data[
                        bios->legacy.mem_init_tbl_ptr + 0x10];

                for (i = 0; i < 8; i++)
                        bios_wr32(bios, NV04_PFB_SCRAMBLE(i),
                                  ROM32(scramble_tab[i]));
        }

        /* Set memory type/width/length defaults depending on the straps */
        bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);

        if (ramcfg[1] & 0x80)
                bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);

        bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
        bios_md32(bios, NV04_PFB_CFG1, 0, 1);

        /* Probe memory bus width */
        for (i = 0; i < 4; i++)
                poke_fb(dev, fb, 4 * i, patt);

        if (peek_fb(dev, fb, 0xc) != patt)
                bios_md32(bios, NV04_PFB_BOOT_0,
                          NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);

        /* Probe memory length */
        v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;

        if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
            (!read_back_fb(dev, fb, 0x1000000, ++patt) ||
             !read_back_fb(dev, fb, 0, ++patt)))
                bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
                          NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);

        if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
            !read_back_fb(dev, fb, 0x800000, ++patt))
                bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
                          NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);

        if (!read_back_fb(dev, fb, 0x400000, ++patt))
                bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
                          NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);

out:
        /* Sequencer on */
        NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);

        io_mapping_free(fb);
        return 0;
}

static int
nv10_init_compute_mem(struct nvbios *bios)
{
        struct drm_device *dev = bios->dev;
        struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
        const int mem_width[] = { 0x10, 0x00, 0x20 };
        const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2);
        uint32_t patt = 0xdeadbeef;
        struct io_mapping *fb;
        int i, j, k;

        /* Map the framebuffer aperture */
        fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
                                  pci_resource_len(dev->pdev, 1));
        if (!fb)
                return -ENOMEM;

        bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);

        /* Probe memory bus width */
        for (i = 0; i < mem_width_count; i++) {
                bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]);

                for (j = 0; j < 4; j++) {
                        for (k = 0; k < 4; k++)
                                poke_fb(dev, fb, 0x1c, 0);

                        poke_fb(dev, fb, 0x1c, patt);
                        poke_fb(dev, fb, 0x3c, 0);

                        if (peek_fb(dev, fb, 0x1c) == patt)
                                goto mem_width_found;
                }
        }

mem_width_found:
        patt <<= 1;

        /* Probe amount of installed memory */
        for (i = 0; i < 4; i++) {
                int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000;

                poke_fb(dev, fb, off, patt);
                poke_fb(dev, fb, 0, 0);

                peek_fb(dev, fb, 0);
                peek_fb(dev, fb, 0);
                peek_fb(dev, fb, 0);
                peek_fb(dev, fb, 0);

                if (peek_fb(dev, fb, off) == patt)
                        goto amount_found;
        }

        /* IC missing - disable the upper half memory space. */
        bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0);

amount_found:
        io_mapping_free(fb);
        return 0;
}

static int
nv20_init_compute_mem(struct nvbios *bios)
{
        struct drm_device *dev = bios->dev;
        struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
        uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900);
        uint32_t amount, off;
        struct io_mapping *fb;

        /* Map the framebuffer aperture */
        fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
                                  pci_resource_len(dev->pdev, 1));
        if (!fb)
                return -ENOMEM;

        bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);

        /* Allow full addressing */
        bios_md32(bios, NV04_PFB_CFG0, 0, mask);

        amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
        for (off = amount; off > 0x2000000; off -= 0x2000000)
                poke_fb(dev, fb, off - 4, off);

        amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
        if (amount != peek_fb(dev, fb, amount - 4))
                /* IC missing - disable the upper half memory space. */
                bios_md32(bios, NV04_PFB_CFG0, mask, 0);

        io_mapping_free(fb);
        return 0;
}

static int
init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_COMPUTE_MEM   opcode: 0x63 ('c')
         *
         * offset      (8 bit): opcode
         *
         * This opcode is meant to set the PFB memory config registers
         * appropriately so that we can correctly calculate how much VRAM it
         * has (on nv10 and better chipsets the amount of installed VRAM is
         * subsequently reported in NV_PFB_CSTATUS (0x10020C)).
         *
         * The implementation of this opcode in general consists of several
         * parts:
         *
         * 1) Determination of memory type and density. Only necessary for
         *    really old chipsets, the memory type reported by the strap bits
         *    (0x101000) is assumed to be accurate on nv05 and newer.
         *
         * 2) Determination of the memory bus width. Usually done by a cunning
         *    combination of writes to offsets 0x1c and 0x3c in the fb, and
         *    seeing whether the written values are read back correctly.
         *
         *    Only necessary on nv0x-nv1x and nv34, on the other cards we can
         *    trust the straps.
         *
         * 3) Determination of how many of the card's RAM pads have ICs
         *    attached, usually done by a cunning combination of writes to an
         *    offset slightly less than the maximum memory reported by
         *    NV_PFB_CSTATUS, then seeing if the test pattern can be read back.
         *
         * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io
         * logs of the VBIOS and kmmio traces of the binary driver POSTing the
         * card show nothing being done for this opcode. Why is it still listed
         * in the table?!
         */

        /* no iexec->execute check by design */

        struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
        int ret;

        if (dev_priv->chipset >= 0x40 ||
            dev_priv->chipset == 0x1a ||
            dev_priv->chipset == 0x1f)
                ret = 0;
        else if (dev_priv->chipset >= 0x20 &&
                 dev_priv->chipset != 0x34)
                ret = nv20_init_compute_mem(bios);
        else if (dev_priv->chipset >= 0x10)
                ret = nv10_init_compute_mem(bios);
        else if (dev_priv->chipset >= 0x5)
                ret = nv05_init_compute_mem(bios);
        else
                ret = nv04_init_compute_mem(bios);

        if (ret)
                return ret;

        return 1;
}

static int
init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_RESET   opcode: 0x65 ('e')
         *
         * offset      (8  bit): opcode
         * offset + 1  (32 bit): register
         * offset + 5  (32 bit): value1
         * offset + 9  (32 bit): value2
         *
         * Assign "value1" to "register", then assign "value2" to "register"
         */

        uint32_t reg = ROM32(bios->data[offset + 1]);
        uint32_t value1 = ROM32(bios->data[offset + 5]);
        uint32_t value2 = ROM32(bios->data[offset + 9]);
        uint32_t pci_nv_19, pci_nv_20;

        /* no iexec->execute check by design */

        pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
        bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00);

        bios_wr32(bios, reg, value1);

        udelay(10);

        bios_wr32(bios, reg, value2);
        bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);

        pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
        pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;     /* 0xfffffffe */
        bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);

        return 13;
}

static int
init_configure_mem(struct nvbios *bios, uint16_t offset,
                   struct init_exec *iexec)
{
        /*
         * INIT_CONFIGURE_MEM   opcode: 0x66 ('f')
         *
         * offset      (8 bit): opcode
         *
         * Equivalent to INIT_DONE on bios version 3 or greater.
         * For early bios versions, sets up the memory registers, using values
         * taken from the memory init table
         */

        /* no iexec->execute check by design */

        uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
        uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
        uint32_t reg, data;

        if (bios->major_version > 2)
                return 0;

        bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
                       bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);

        if (bios->data[meminitoffs] & 1)
                seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;

        for (reg = ROM32(bios->data[seqtbloffs]);
             reg != 0xffffffff;
             reg = ROM32(bios->data[seqtbloffs += 4])) {

                switch (reg) {
                case NV04_PFB_PRE:
                        data = NV04_PFB_PRE_CMD_PRECHARGE;
                        break;
                case NV04_PFB_PAD:
                        data = NV04_PFB_PAD_CKE_NORMAL;
                        break;
                case NV04_PFB_REF:
                        data = NV04_PFB_REF_CMD_REFRESH;
                        break;
                default:
                        data = ROM32(bios->data[meminitdata]);
                        meminitdata += 4;
                        if (data == 0xffffffff)
                                continue;
                }

                bios_wr32(bios, reg, data);
        }

        return 1;
}

static int
init_configure_clk(struct nvbios *bios, uint16_t offset,
                   struct init_exec *iexec)
{
        /*
         * INIT_CONFIGURE_CLK   opcode: 0x67 ('g')
         *
         * offset      (8 bit): opcode
         *
         * Equivalent to INIT_DONE on bios version 3 or greater.
         * For early bios versions, sets up the NVClk and MClk PLLs, using
         * values taken from the memory init table
         */

        /* no iexec->execute check by design */

        uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
        int clock;

        if (bios->major_version > 2)
                return 0;

        clock = ROM16(bios->data[meminitoffs + 4]) * 10;
        setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);

        clock = ROM16(bios->data[meminitoffs + 2]) * 10;
        if (bios->data[meminitoffs] & 1) /* DDR */
                clock *= 2;
        setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);

        return 1;
}

static int
init_configure_preinit(struct nvbios *bios, uint16_t offset,
                       struct init_exec *iexec)
{
        /*
         * INIT_CONFIGURE_PREINIT   opcode: 0x68 ('h')
         *
         * offset      (8 bit): opcode
         *
         * Equivalent to INIT_DONE on bios version 3 or greater.
         * For early bios versions, does early init, loading ram and crystal
         * configuration from straps into CR3C
         */

        /* no iexec->execute check by design */

        uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
        uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & 0x40) >> 6;

        if (bios->major_version > 2)
                return 0;

        bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
                             NV_CIO_CRE_SCRATCH4__INDEX, cr3c);

        return 1;
}

static int
init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_IO   opcode: 0x69 ('i')
         *
         * offset      (8  bit): opcode
         * offset + 1  (16 bit): CRTC port
         * offset + 3  (8  bit): mask
         * offset + 4  (8  bit): data
         *
         * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
         */

        struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
        uint16_t crtcport = ROM16(bios->data[offset + 1]);
        uint8_t mask = bios->data[offset + 3];
        uint8_t data = bios->data[offset + 4];

        if (!iexec->execute)
                return 5;

        BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
                offset, crtcport, mask, data);

        /*
         * I have no idea what this does, but NVIDIA do this magic sequence
         * in the places where this INIT_IO happens..
         */
        if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
                int i;

                bios_wr32(bios, 0x614100, (bios_rd32(
                          bios, 0x614100) & 0x0fffffff) | 0x00800000);

                bios_wr32(bios, 0x00e18c, bios_rd32(
                          bios, 0x00e18c) | 0x00020000);

                bios_wr32(bios, 0x614900, (bios_rd32(
                          bios, 0x614900) & 0x0fffffff) | 0x00800000);

                bios_wr32(bios, 0x000200, bios_rd32(
                          bios, 0x000200) & ~0x40000000);

                mdelay(10);

                bios_wr32(bios, 0x00e18c, bios_rd32(
                          bios, 0x00e18c) & ~0x00020000);

                bios_wr32(bios, 0x000200, bios_rd32(
                          bios, 0x000200) | 0x40000000);

                bios_wr32(bios, 0x614100, 0x00800018);
                bios_wr32(bios, 0x614900, 0x00800018);

                mdelay(10);

                bios_wr32(bios, 0x614100, 0x10000018);
                bios_wr32(bios, 0x614900, 0x10000018);

                for (i = 0; i < 3; i++)
                        bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
                                  bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);

                for (i = 0; i < 2; i++)
                        bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
                                  bios, 0x614300 + (i*0x800)) & 0xfffff0f0);

                for (i = 0; i < 3; i++)
                        bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
                                  bios, 0x614380 + (i*0x800)) & 0xfffff0f0);

                for (i = 0; i < 2; i++)
                        bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
                                  bios, 0x614200 + (i*0x800)) & 0xfffffff0);

                for (i = 0; i < 2; i++)
                        bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
                                  bios, 0x614108 + (i*0x800)) & 0x0fffffff);
                return 5;
        }

        bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
                                                                        data);
        return 5;
}

static int
init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_SUB   opcode: 0x6B ('k')
         *
         * offset      (8 bit): opcode
         * offset + 1  (8 bit): script number
         *
         * Execute script number "script number", as a subroutine
         */

        uint8_t sub = bios->data[offset + 1];

        if (!iexec->execute)
                return 2;

        BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);

        parse_init_table(bios,
                         ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
                         iexec);

        BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);

        return 2;
}

static int
init_ram_condition(struct nvbios *bios, uint16_t offset,
                   struct init_exec *iexec)
{
        /*
         * INIT_RAM_CONDITION   opcode: 0x6D ('m')
         *
         * offset      (8 bit): opcode
         * offset + 1  (8 bit): mask
         * offset + 2  (8 bit): cmpval
         *
         * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval".
         * If condition not met skip subsequent opcodes until condition is
         * inverted (INIT_NOT), or we hit INIT_RESUME
         */

        uint8_t mask = bios->data[offset + 1];
        uint8_t cmpval = bios->data[offset + 2];
        uint8_t data;

        if (!iexec->execute)
                return 3;

        data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask;

        BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
                offset, data, cmpval);

        if (data == cmpval)
                BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
        else {
                BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
                iexec->execute = false;
        }

        return 3;
}

static int
init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_NV_REG   opcode: 0x6E ('n')
         *
         * offset      (8  bit): opcode
         * offset + 1  (32 bit): register
         * offset + 5  (32 bit): mask
         * offset + 9  (32 bit): data
         *
         * Assign ((REGVAL("register") & "mask") | "data") to "register"
         */

        uint32_t reg = ROM32(bios->data[offset + 1]);
        uint32_t mask = ROM32(bios->data[offset + 5]);
        uint32_t data = ROM32(bios->data[offset + 9]);

        if (!iexec->execute)
                return 13;

        BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
                offset, reg, mask, data);

        bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);

        return 13;
}

static int
init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_MACRO   opcode: 0x6F ('o')
         *
         * offset      (8 bit): opcode
         * offset + 1  (8 bit): macro number
         *
         * Look up macro index "macro number" in the macro index table.
         * The macro index table entry has 1 byte for the index in the macro
         * table, and 1 byte for the number of times to repeat the macro.
         * The macro table entry has 4 bytes for the register address and
         * 4 bytes for the value to write to that register
         */

        uint8_t macro_index_tbl_idx = bios->data[offset + 1];
        uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
        uint8_t macro_tbl_idx = bios->data[tmp];
        uint8_t count = bios->data[tmp + 1];
        uint32_t reg, data;
        int i;

        if (!iexec->execute)
                return 2;

        BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
                      "Count: 0x%02X\n",
                offset, macro_index_tbl_idx, macro_tbl_idx, count);

        for (i = 0; i < count; i++) {
                uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;

                reg = ROM32(bios->data[macroentryptr]);
                data = ROM32(bios->data[macroentryptr + 4]);

                bios_wr32(bios, reg, data);
        }

        return 2;
}

static int
init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_DONE   opcode: 0x71 ('q')
         *
         * offset      (8  bit): opcode
         *
         * End the current script
         */

        /* mild retval abuse to stop parsing this table */
        return 0;
}

static int
init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_RESUME   opcode: 0x72 ('r')
         *
         * offset      (8  bit): opcode
         *
         * End the current execute / no-execute condition
         */

        if (iexec->execute)
                return 1;

        iexec->execute = true;
        BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);

        return 1;
}

static int
init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_TIME   opcode: 0x74 ('t')
         *
         * offset      (8  bit): opcode
         * offset + 1  (16 bit): time
         *
         * Sleep for "time" microseconds.
         */

        unsigned time = ROM16(bios->data[offset + 1]);

        if (!iexec->execute)
                return 3;

        BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
                offset, time);

        if (time < 1000)
                udelay(time);
        else
                msleep((time + 900) / 1000);

        return 3;
}

static int
init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
{
        /*
         * INIT_CONDITION   opcode: 0x75 ('u')
         *
         * offset      (8 bit): opcode
         * offset + 1  (8 bit): condition number
         *
         * Check condition "condition number" in the condition table.
         * If condition not met skip subsequent opcodes until condition is
         * inverted (INIT_NOT), or we hit INIT_RESUME
         */

        uint8_t cond = bios->data[offset + 1];

        if (!iexec->execute)
                return 2;

        BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);

        if (bios_condition_met(bios, offset, cond))
                BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
        else {
                BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
                iexec->execute = false;
        }

        return 2;
}