LXR linux/drivers/gpu/drm/nouveau/nouveau

   1/*
   2 * Copyright 2007-2008 Nouveau Project
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21 * DEALINGS IN THE SOFTWARE.
  22 */
  23
  24#ifndef __NOUVEAU_BIOS_H__
  25#define __NOUVEAU_BIOS_H__
  26
  27#include "nvreg.h"
  28#include "nouveau_i2c.h"
  29
  30#define DCB_MAX_NUM_ENTRIES 16
  31#define DCB_MAX_NUM_I2C_ENTRIES 16
  32#define DCB_MAX_NUM_GPIO_ENTRIES 32
  33#define DCB_MAX_NUM_CONNECTOR_ENTRIES 16
  34
  35#define DCB_LOC_ON_CHIP 0
  36
  37#define ROM16(x) le16_to_cpu(*(uint16_t *)&(x))
  38#define ROM32(x) le32_to_cpu(*(uint32_t *)&(x))
  39#define ROMPTR(bios, x) (ROM16(x) ? &(bios)->data[ROM16(x)] : NULL)
  40
  41struct bit_entry {
  42        uint8_t  id;
  43        uint8_t  version;
  44        uint16_t length;
  45        uint16_t offset;
  46        uint8_t *data;
  47};
  48
  49int bit_table(struct drm_device *, u8 id, struct bit_entry *);
  50
  51struct dcb_i2c_entry {
  52        uint32_t entry;
  53        uint8_t port_type;
  54        uint8_t read, write;
  55        struct nouveau_i2c_chan *chan;
  56};
  57
  58enum dcb_gpio_tag {
  59        DCB_GPIO_TVDAC0 = 0xc,
  60        DCB_GPIO_TVDAC1 = 0x2d,
  61};
  62
  63struct dcb_gpio_entry {
  64        enum dcb_gpio_tag tag;
  65        int line;
  66        bool invert;
  67        uint32_t entry;
  68        uint8_t state_default;
  69        uint8_t state[2];
  70};
  71
  72struct dcb_gpio_table {
  73        int entries;
  74        struct dcb_gpio_entry entry[DCB_MAX_NUM_GPIO_ENTRIES];
  75};
  76
  77enum dcb_connector_type {
  78        DCB_CONNECTOR_VGA = 0x00,
  79        DCB_CONNECTOR_TV_0 = 0x10,
  80        DCB_CONNECTOR_TV_1 = 0x11,
  81        DCB_CONNECTOR_TV_3 = 0x13,
  82        DCB_CONNECTOR_DVI_I = 0x30,
  83        DCB_CONNECTOR_DVI_D = 0x31,
  84        DCB_CONNECTOR_LVDS = 0x40,
  85        DCB_CONNECTOR_DP = 0x46,
  86        DCB_CONNECTOR_eDP = 0x47,
  87        DCB_CONNECTOR_HDMI_0 = 0x60,
  88        DCB_CONNECTOR_HDMI_1 = 0x61,
  89        DCB_CONNECTOR_NONE = 0xff
  90};
  91
  92struct dcb_connector_table_entry {
  93        uint8_t index;
  94        uint32_t entry;
  95        enum dcb_connector_type type;
  96        uint8_t index2;
  97        uint8_t gpio_tag;
  98        void *drm;
  99};
 100
 101struct dcb_connector_table {
 102        int entries;
 103        struct dcb_connector_table_entry entry[DCB_MAX_NUM_CONNECTOR_ENTRIES];
 104};
 105
 106enum dcb_type {
 107        OUTPUT_ANALOG = 0,
 108        OUTPUT_TV = 1,
 109        OUTPUT_TMDS = 2,
 110        OUTPUT_LVDS = 3,
 111        OUTPUT_DP = 6,
 112        OUTPUT_EOL = 14, /* DCB 4.0+, appears to be end-of-list */
 113        OUTPUT_ANY = -1
 114};
 115
 116struct dcb_entry {
 117        int index;      /* may not be raw dcb index if merging has happened */
 118        enum dcb_type type;
 119        uint8_t i2c_index;
 120        uint8_t heads;
 121        uint8_t connector;
 122        uint8_t bus;
 123        uint8_t location;
 124        uint8_t or;
 125        bool duallink_possible;
 126        union {
 127                struct sor_conf {
 128                        int link;
 129                } sorconf;
 130                struct {
 131                        int maxfreq;
 132                } crtconf;
 133                struct {
 134                        struct sor_conf sor;
 135                        bool use_straps_for_mode;
 136                        bool use_acpi_for_edid;
 137                        bool use_power_scripts;
 138                } lvdsconf;
 139                struct {
 140                        bool has_component_output;
 141                } tvconf;
 142                struct {
 143                        struct sor_conf sor;
 144                        int link_nr;
 145                        int link_bw;
 146                } dpconf;
 147                struct {
 148                        struct sor_conf sor;
 149                        int slave_addr;
 150                } tmdsconf;
 151        };
 152        bool i2c_upper_default;
 153};
 154
 155struct dcb_table {
 156        uint8_t version;
 157
 158        int entries;
 159        struct dcb_entry entry[DCB_MAX_NUM_ENTRIES];
 160
 161        uint8_t *i2c_table;
 162        uint8_t i2c_default_indices;
 163        struct dcb_i2c_entry i2c[DCB_MAX_NUM_I2C_ENTRIES];
 164
 165        uint16_t gpio_table_ptr;
 166        struct dcb_gpio_table gpio;
 167        uint16_t connector_table_ptr;
 168        struct dcb_connector_table connector;
 169};
 170
 171enum nouveau_or {
 172        OUTPUT_A = (1 << 0),
 173        OUTPUT_B = (1 << 1),
 174        OUTPUT_C = (1 << 2)
 175};
 176
 177enum LVDS_script {
 178        /* Order *does* matter here */
 179        LVDS_INIT = 1,
 180        LVDS_RESET,
 181        LVDS_BACKLIGHT_ON,
 182        LVDS_BACKLIGHT_OFF,
 183        LVDS_PANEL_ON,
 184        LVDS_PANEL_OFF
 185};
 186
 187/* these match types in pll limits table version 0x40,
 188 * nouveau uses them on all chipsets internally where a
 189 * specific pll needs to be referenced, but the exact
 190 * register isn't known.
 191 */
 192enum pll_types {
 193        PLL_CORE   = 0x01,
 194        PLL_SHADER = 0x02,
 195        PLL_UNK03  = 0x03,
 196        PLL_MEMORY = 0x04,
 197        PLL_UNK05  = 0x05,
 198        PLL_UNK40  = 0x40,
 199        PLL_UNK41  = 0x41,
 200        PLL_UNK42  = 0x42,
 201        PLL_VPLL0  = 0x80,
 202        PLL_VPLL1  = 0x81,
 203        PLL_MAX    = 0xff
 204};
 205
 206struct pll_lims {
 207        u32 reg;
 208
 209        struct {
 210                int minfreq;
 211                int maxfreq;
 212                int min_inputfreq;
 213                int max_inputfreq;
 214
 215                uint8_t min_m;
 216                uint8_t max_m;
 217                uint8_t min_n;
 218                uint8_t max_n;
 219        } vco1, vco2;
 220
 221        uint8_t max_log2p;
 222        /*
 223         * for most pre nv50 cards setting a log2P of 7 (the common max_log2p
 224         * value) is no different to 6 (at least for vplls) so allowing the MNP
 225         * calc to use 7 causes the generated clock to be out by a factor of 2.
 226         * however, max_log2p cannot be fixed-up during parsing as the
 227         * unmodified max_log2p value is still needed for setting mplls, hence
 228         * an additional max_usable_log2p member
 229         */
 230        uint8_t max_usable_log2p;
 231        uint8_t log2p_bias;
 232
 233        uint8_t min_p;
 234        uint8_t max_p;
 235
 236        int refclk;
 237};
 238
 239struct nvbios {
 240        struct drm_device *dev;
 241        enum {
 242                NVBIOS_BMP,
 243                NVBIOS_BIT
 244        } type;
 245        uint16_t offset;
 246
 247        uint8_t chip_version;
 248
 249        uint32_t dactestval;
 250        uint32_t tvdactestval;
 251        uint8_t digital_min_front_porch;
 252        bool fp_no_ddc;
 253
 254        struct mutex lock;
 255
 256        uint8_t data[NV_PROM_SIZE];
 257        unsigned int length;
 258        bool execute;
 259
 260        uint8_t major_version;
 261        uint8_t feature_byte;
 262        bool is_mobile;
 263
 264        uint32_t fmaxvco, fminvco;
 265
 266        bool old_style_init;
 267        uint16_t init_script_tbls_ptr;
 268        uint16_t extra_init_script_tbl_ptr;
 269        uint16_t macro_index_tbl_ptr;
 270        uint16_t macro_tbl_ptr;
 271        uint16_t condition_tbl_ptr;
 272        uint16_t io_condition_tbl_ptr;
 273        uint16_t io_flag_condition_tbl_ptr;
 274        uint16_t init_function_tbl_ptr;
 275
 276        uint16_t pll_limit_tbl_ptr;
 277        uint16_t ram_restrict_tbl_ptr;
 278        uint8_t ram_restrict_group_count;
 279
 280        uint16_t some_script_ptr; /* BIT I + 14 */
 281        uint16_t init96_tbl_ptr; /* BIT I + 16 */
 282
 283        struct dcb_table dcb;
 284
 285        struct {
 286                int crtchead;
 287        } state;
 288
 289        struct {
 290                struct dcb_entry *output;
 291                uint16_t script_table_ptr;
 292                uint16_t dp_table_ptr;
 293        } display;
 294
 295        struct {
 296                uint16_t fptablepointer;        /* also used by tmds */
 297                uint16_t fpxlatetableptr;
 298                int xlatwidth;
 299                uint16_t lvdsmanufacturerpointer;
 300                uint16_t fpxlatemanufacturertableptr;
 301                uint16_t mode_ptr;
 302                uint16_t xlated_entry;
 303                bool power_off_for_reset;
 304                bool reset_after_pclk_change;
 305                bool dual_link;
 306                bool link_c_increment;
 307                bool if_is_24bit;
 308                int duallink_transition_clk;
 309                uint8_t strapless_is_24bit;
 310                uint8_t *edid;
 311
 312                /* will need resetting after suspend */
 313                int last_script_invoc;
 314                bool lvds_init_run;
 315        } fp;
 316
 317        struct {
 318                uint16_t output0_script_ptr;
 319                uint16_t output1_script_ptr;
 320        } tmds;
 321
 322        struct {
 323                uint16_t mem_init_tbl_ptr;
 324                uint16_t sdr_seq_tbl_ptr;
 325                uint16_t ddr_seq_tbl_ptr;
 326
 327                struct {
 328                        uint8_t crt, tv, panel;
 329                } i2c_indices;
 330
 331                uint16_t lvds_single_a_script_ptr;
 332        } legacy;
 333};
 334
 335#endif
 336