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25#include "drmP.h"
26
27#include "nouveau_drv.h"
28#include "nouveau_i2c.h"
29#include "nouveau_connector.h"
30#include "nouveau_encoder.h"
31
32static int
33auxch_rd(struct drm_encoder *encoder, int address, uint8_t *buf, int size)
34{
35 struct drm_device *dev = encoder->dev;
36 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
37 struct nouveau_i2c_chan *auxch;
38 int ret;
39
40 auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
41 if (!auxch)
42 return -ENODEV;
43
44 ret = nouveau_dp_auxch(auxch, 9, address, buf, size);
45 if (ret)
46 return ret;
47
48 return 0;
49}
50
51static int
52auxch_wr(struct drm_encoder *encoder, int address, uint8_t *buf, int size)
53{
54 struct drm_device *dev = encoder->dev;
55 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
56 struct nouveau_i2c_chan *auxch;
57 int ret;
58
59 auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
60 if (!auxch)
61 return -ENODEV;
62
63 ret = nouveau_dp_auxch(auxch, 8, address, buf, size);
64 return ret;
65}
66
67static int
68nouveau_dp_lane_count_set(struct drm_encoder *encoder, uint8_t cmd)
69{
70 struct drm_device *dev = encoder->dev;
71 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
72 uint32_t tmp;
73 int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
74
75 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
76 tmp &= ~(NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED |
77 NV50_SOR_DP_CTRL_LANE_MASK);
78 tmp |= ((1 << (cmd & DP_LANE_COUNT_MASK)) - 1) << 16;
79 if (cmd & DP_LANE_COUNT_ENHANCED_FRAME_EN)
80 tmp |= NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED;
81 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
82
83 return auxch_wr(encoder, DP_LANE_COUNT_SET, &cmd, 1);
84}
85
86static int
87nouveau_dp_link_bw_set(struct drm_encoder *encoder, uint8_t cmd)
88{
89 struct drm_device *dev = encoder->dev;
90 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
91 uint32_t tmp;
92 int reg = 0x614300 + (nv_encoder->or * 0x800);
93
94 tmp = nv_rd32(dev, reg);
95 tmp &= 0xfff3ffff;
96 if (cmd == DP_LINK_BW_2_7)
97 tmp |= 0x00040000;
98 nv_wr32(dev, reg, tmp);
99
100 return auxch_wr(encoder, DP_LINK_BW_SET, &cmd, 1);
101}
102
103static int
104nouveau_dp_link_train_set(struct drm_encoder *encoder, int pattern)
105{
106 struct drm_device *dev = encoder->dev;
107 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
108 uint32_t tmp;
109 uint8_t cmd;
110 int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
111 int ret;
112
113 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
114 tmp &= ~NV50_SOR_DP_CTRL_TRAINING_PATTERN;
115 tmp |= (pattern << 24);
116 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
117
118 ret = auxch_rd(encoder, DP_TRAINING_PATTERN_SET, &cmd, 1);
119 if (ret)
120 return ret;
121 cmd &= ~DP_TRAINING_PATTERN_MASK;
122 cmd |= (pattern & DP_TRAINING_PATTERN_MASK);
123 return auxch_wr(encoder, DP_TRAINING_PATTERN_SET, &cmd, 1);
124}
125
126static int
127nouveau_dp_max_voltage_swing(struct drm_encoder *encoder)
128{
129 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
130 struct drm_device *dev = encoder->dev;
131 struct bit_displayport_encoder_table_entry *dpse;
132 struct bit_displayport_encoder_table *dpe;
133 int i, dpe_headerlen, max_vs = 0;
134
135 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
136 if (!dpe)
137 return false;
138 dpse = (void *)((char *)dpe + dpe_headerlen);
139
140 for (i = 0; i < dpe_headerlen; i++, dpse++) {
141 if (dpse->vs_level > max_vs)
142 max_vs = dpse->vs_level;
143 }
144
145 return max_vs;
146}
147
148static int
149nouveau_dp_max_pre_emphasis(struct drm_encoder *encoder, int vs)
150{
151 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
152 struct drm_device *dev = encoder->dev;
153 struct bit_displayport_encoder_table_entry *dpse;
154 struct bit_displayport_encoder_table *dpe;
155 int i, dpe_headerlen, max_pre = 0;
156
157 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
158 if (!dpe)
159 return false;
160 dpse = (void *)((char *)dpe + dpe_headerlen);
161
162 for (i = 0; i < dpe_headerlen; i++, dpse++) {
163 if (dpse->vs_level != vs)
164 continue;
165
166 if (dpse->pre_level > max_pre)
167 max_pre = dpse->pre_level;
168 }
169
170 return max_pre;
171}
172
173static bool
174nouveau_dp_link_train_adjust(struct drm_encoder *encoder, uint8_t *config)
175{
176 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
177 struct drm_device *dev = encoder->dev;
178 struct bit_displayport_encoder_table_entry *dpse;
179 struct bit_displayport_encoder_table *dpe;
180 int ret, i, dpe_headerlen, vs = 0, pre = 0;
181 uint8_t request[2];
182
183 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
184 if (!dpe)
185 return false;
186 dpse = (void *)((char *)dpe + dpe_headerlen);
187
188 ret = auxch_rd(encoder, DP_ADJUST_REQUEST_LANE0_1, request, 2);
189 if (ret)
190 return false;
191
192 NV_DEBUG_KMS(dev, "\t\tadjust 0x%02x 0x%02x\n", request[0], request[1]);
193
194
195 for (i = 0; i < nv_encoder->dp.link_nr; i++) {
196 int lane_req = (request[i >> 1] >> ((i & 1) << 2)) & 0xf;
197 int lane_vs = lane_req & 3;
198 int lane_pre = (lane_req >> 2) & 3;
199
200 if (lane_vs > vs)
201 vs = lane_vs;
202 if (lane_pre > pre)
203 pre = lane_pre;
204 }
205
206 if (vs >= nouveau_dp_max_voltage_swing(encoder)) {
207 vs = nouveau_dp_max_voltage_swing(encoder);
208 vs |= 4;
209 }
210
211 if (pre >= nouveau_dp_max_pre_emphasis(encoder, vs & 3)) {
212 pre = nouveau_dp_max_pre_emphasis(encoder, vs & 3);
213 pre |= 4;
214 }
215
216
217 for (i = 0; i < nv_encoder->dp.link_nr; i++)
218 config[i] = (pre << 3) | vs;
219
220 return true;
221}
222
223static bool
224nouveau_dp_link_train_commit(struct drm_encoder *encoder, uint8_t *config)
225{
226 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
227 struct drm_device *dev = encoder->dev;
228 struct bit_displayport_encoder_table_entry *dpse;
229 struct bit_displayport_encoder_table *dpe;
230 int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
231 int dpe_headerlen, ret, i;
232
233 NV_DEBUG_KMS(dev, "\t\tconfig 0x%02x 0x%02x 0x%02x 0x%02x\n",
234 config[0], config[1], config[2], config[3]);
235
236 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
237 if (!dpe)
238 return false;
239 dpse = (void *)((char *)dpe + dpe_headerlen);
240
241 for (i = 0; i < dpe->record_nr; i++, dpse++) {
242 if (dpse->vs_level == (config[0] & 3) &&
243 dpse->pre_level == ((config[0] >> 3) & 3))
244 break;
245 }
246 BUG_ON(i == dpe->record_nr);
247
248 for (i = 0; i < nv_encoder->dp.link_nr; i++) {
249 const int shift[4] = { 16, 8, 0, 24 };
250 uint32_t mask = 0xff << shift[i];
251 uint32_t reg0, reg1, reg2;
252
253 reg0 = nv_rd32(dev, NV50_SOR_DP_UNK118(or, link)) & ~mask;
254 reg0 |= (dpse->reg0 << shift[i]);
255 reg1 = nv_rd32(dev, NV50_SOR_DP_UNK120(or, link)) & ~mask;
256 reg1 |= (dpse->reg1 << shift[i]);
257 reg2 = nv_rd32(dev, NV50_SOR_DP_UNK130(or, link)) & 0xffff00ff;
258 reg2 |= (dpse->reg2 << 8);
259 nv_wr32(dev, NV50_SOR_DP_UNK118(or, link), reg0);
260 nv_wr32(dev, NV50_SOR_DP_UNK120(or, link), reg1);
261 nv_wr32(dev, NV50_SOR_DP_UNK130(or, link), reg2);
262 }
263
264 ret = auxch_wr(encoder, DP_TRAINING_LANE0_SET, config, 4);
265 if (ret)
266 return false;
267
268 return true;
269}
270
271bool
272nouveau_dp_link_train(struct drm_encoder *encoder)
273{
274 struct drm_device *dev = encoder->dev;
275 struct drm_nouveau_private *dev_priv = dev->dev_private;
276 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
277 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
278 struct nouveau_connector *nv_connector;
279 struct bit_displayport_encoder_table *dpe;
280 int dpe_headerlen;
281 uint8_t config[4], status[3];
282 bool cr_done, cr_max_vs, eq_done, hpd_state;
283 int ret = 0, i, tries, voltage;
284
285 NV_DEBUG_KMS(dev, "link training!!\n");
286
287 nv_connector = nouveau_encoder_connector_get(nv_encoder);
288 if (!nv_connector)
289 return false;
290
291 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
292 if (!dpe) {
293 NV_ERROR(dev, "SOR-%d: no DP encoder table!\n", nv_encoder->or);
294 return false;
295 }
296
297
298
299
300 hpd_state = pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, false);
301
302 if (dpe->script0) {
303 NV_DEBUG_KMS(dev, "SOR-%d: running DP script 0\n", nv_encoder->or);
304 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script0),
305 nv_encoder->dcb);
306 }
307
308train:
309 cr_done = eq_done = false;
310
311
312 NV_DEBUG_KMS(dev, "\tbegin train: bw %d, lanes %d\n",
313 nv_encoder->dp.link_bw, nv_encoder->dp.link_nr);
314
315 ret = nouveau_dp_link_bw_set(encoder, nv_encoder->dp.link_bw);
316 if (ret)
317 return false;
318
319 config[0] = nv_encoder->dp.link_nr;
320 if (nv_encoder->dp.dpcd_version >= 0x11 &&
321 nv_encoder->dp.enhanced_frame)
322 config[0] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
323
324 ret = nouveau_dp_lane_count_set(encoder, config[0]);
325 if (ret)
326 return false;
327
328
329 NV_DEBUG_KMS(dev, "\tbegin cr\n");
330 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_1);
331 if (ret)
332 goto stop;
333
334 tries = 0;
335 voltage = -1;
336 memset(config, 0x00, sizeof(config));
337 for (;;) {
338 if (!nouveau_dp_link_train_commit(encoder, config))
339 break;
340
341 udelay(100);
342
343 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 2);
344 if (ret)
345 break;
346 NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n",
347 status[0], status[1]);
348
349 cr_done = true;
350 cr_max_vs = false;
351 for (i = 0; i < nv_encoder->dp.link_nr; i++) {
352 int lane = (status[i >> 1] >> ((i & 1) * 4)) & 0xf;
353
354 if (!(lane & DP_LANE_CR_DONE)) {
355 cr_done = false;
356 if (config[i] & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED)
357 cr_max_vs = true;
358 break;
359 }
360 }
361
362 if ((config[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
363 voltage = config[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
364 tries = 0;
365 }
366
367 if (cr_done || cr_max_vs || (++tries == 5))
368 break;
369
370 if (!nouveau_dp_link_train_adjust(encoder, config))
371 break;
372 }
373
374 if (!cr_done)
375 goto stop;
376
377
378 NV_DEBUG_KMS(dev, "\tbegin eq\n");
379 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_2);
380 if (ret)
381 goto stop;
382
383 for (tries = 0; tries <= 5; tries++) {
384 udelay(400);
385
386 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 3);
387 if (ret)
388 break;
389 NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n",
390 status[0], status[1]);
391
392 eq_done = true;
393 if (!(status[2] & DP_INTERLANE_ALIGN_DONE))
394 eq_done = false;
395
396 for (i = 0; eq_done && i < nv_encoder->dp.link_nr; i++) {
397 int lane = (status[i >> 1] >> ((i & 1) * 4)) & 0xf;
398
399 if (!(lane & DP_LANE_CR_DONE)) {
400 cr_done = false;
401 break;
402 }
403
404 if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
405 !(lane & DP_LANE_SYMBOL_LOCKED)) {
406 eq_done = false;
407 break;
408 }
409 }
410
411 if (eq_done || !cr_done)
412 break;
413
414 if (!nouveau_dp_link_train_adjust(encoder, config) ||
415 !nouveau_dp_link_train_commit(encoder, config))
416 break;
417 }
418
419stop:
420
421 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_DISABLE);
422 if (ret)
423 return false;
424
425
426 if (!ret && !(eq_done && cr_done)) {
427 NV_DEBUG_KMS(dev, "\twe failed\n");
428 if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62) {
429 NV_DEBUG_KMS(dev, "retry link training at low rate\n");
430 nv_encoder->dp.link_bw = DP_LINK_BW_1_62;
431 goto train;
432 }
433 }
434
435 if (dpe->script1) {
436 NV_DEBUG_KMS(dev, "SOR-%d: running DP script 1\n", nv_encoder->or);
437 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script1),
438 nv_encoder->dcb);
439 }
440
441
442 pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, hpd_state);
443
444 return eq_done;
445}
446
447bool
448nouveau_dp_detect(struct drm_encoder *encoder)
449{
450 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
451 struct drm_device *dev = encoder->dev;
452 uint8_t dpcd[4];
453 int ret;
454
455 ret = auxch_rd(encoder, 0x0000, dpcd, 4);
456 if (ret)
457 return false;
458
459 NV_DEBUG_KMS(dev, "encoder: link_bw %d, link_nr %d\n"
460 "display: link_bw %d, link_nr %d version 0x%02x\n",
461 nv_encoder->dcb->dpconf.link_bw,
462 nv_encoder->dcb->dpconf.link_nr,
463 dpcd[1], dpcd[2] & 0x0f, dpcd[0]);
464
465 nv_encoder->dp.dpcd_version = dpcd[0];
466
467 nv_encoder->dp.link_bw = dpcd[1];
468 if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62 &&
469 !nv_encoder->dcb->dpconf.link_bw)
470 nv_encoder->dp.link_bw = DP_LINK_BW_1_62;
471
472 nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
473 if (nv_encoder->dp.link_nr > nv_encoder->dcb->dpconf.link_nr)
474 nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
475
476 nv_encoder->dp.enhanced_frame = (dpcd[2] & DP_ENHANCED_FRAME_CAP);
477
478 return true;
479}
480
481int
482nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
483 uint8_t *data, int data_nr)
484{
485 struct drm_device *dev = auxch->dev;
486 uint32_t tmp, ctrl, stat = 0, data32[4] = {};
487 int ret = 0, i, index = auxch->rd;
488
489 NV_DEBUG_KMS(dev, "ch %d cmd %d addr 0x%x len %d\n", index, cmd, addr, data_nr);
490
491 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
492 nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp | 0x00100000);
493 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
494 if (!(tmp & 0x01000000)) {
495 NV_ERROR(dev, "expected bit 24 == 1, got 0x%08x\n", tmp);
496 ret = -EIO;
497 goto out;
498 }
499
500 for (i = 0; i < 3; i++) {
501 tmp = nv_rd32(dev, NV50_AUXCH_STAT(auxch->rd));
502 if (tmp & NV50_AUXCH_STAT_STATE_READY)
503 break;
504 udelay(100);
505 }
506
507 if (i == 3) {
508 ret = -EBUSY;
509 goto out;
510 }
511
512 if (!(cmd & 1)) {
513 memcpy(data32, data, data_nr);
514 for (i = 0; i < 4; i++) {
515 NV_DEBUG_KMS(dev, "wr %d: 0x%08x\n", i, data32[i]);
516 nv_wr32(dev, NV50_AUXCH_DATA_OUT(index, i), data32[i]);
517 }
518 }
519
520 nv_wr32(dev, NV50_AUXCH_ADDR(index), addr);
521 ctrl = nv_rd32(dev, NV50_AUXCH_CTRL(index));
522 ctrl &= ~(NV50_AUXCH_CTRL_CMD | NV50_AUXCH_CTRL_LEN);
523 ctrl |= (cmd << NV50_AUXCH_CTRL_CMD_SHIFT);
524 ctrl |= ((data_nr - 1) << NV50_AUXCH_CTRL_LEN_SHIFT);
525
526 for (i = 0; i < 16; i++) {
527 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x80000000);
528 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl);
529 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x00010000);
530 if (!nv_wait(dev, NV50_AUXCH_CTRL(index),
531 0x00010000, 0x00000000)) {
532 NV_ERROR(dev, "expected bit 16 == 0, got 0x%08x\n",
533 nv_rd32(dev, NV50_AUXCH_CTRL(index)));
534 ret = -EBUSY;
535 goto out;
536 }
537
538 udelay(400);
539
540 stat = nv_rd32(dev, NV50_AUXCH_STAT(index));
541 if ((stat & NV50_AUXCH_STAT_REPLY_AUX) !=
542 NV50_AUXCH_STAT_REPLY_AUX_DEFER)
543 break;
544 }
545
546 if (i == 16) {
547 NV_ERROR(dev, "auxch DEFER too many times, bailing\n");
548 ret = -EREMOTEIO;
549 goto out;
550 }
551
552 if (cmd & 1) {
553 if ((stat & NV50_AUXCH_STAT_COUNT) != data_nr) {
554 ret = -EREMOTEIO;
555 goto out;
556 }
557
558 for (i = 0; i < 4; i++) {
559 data32[i] = nv_rd32(dev, NV50_AUXCH_DATA_IN(index, i));
560 NV_DEBUG_KMS(dev, "rd %d: 0x%08x\n", i, data32[i]);
561 }
562 memcpy(data, data32, data_nr);
563 }
564
565out:
566 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
567 nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp & ~0x00100000);
568 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
569 if (tmp & 0x01000000) {
570 NV_ERROR(dev, "expected bit 24 == 0, got 0x%08x\n", tmp);
571 ret = -EIO;
572 }
573
574 udelay(400);
575
576 return ret ? ret : (stat & NV50_AUXCH_STAT_REPLY);
577}
578
579static int
580nouveau_dp_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
581{
582 struct nouveau_i2c_chan *auxch = (struct nouveau_i2c_chan *)adap;
583 struct drm_device *dev = auxch->dev;
584 struct i2c_msg *msg = msgs;
585 int ret, mcnt = num;
586
587 while (mcnt--) {
588 u8 remaining = msg->len;
589 u8 *ptr = msg->buf;
590
591 while (remaining) {
592 u8 cnt = (remaining > 16) ? 16 : remaining;
593 u8 cmd;
594
595 if (msg->flags & I2C_M_RD)
596 cmd = AUX_I2C_READ;
597 else
598 cmd = AUX_I2C_WRITE;
599
600 if (mcnt || remaining > 16)
601 cmd |= AUX_I2C_MOT;
602
603 ret = nouveau_dp_auxch(auxch, cmd, msg->addr, ptr, cnt);
604 if (ret < 0)
605 return ret;
606
607 switch (ret & NV50_AUXCH_STAT_REPLY_I2C) {
608 case NV50_AUXCH_STAT_REPLY_I2C_ACK:
609 break;
610 case NV50_AUXCH_STAT_REPLY_I2C_NACK:
611 return -EREMOTEIO;
612 case NV50_AUXCH_STAT_REPLY_I2C_DEFER:
613 udelay(100);
614 continue;
615 default:
616 NV_ERROR(dev, "bad auxch reply: 0x%08x\n", ret);
617 return -EREMOTEIO;
618 }
619
620 ptr += cnt;
621 remaining -= cnt;
622 }
623
624 msg++;
625 }
626
627 return num;
628}
629
630static u32
631nouveau_dp_i2c_func(struct i2c_adapter *adap)
632{
633 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
634}
635
636const struct i2c_algorithm nouveau_dp_i2c_algo = {
637 .master_xfer = nouveau_dp_i2c_xfer,
638 .functionality = nouveau_dp_i2c_func
639};
640
