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25#include <linux/console.h>
26
27#include "drmP.h"
28#include "drm.h"
29#include "drm_crtc_helper.h"
30#include "nouveau_drv.h"
31#include "nouveau_hw.h"
32#include "nouveau_fb.h"
33#include "nouveau_fbcon.h"
34#include "nouveau_pm.h"
35#include "nv50_display.h"
36
37#include "drm_pciids.h"
38
39MODULE_PARM_DESC(agpmode, "AGP mode (0 to disable AGP)");
40int nouveau_agpmode = -1;
41module_param_named(agpmode, nouveau_agpmode, int, 0400);
42
43MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
44static int nouveau_modeset = -1;
45module_param_named(modeset, nouveau_modeset, int, 0400);
46
47MODULE_PARM_DESC(vbios, "Override default VBIOS location");
48char *nouveau_vbios;
49module_param_named(vbios, nouveau_vbios, charp, 0400);
50
51MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
52int nouveau_vram_pushbuf;
53module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
54
55MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
56int nouveau_vram_notify = 0;
57module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
58
59MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
60int nouveau_duallink = 1;
61module_param_named(duallink, nouveau_duallink, int, 0400);
62
63MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
64int nouveau_uscript_lvds = -1;
65module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);
66
67MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
68int nouveau_uscript_tmds = -1;
69module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
70
71MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
72int nouveau_ignorelid = 0;
73module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
74
75MODULE_PARM_DESC(noaccel, "Disable all acceleration");
76int nouveau_noaccel = 0;
77module_param_named(noaccel, nouveau_noaccel, int, 0400);
78
79MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
80int nouveau_nofbaccel = 0;
81module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
82
83MODULE_PARM_DESC(force_post, "Force POST");
84int nouveau_force_post = 0;
85module_param_named(force_post, nouveau_force_post, int, 0400);
86
87MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
88int nouveau_override_conntype = 0;
89module_param_named(override_conntype, nouveau_override_conntype, int, 0400);
90
91MODULE_PARM_DESC(tv_disable, "Disable TV-out detection\n");
92int nouveau_tv_disable = 0;
93module_param_named(tv_disable, nouveau_tv_disable, int, 0400);
94
95MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
96 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
97 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
98 "\t\tDefault: PAL\n"
99 "\t\t*NOTE* Ignored for cards with external TV encoders.");
100char *nouveau_tv_norm;
101module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
102
103MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
104 "\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
105 "\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
106 "\t\t0x100 vgaattr, 0x200 EVO (G80+). ");
107int nouveau_reg_debug;
108module_param_named(reg_debug, nouveau_reg_debug, int, 0600);
109
110MODULE_PARM_DESC(perflvl, "Performance level (default: boot)\n");
111char *nouveau_perflvl;
112module_param_named(perflvl, nouveau_perflvl, charp, 0400);
113
114MODULE_PARM_DESC(perflvl_wr, "Allow perflvl changes (warning: dangerous!)\n");
115int nouveau_perflvl_wr;
116module_param_named(perflvl_wr, nouveau_perflvl_wr, int, 0400);
117
118MODULE_PARM_DESC(msi, "Enable MSI (default: off)\n");
119int nouveau_msi;
120module_param_named(msi, nouveau_msi, int, 0400);
121
122int nouveau_fbpercrtc;
123#if 0
124module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
125#endif
126
127static struct pci_device_id pciidlist[] = {
128 {
129 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
130 .class = PCI_BASE_CLASS_DISPLAY << 16,
131 .class_mask = 0xff << 16,
132 },
133 {
134 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
135 .class = PCI_BASE_CLASS_DISPLAY << 16,
136 .class_mask = 0xff << 16,
137 },
138 {}
139};
140
141MODULE_DEVICE_TABLE(pci, pciidlist);
142
143static struct drm_driver driver;
144
145static int __devinit
146nouveau_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
147{
148 return drm_get_pci_dev(pdev, ent, &driver);
149}
150
151static void
152nouveau_pci_remove(struct pci_dev *pdev)
153{
154 struct drm_device *dev = pci_get_drvdata(pdev);
155
156 drm_put_dev(dev);
157}
158
159int
160nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
161{
162 struct drm_device *dev = pci_get_drvdata(pdev);
163 struct drm_nouveau_private *dev_priv = dev->dev_private;
164 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
165 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
166 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
167 struct nouveau_channel *chan;
168 struct drm_crtc *crtc;
169 int ret, i;
170
171 if (pm_state.event == PM_EVENT_PRETHAW)
172 return 0;
173
174 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
175 return 0;
176
177 NV_INFO(dev, "Disabling fbcon acceleration...\n");
178 nouveau_fbcon_save_disable_accel(dev);
179
180 NV_INFO(dev, "Unpinning framebuffer(s)...\n");
181 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
182 struct nouveau_framebuffer *nouveau_fb;
183
184 nouveau_fb = nouveau_framebuffer(crtc->fb);
185 if (!nouveau_fb || !nouveau_fb->nvbo)
186 continue;
187
188 nouveau_bo_unpin(nouveau_fb->nvbo);
189 }
190
191 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
192 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
193
194 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
195 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
196 }
197
198 NV_INFO(dev, "Evicting buffers...\n");
199 ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
200
201 NV_INFO(dev, "Idling channels...\n");
202 for (i = 0; i < pfifo->channels; i++) {
203 chan = dev_priv->channels.ptr[i];
204
205 if (chan && chan->pushbuf_bo)
206 nouveau_channel_idle(chan);
207 }
208
209 pgraph->fifo_access(dev, false);
210 nouveau_wait_for_idle(dev);
211 pfifo->reassign(dev, false);
212 pfifo->disable(dev);
213 pfifo->unload_context(dev);
214 pgraph->unload_context(dev);
215
216 ret = pinstmem->suspend(dev);
217 if (ret) {
218 NV_ERROR(dev, "... failed: %d\n", ret);
219 goto out_abort;
220 }
221
222 NV_INFO(dev, "Suspending GPU objects...\n");
223 ret = nouveau_gpuobj_suspend(dev);
224 if (ret) {
225 NV_ERROR(dev, "... failed: %d\n", ret);
226 pinstmem->resume(dev);
227 goto out_abort;
228 }
229
230 NV_INFO(dev, "And we're gone!\n");
231 pci_save_state(pdev);
232 if (pm_state.event == PM_EVENT_SUSPEND) {
233 pci_disable_device(pdev);
234 pci_set_power_state(pdev, PCI_D3hot);
235 }
236
237 console_lock();
238 nouveau_fbcon_set_suspend(dev, 1);
239 console_unlock();
240 nouveau_fbcon_restore_accel(dev);
241 return 0;
242
243out_abort:
244 NV_INFO(dev, "Re-enabling acceleration..\n");
245 pfifo->enable(dev);
246 pfifo->reassign(dev, true);
247 pgraph->fifo_access(dev, true);
248 return ret;
249}
250
251int
252nouveau_pci_resume(struct pci_dev *pdev)
253{
254 struct drm_device *dev = pci_get_drvdata(pdev);
255 struct drm_nouveau_private *dev_priv = dev->dev_private;
256 struct nouveau_engine *engine = &dev_priv->engine;
257 struct drm_crtc *crtc;
258 int ret, i;
259
260 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
261 return 0;
262
263 nouveau_fbcon_save_disable_accel(dev);
264
265 NV_INFO(dev, "We're back, enabling device...\n");
266 pci_set_power_state(pdev, PCI_D0);
267 pci_restore_state(pdev);
268 if (pci_enable_device(pdev))
269 return -1;
270 pci_set_master(dev->pdev);
271
272
273 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP)
274 nouveau_mem_reset_agp(dev);
275
276
277 engine->display.early_init(dev);
278
279 NV_INFO(dev, "POSTing device...\n");
280 ret = nouveau_run_vbios_init(dev);
281 if (ret)
282 return ret;
283
284 nouveau_pm_resume(dev);
285
286 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
287 ret = nouveau_mem_init_agp(dev);
288 if (ret) {
289 NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
290 return ret;
291 }
292 }
293
294 NV_INFO(dev, "Restoring GPU objects...\n");
295 nouveau_gpuobj_resume(dev);
296
297 NV_INFO(dev, "Reinitialising engines...\n");
298 engine->instmem.resume(dev);
299 engine->mc.init(dev);
300 engine->timer.init(dev);
301 engine->fb.init(dev);
302 engine->graph.init(dev);
303 engine->crypt.init(dev);
304 engine->fifo.init(dev);
305
306 nouveau_irq_postinstall(dev);
307
308
309 if (nouveau_vram_pushbuf) {
310 struct nouveau_channel *chan;
311 int j;
312
313 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
314 chan = dev_priv->channels.ptr[i];
315 if (!chan || !chan->pushbuf_bo)
316 continue;
317
318 for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
319 nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
320 }
321 }
322
323 NV_INFO(dev, "Restoring mode...\n");
324 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
325 struct nouveau_framebuffer *nouveau_fb;
326
327 nouveau_fb = nouveau_framebuffer(crtc->fb);
328 if (!nouveau_fb || !nouveau_fb->nvbo)
329 continue;
330
331 nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
332 }
333
334 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
335 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
336
337 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
338 if (!ret)
339 ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
340 if (ret)
341 NV_ERROR(dev, "Could not pin/map cursor.\n");
342 }
343
344 engine->display.init(dev);
345
346 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
347 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
348 u32 offset = nv_crtc->cursor.nvbo->bo.mem.start << PAGE_SHIFT;
349
350 nv_crtc->cursor.set_offset(nv_crtc, offset);
351 nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
352 nv_crtc->cursor_saved_y);
353 }
354
355
356 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
357 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
358
359 nv_crtc->lut.depth = 0;
360 }
361
362 console_lock();
363 nouveau_fbcon_set_suspend(dev, 0);
364 console_unlock();
365
366 nouveau_fbcon_zfill_all(dev);
367
368 drm_helper_resume_force_mode(dev);
369
370 nouveau_fbcon_restore_accel(dev);
371 return 0;
372}
373
374static struct drm_driver driver = {
375 .driver_features =
376 DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
377 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
378 DRIVER_MODESET,
379 .load = nouveau_load,
380 .firstopen = nouveau_firstopen,
381 .lastclose = nouveau_lastclose,
382 .unload = nouveau_unload,
383 .preclose = nouveau_preclose,
384#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
385 .debugfs_init = nouveau_debugfs_init,
386 .debugfs_cleanup = nouveau_debugfs_takedown,
387#endif
388 .irq_preinstall = nouveau_irq_preinstall,
389 .irq_postinstall = nouveau_irq_postinstall,
390 .irq_uninstall = nouveau_irq_uninstall,
391 .irq_handler = nouveau_irq_handler,
392 .get_vblank_counter = drm_vblank_count,
393 .enable_vblank = nouveau_vblank_enable,
394 .disable_vblank = nouveau_vblank_disable,
395 .reclaim_buffers = drm_core_reclaim_buffers,
396 .ioctls = nouveau_ioctls,
397 .fops = {
398 .owner = THIS_MODULE,
399 .open = drm_open,
400 .release = drm_release,
401 .unlocked_ioctl = drm_ioctl,
402 .mmap = nouveau_ttm_mmap,
403 .poll = drm_poll,
404 .fasync = drm_fasync,
405 .read = drm_read,
406#if defined(CONFIG_COMPAT)
407 .compat_ioctl = nouveau_compat_ioctl,
408#endif
409 .llseek = noop_llseek,
410 },
411 .pci_driver = {
412 .name = DRIVER_NAME,
413 .id_table = pciidlist,
414 .probe = nouveau_pci_probe,
415 .remove = nouveau_pci_remove,
416 .suspend = nouveau_pci_suspend,
417 .resume = nouveau_pci_resume
418 },
419
420 .gem_init_object = nouveau_gem_object_new,
421 .gem_free_object = nouveau_gem_object_del,
422
423 .name = DRIVER_NAME,
424 .desc = DRIVER_DESC,
425#ifdef GIT_REVISION
426 .date = GIT_REVISION,
427#else
428 .date = DRIVER_DATE,
429#endif
430 .major = DRIVER_MAJOR,
431 .minor = DRIVER_MINOR,
432 .patchlevel = DRIVER_PATCHLEVEL,
433};
434
435static int __init nouveau_init(void)
436{
437 driver.num_ioctls = nouveau_max_ioctl;
438
439 if (nouveau_modeset == -1) {
440#ifdef CONFIG_VGA_CONSOLE
441 if (vgacon_text_force())
442 nouveau_modeset = 0;
443 else
444#endif
445 nouveau_modeset = 1;
446 }
447
448 if (!nouveau_modeset)
449 return 0;
450
451 nouveau_register_dsm_handler();
452 return drm_init(&driver);
453}
454
455static void __exit nouveau_exit(void)
456{
457 if (!nouveau_modeset)
458 return;
459
460 drm_exit(&driver);
461 nouveau_unregister_dsm_handler();
462}
463
464module_init(nouveau_init);
465module_exit(nouveau_exit);
466
467MODULE_AUTHOR(DRIVER_AUTHOR);
468MODULE_DESCRIPTION(DRIVER_DESC);
469MODULE_LICENSE("GPL and additional rights");
470
