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28#ifndef __RADEON_H__
29#define __RADEON_H__
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63#include <asm/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
72#include <ttm/ttm_execbuf_util.h>
73
74#include "radeon_family.h"
75#include "radeon_mode.h"
76#include "radeon_reg.h"
77
78
79
80
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
89extern int radeon_testing;
90extern int radeon_connector_table;
91extern int radeon_tv;
92extern int radeon_audio;
93extern int radeon_disp_priority;
94extern int radeon_hw_i2c;
95extern int radeon_pcie_gen2;
96
97
98
99
100
101#define RADEON_MAX_USEC_TIMEOUT 100000
102#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
103
104#define RADEON_IB_POOL_SIZE 16
105#define RADEON_DEBUGFS_MAX_NUM_FILES 32
106#define RADEONFB_CONN_LIMIT 4
107#define RADEON_BIOS_NUM_SCRATCH 8
108
109
110
111
112enum radeon_pll_errata {
113 CHIP_ERRATA_R300_CG = 0x00000001,
114 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
115 CHIP_ERRATA_PLL_DELAY = 0x00000004
116};
117
118
119struct radeon_device;
120
121
122
123
124
125#define ATRM_BIOS_PAGE 4096
126
127#if defined(CONFIG_VGA_SWITCHEROO)
128bool radeon_atrm_supported(struct pci_dev *pdev);
129int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
130#else
131static inline bool radeon_atrm_supported(struct pci_dev *pdev)
132{
133 return false;
134}
135
136static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
137 return -EINVAL;
138}
139#endif
140bool radeon_get_bios(struct radeon_device *rdev);
141
142
143
144
145
146struct radeon_dummy_page {
147 struct page *page;
148 dma_addr_t addr;
149};
150int radeon_dummy_page_init(struct radeon_device *rdev);
151void radeon_dummy_page_fini(struct radeon_device *rdev);
152
153
154
155
156
157struct radeon_clock {
158 struct radeon_pll p1pll;
159 struct radeon_pll p2pll;
160 struct radeon_pll dcpll;
161 struct radeon_pll spll;
162 struct radeon_pll mpll;
163
164 uint32_t default_mclk;
165 uint32_t default_sclk;
166 uint32_t default_dispclk;
167 uint32_t dp_extclk;
168};
169
170
171
172
173int radeon_pm_init(struct radeon_device *rdev);
174void radeon_pm_fini(struct radeon_device *rdev);
175void radeon_pm_compute_clocks(struct radeon_device *rdev);
176void radeon_pm_suspend(struct radeon_device *rdev);
177void radeon_pm_resume(struct radeon_device *rdev);
178void radeon_combios_get_power_modes(struct radeon_device *rdev);
179void radeon_atombios_get_power_modes(struct radeon_device *rdev);
180void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level);
181void rs690_pm_info(struct radeon_device *rdev);
182extern int rv6xx_get_temp(struct radeon_device *rdev);
183extern int rv770_get_temp(struct radeon_device *rdev);
184extern int evergreen_get_temp(struct radeon_device *rdev);
185extern int sumo_get_temp(struct radeon_device *rdev);
186
187
188
189
190struct radeon_fence_driver {
191 uint32_t scratch_reg;
192 atomic_t seq;
193 uint32_t last_seq;
194 unsigned long last_jiffies;
195 unsigned long last_timeout;
196 wait_queue_head_t queue;
197 rwlock_t lock;
198 struct list_head created;
199 struct list_head emited;
200 struct list_head signaled;
201 bool initialized;
202};
203
204struct radeon_fence {
205 struct radeon_device *rdev;
206 struct kref kref;
207 struct list_head list;
208
209 uint32_t seq;
210 bool emited;
211 bool signaled;
212};
213
214int radeon_fence_driver_init(struct radeon_device *rdev);
215void radeon_fence_driver_fini(struct radeon_device *rdev);
216int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
217int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
218void radeon_fence_process(struct radeon_device *rdev);
219bool radeon_fence_signaled(struct radeon_fence *fence);
220int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
221int radeon_fence_wait_next(struct radeon_device *rdev);
222int radeon_fence_wait_last(struct radeon_device *rdev);
223struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
224void radeon_fence_unref(struct radeon_fence **fence);
225
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227
228
229struct radeon_surface_reg {
230 struct radeon_bo *bo;
231};
232
233#define RADEON_GEM_MAX_SURFACES 8
234
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236
237
238struct radeon_mman {
239 struct ttm_bo_global_ref bo_global_ref;
240 struct drm_global_reference mem_global_ref;
241 struct ttm_bo_device bdev;
242 bool mem_global_referenced;
243 bool initialized;
244};
245
246struct radeon_bo {
247
248 struct list_head list;
249
250 u32 placements[3];
251 struct ttm_placement placement;
252 struct ttm_buffer_object tbo;
253 struct ttm_bo_kmap_obj kmap;
254 unsigned pin_count;
255 void *kptr;
256 u32 tiling_flags;
257 u32 pitch;
258 int surface_reg;
259
260 struct radeon_device *rdev;
261 struct drm_gem_object *gobj;
262};
263
264struct radeon_bo_list {
265 struct ttm_validate_buffer tv;
266 struct radeon_bo *bo;
267 uint64_t gpu_offset;
268 unsigned rdomain;
269 unsigned wdomain;
270 u32 tiling_flags;
271};
272
273
274
275
276struct radeon_gem {
277 struct mutex mutex;
278 struct list_head objects;
279};
280
281int radeon_gem_init(struct radeon_device *rdev);
282void radeon_gem_fini(struct radeon_device *rdev);
283int radeon_gem_object_create(struct radeon_device *rdev, int size,
284 int alignment, int initial_domain,
285 bool discardable, bool kernel,
286 struct drm_gem_object **obj);
287int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
288 uint64_t *gpu_addr);
289void radeon_gem_object_unpin(struct drm_gem_object *obj);
290
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294
295struct radeon_mc;
296
297struct radeon_gart_table_ram {
298 volatile uint32_t *ptr;
299};
300
301struct radeon_gart_table_vram {
302 struct radeon_bo *robj;
303 volatile uint32_t *ptr;
304};
305
306union radeon_gart_table {
307 struct radeon_gart_table_ram ram;
308 struct radeon_gart_table_vram vram;
309};
310
311#define RADEON_GPU_PAGE_SIZE 4096
312#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
313
314struct radeon_gart {
315 dma_addr_t table_addr;
316 unsigned num_gpu_pages;
317 unsigned num_cpu_pages;
318 unsigned table_size;
319 union radeon_gart_table table;
320 struct page **pages;
321 dma_addr_t *pages_addr;
322 bool ready;
323};
324
325int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
326void radeon_gart_table_ram_free(struct radeon_device *rdev);
327int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
328void radeon_gart_table_vram_free(struct radeon_device *rdev);
329int radeon_gart_init(struct radeon_device *rdev);
330void radeon_gart_fini(struct radeon_device *rdev);
331void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
332 int pages);
333int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
334 int pages, struct page **pagelist);
335
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339
340struct radeon_mc {
341 resource_size_t aper_size;
342 resource_size_t aper_base;
343 resource_size_t agp_base;
344
345
346 u64 mc_vram_size;
347 u64 visible_vram_size;
348 u64 gtt_size;
349 u64 gtt_start;
350 u64 gtt_end;
351 u64 vram_start;
352 u64 vram_end;
353 unsigned vram_width;
354 u64 real_vram_size;
355 int vram_mtrr;
356 bool vram_is_ddr;
357 bool igp_sideport_enabled;
358 u64 gtt_base_align;
359};
360
361bool radeon_combios_sideport_present(struct radeon_device *rdev);
362bool radeon_atombios_sideport_present(struct radeon_device *rdev);
363
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366
367struct radeon_scratch {
368 unsigned num_reg;
369 uint32_t reg_base;
370 bool free[32];
371 uint32_t reg[32];
372};
373
374int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
375void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
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382struct radeon_unpin_work {
383 struct work_struct work;
384 struct radeon_device *rdev;
385 int crtc_id;
386 struct radeon_fence *fence;
387 struct drm_pending_vblank_event *event;
388 struct radeon_bo *old_rbo;
389 u64 new_crtc_base;
390};
391
392struct r500_irq_stat_regs {
393 u32 disp_int;
394};
395
396struct r600_irq_stat_regs {
397 u32 disp_int;
398 u32 disp_int_cont;
399 u32 disp_int_cont2;
400 u32 d1grph_int;
401 u32 d2grph_int;
402};
403
404struct evergreen_irq_stat_regs {
405 u32 disp_int;
406 u32 disp_int_cont;
407 u32 disp_int_cont2;
408 u32 disp_int_cont3;
409 u32 disp_int_cont4;
410 u32 disp_int_cont5;
411 u32 d1grph_int;
412 u32 d2grph_int;
413 u32 d3grph_int;
414 u32 d4grph_int;
415 u32 d5grph_int;
416 u32 d6grph_int;
417};
418
419union radeon_irq_stat_regs {
420 struct r500_irq_stat_regs r500;
421 struct r600_irq_stat_regs r600;
422 struct evergreen_irq_stat_regs evergreen;
423};
424
425struct radeon_irq {
426 bool installed;
427 bool sw_int;
428
429 bool crtc_vblank_int[6];
430 bool pflip[6];
431 wait_queue_head_t vblank_queue;
432
433 bool hpd[6];
434 bool gui_idle;
435 bool gui_idle_acked;
436 wait_queue_head_t idle_queue;
437
438 bool hdmi[2];
439 spinlock_t sw_lock;
440 int sw_refcount;
441 union radeon_irq_stat_regs stat_regs;
442 spinlock_t pflip_lock[6];
443 int pflip_refcount[6];
444};
445
446int radeon_irq_kms_init(struct radeon_device *rdev);
447void radeon_irq_kms_fini(struct radeon_device *rdev);
448void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
449void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
450void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
451void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
452
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455
456struct radeon_ib {
457 struct list_head list;
458 unsigned idx;
459 uint64_t gpu_addr;
460 struct radeon_fence *fence;
461 uint32_t *ptr;
462 uint32_t length_dw;
463 bool free;
464};
465
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468
469
470struct radeon_ib_pool {
471 struct mutex mutex;
472 struct radeon_bo *robj;
473 struct list_head bogus_ib;
474 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
475 bool ready;
476 unsigned head_id;
477};
478
479struct radeon_cp {
480 struct radeon_bo *ring_obj;
481 volatile uint32_t *ring;
482 unsigned rptr;
483 unsigned wptr;
484 unsigned wptr_old;
485 unsigned ring_size;
486 unsigned ring_free_dw;
487 int count_dw;
488 uint64_t gpu_addr;
489 uint32_t align_mask;
490 uint32_t ptr_mask;
491 struct mutex mutex;
492 bool ready;
493};
494
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497
498struct r600_ih {
499 struct radeon_bo *ring_obj;
500 volatile uint32_t *ring;
501 unsigned rptr;
502 unsigned wptr;
503 unsigned wptr_old;
504 unsigned ring_size;
505 uint64_t gpu_addr;
506 uint32_t ptr_mask;
507 spinlock_t lock;
508 bool enabled;
509};
510
511struct r600_blit {
512 struct mutex mutex;
513 struct radeon_bo *shader_obj;
514 u64 shader_gpu_addr;
515 u32 vs_offset, ps_offset;
516 u32 state_offset;
517 u32 state_len;
518 u32 vb_used, vb_total;
519 struct radeon_ib *vb_ib;
520};
521
522int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
523void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
524int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
525int radeon_ib_pool_init(struct radeon_device *rdev);
526void radeon_ib_pool_fini(struct radeon_device *rdev);
527int radeon_ib_test(struct radeon_device *rdev);
528extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
529
530void radeon_ring_free_size(struct radeon_device *rdev);
531int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
532int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
533void radeon_ring_commit(struct radeon_device *rdev);
534void radeon_ring_unlock_commit(struct radeon_device *rdev);
535void radeon_ring_unlock_undo(struct radeon_device *rdev);
536int radeon_ring_test(struct radeon_device *rdev);
537int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
538void radeon_ring_fini(struct radeon_device *rdev);
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543
544struct radeon_cs_reloc {
545 struct drm_gem_object *gobj;
546 struct radeon_bo *robj;
547 struct radeon_bo_list lobj;
548 uint32_t handle;
549 uint32_t flags;
550};
551
552struct radeon_cs_chunk {
553 uint32_t chunk_id;
554 uint32_t length_dw;
555 int kpage_idx[2];
556 uint32_t *kpage[2];
557 uint32_t *kdata;
558 void __user *user_ptr;
559 int last_copied_page;
560 int last_page_index;
561};
562
563struct radeon_cs_parser {
564 struct device *dev;
565 struct radeon_device *rdev;
566 struct drm_file *filp;
567
568 unsigned nchunks;
569 struct radeon_cs_chunk *chunks;
570 uint64_t *chunks_array;
571
572 unsigned idx;
573
574 unsigned nrelocs;
575 struct radeon_cs_reloc *relocs;
576 struct radeon_cs_reloc **relocs_ptr;
577 struct list_head validated;
578
579 int chunk_ib_idx;
580 int chunk_relocs_idx;
581 struct radeon_ib *ib;
582 void *track;
583 unsigned family;
584 int parser_error;
585};
586
587extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
588extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
589
590
591static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
592{
593 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
594 u32 pg_idx, pg_offset;
595 u32 idx_value = 0;
596 int new_page;
597
598 pg_idx = (idx * 4) / PAGE_SIZE;
599 pg_offset = (idx * 4) % PAGE_SIZE;
600
601 if (ibc->kpage_idx[0] == pg_idx)
602 return ibc->kpage[0][pg_offset/4];
603 if (ibc->kpage_idx[1] == pg_idx)
604 return ibc->kpage[1][pg_offset/4];
605
606 new_page = radeon_cs_update_pages(p, pg_idx);
607 if (new_page < 0) {
608 p->parser_error = new_page;
609 return 0;
610 }
611
612 idx_value = ibc->kpage[new_page][pg_offset/4];
613 return idx_value;
614}
615
616struct radeon_cs_packet {
617 unsigned idx;
618 unsigned type;
619 unsigned reg;
620 unsigned opcode;
621 int count;
622 unsigned one_reg_wr;
623};
624
625typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
626 struct radeon_cs_packet *pkt,
627 unsigned idx, unsigned reg);
628typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
629 struct radeon_cs_packet *pkt);
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631
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633
634
635int radeon_agp_init(struct radeon_device *rdev);
636void radeon_agp_resume(struct radeon_device *rdev);
637void radeon_agp_suspend(struct radeon_device *rdev);
638void radeon_agp_fini(struct radeon_device *rdev);
639
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642
643
644struct radeon_wb {
645 struct radeon_bo *wb_obj;
646 volatile uint32_t *wb;
647 uint64_t gpu_addr;
648 bool enabled;
649 bool use_event;
650};
651
652#define RADEON_WB_SCRATCH_OFFSET 0
653#define RADEON_WB_CP_RPTR_OFFSET 1024
654#define R600_WB_IH_WPTR_OFFSET 2048
655#define R600_WB_EVENT_OFFSET 3072
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676
677enum radeon_pm_method {
678 PM_METHOD_PROFILE,
679 PM_METHOD_DYNPM,
680};
681
682enum radeon_dynpm_state {
683 DYNPM_STATE_DISABLED,
684 DYNPM_STATE_MINIMUM,
685 DYNPM_STATE_PAUSED,
686 DYNPM_STATE_ACTIVE,
687 DYNPM_STATE_SUSPENDED,
688};
689enum radeon_dynpm_action {
690 DYNPM_ACTION_NONE,
691 DYNPM_ACTION_MINIMUM,
692 DYNPM_ACTION_DOWNCLOCK,
693 DYNPM_ACTION_UPCLOCK,
694 DYNPM_ACTION_DEFAULT
695};
696
697enum radeon_voltage_type {
698 VOLTAGE_NONE = 0,
699 VOLTAGE_GPIO,
700 VOLTAGE_VDDC,
701 VOLTAGE_SW
702};
703
704enum radeon_pm_state_type {
705 POWER_STATE_TYPE_DEFAULT,
706 POWER_STATE_TYPE_POWERSAVE,
707 POWER_STATE_TYPE_BATTERY,
708 POWER_STATE_TYPE_BALANCED,
709 POWER_STATE_TYPE_PERFORMANCE,
710};
711
712enum radeon_pm_profile_type {
713 PM_PROFILE_DEFAULT,
714 PM_PROFILE_AUTO,
715 PM_PROFILE_LOW,
716 PM_PROFILE_MID,
717 PM_PROFILE_HIGH,
718};
719
720#define PM_PROFILE_DEFAULT_IDX 0
721#define PM_PROFILE_LOW_SH_IDX 1
722#define PM_PROFILE_MID_SH_IDX 2
723#define PM_PROFILE_HIGH_SH_IDX 3
724#define PM_PROFILE_LOW_MH_IDX 4
725#define PM_PROFILE_MID_MH_IDX 5
726#define PM_PROFILE_HIGH_MH_IDX 6
727#define PM_PROFILE_MAX 7
728
729struct radeon_pm_profile {
730 int dpms_off_ps_idx;
731 int dpms_on_ps_idx;
732 int dpms_off_cm_idx;
733 int dpms_on_cm_idx;
734};
735
736enum radeon_int_thermal_type {
737 THERMAL_TYPE_NONE,
738 THERMAL_TYPE_RV6XX,
739 THERMAL_TYPE_RV770,
740 THERMAL_TYPE_EVERGREEN,
741 THERMAL_TYPE_SUMO,
742 THERMAL_TYPE_NI,
743};
744
745struct radeon_voltage {
746 enum radeon_voltage_type type;
747
748 struct radeon_gpio_rec gpio;
749 u32 delay;
750 bool active_high;
751
752 u8 vddc_id;
753 u8 vddci_id;
754 bool vddci_enabled;
755
756 u32 voltage;
757};
758
759
760#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
761
762struct radeon_pm_clock_info {
763
764 u32 mclk;
765
766 u32 sclk;
767
768 struct radeon_voltage voltage;
769
770 u32 flags;
771};
772
773
774#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
775
776struct radeon_power_state {
777 enum radeon_pm_state_type type;
778
779 struct radeon_pm_clock_info clock_info[8];
780
781 int num_clock_modes;
782 struct radeon_pm_clock_info *default_clock_mode;
783
784 u32 flags;
785 u32 misc;
786 u32 misc2;
787 int pcie_lanes;
788};
789
790
791
792
793#define RADEON_MODE_OVERCLOCK_MARGIN 500
794
795struct radeon_pm {
796 struct mutex mutex;
797 u32 active_crtcs;
798 int active_crtc_count;
799 int req_vblank;
800 bool vblank_sync;
801 bool gui_idle;
802 fixed20_12 max_bandwidth;
803 fixed20_12 igp_sideport_mclk;
804 fixed20_12 igp_system_mclk;
805 fixed20_12 igp_ht_link_clk;
806 fixed20_12 igp_ht_link_width;
807 fixed20_12 k8_bandwidth;
808 fixed20_12 sideport_bandwidth;
809 fixed20_12 ht_bandwidth;
810 fixed20_12 core_bandwidth;
811 fixed20_12 sclk;
812 fixed20_12 mclk;
813 fixed20_12 needed_bandwidth;
814 struct radeon_power_state *power_state;
815
816 int num_power_states;
817 int current_power_state_index;
818 int current_clock_mode_index;
819 int requested_power_state_index;
820 int requested_clock_mode_index;
821 int default_power_state_index;
822 u32 current_sclk;
823 u32 current_mclk;
824 u32 current_vddc;
825 u32 default_sclk;
826 u32 default_mclk;
827 u32 default_vddc;
828 struct radeon_i2c_chan *i2c_bus;
829
830 enum radeon_pm_method pm_method;
831
832 struct delayed_work dynpm_idle_work;
833 enum radeon_dynpm_state dynpm_state;
834 enum radeon_dynpm_action dynpm_planned_action;
835 unsigned long dynpm_action_timeout;
836 bool dynpm_can_upclock;
837 bool dynpm_can_downclock;
838
839 enum radeon_pm_profile_type profile;
840 int profile_index;
841 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
842
843 enum radeon_int_thermal_type int_thermal_type;
844 struct device *int_hwmon_dev;
845};
846
847
848
849
850
851void radeon_benchmark(struct radeon_device *rdev);
852
853
854
855
856
857void radeon_test_moves(struct radeon_device *rdev);
858
859
860
861
862
863int radeon_debugfs_add_files(struct radeon_device *rdev,
864 struct drm_info_list *files,
865 unsigned nfiles);
866int radeon_debugfs_fence_init(struct radeon_device *rdev);
867
868
869
870
871
872struct radeon_asic {
873 int (*init)(struct radeon_device *rdev);
874 void (*fini)(struct radeon_device *rdev);
875 int (*resume)(struct radeon_device *rdev);
876 int (*suspend)(struct radeon_device *rdev);
877 void (*vga_set_state)(struct radeon_device *rdev, bool state);
878 bool (*gpu_is_lockup)(struct radeon_device *rdev);
879 int (*asic_reset)(struct radeon_device *rdev);
880 void (*gart_tlb_flush)(struct radeon_device *rdev);
881 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
882 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
883 void (*cp_fini)(struct radeon_device *rdev);
884 void (*cp_disable)(struct radeon_device *rdev);
885 void (*cp_commit)(struct radeon_device *rdev);
886 void (*ring_start)(struct radeon_device *rdev);
887 int (*ring_test)(struct radeon_device *rdev);
888 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
889 int (*irq_set)(struct radeon_device *rdev);
890 int (*irq_process)(struct radeon_device *rdev);
891 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
892 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
893 int (*cs_parse)(struct radeon_cs_parser *p);
894 int (*copy_blit)(struct radeon_device *rdev,
895 uint64_t src_offset,
896 uint64_t dst_offset,
897 unsigned num_pages,
898 struct radeon_fence *fence);
899 int (*copy_dma)(struct radeon_device *rdev,
900 uint64_t src_offset,
901 uint64_t dst_offset,
902 unsigned num_pages,
903 struct radeon_fence *fence);
904 int (*copy)(struct radeon_device *rdev,
905 uint64_t src_offset,
906 uint64_t dst_offset,
907 unsigned num_pages,
908 struct radeon_fence *fence);
909 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
910 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
911 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
912 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
913 int (*get_pcie_lanes)(struct radeon_device *rdev);
914 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
915 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
916 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
917 uint32_t tiling_flags, uint32_t pitch,
918 uint32_t offset, uint32_t obj_size);
919 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
920 void (*bandwidth_update)(struct radeon_device *rdev);
921 void (*hpd_init)(struct radeon_device *rdev);
922 void (*hpd_fini)(struct radeon_device *rdev);
923 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
924 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
925
926
927
928
929
930
931 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
932 bool (*gui_idle)(struct radeon_device *rdev);
933
934 void (*pm_misc)(struct radeon_device *rdev);
935 void (*pm_prepare)(struct radeon_device *rdev);
936 void (*pm_finish)(struct radeon_device *rdev);
937 void (*pm_init_profile)(struct radeon_device *rdev);
938 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
939
940 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
941 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
942 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
943};
944
945
946
947
948struct r100_gpu_lockup {
949 unsigned long last_jiffies;
950 u32 last_cp_rptr;
951};
952
953struct r100_asic {
954 const unsigned *reg_safe_bm;
955 unsigned reg_safe_bm_size;
956 u32 hdp_cntl;
957 struct r100_gpu_lockup lockup;
958};
959
960struct r300_asic {
961 const unsigned *reg_safe_bm;
962 unsigned reg_safe_bm_size;
963 u32 resync_scratch;
964 u32 hdp_cntl;
965 struct r100_gpu_lockup lockup;
966};
967
968struct r600_asic {
969 unsigned max_pipes;
970 unsigned max_tile_pipes;
971 unsigned max_simds;
972 unsigned max_backends;
973 unsigned max_gprs;
974 unsigned max_threads;
975 unsigned max_stack_entries;
976 unsigned max_hw_contexts;
977 unsigned max_gs_threads;
978 unsigned sx_max_export_size;
979 unsigned sx_max_export_pos_size;
980 unsigned sx_max_export_smx_size;
981 unsigned sq_num_cf_insts;
982 unsigned tiling_nbanks;
983 unsigned tiling_npipes;
984 unsigned tiling_group_size;
985 unsigned tile_config;
986 struct r100_gpu_lockup lockup;
987};
988
989struct rv770_asic {
990 unsigned max_pipes;
991 unsigned max_tile_pipes;
992 unsigned max_simds;
993 unsigned max_backends;
994 unsigned max_gprs;
995 unsigned max_threads;
996 unsigned max_stack_entries;
997 unsigned max_hw_contexts;
998 unsigned max_gs_threads;
999 unsigned sx_max_export_size;
1000 unsigned sx_max_export_pos_size;
1001 unsigned sx_max_export_smx_size;
1002 unsigned sq_num_cf_insts;
1003 unsigned sx_num_of_sets;
1004 unsigned sc_prim_fifo_size;
1005 unsigned sc_hiz_tile_fifo_size;
1006 unsigned sc_earlyz_tile_fifo_fize;
1007 unsigned tiling_nbanks;
1008 unsigned tiling_npipes;
1009 unsigned tiling_group_size;
1010 unsigned tile_config;
1011 struct r100_gpu_lockup lockup;
1012};
1013
1014struct evergreen_asic {
1015 unsigned num_ses;
1016 unsigned max_pipes;
1017 unsigned max_tile_pipes;
1018 unsigned max_simds;
1019 unsigned max_backends;
1020 unsigned max_gprs;
1021 unsigned max_threads;
1022 unsigned max_stack_entries;
1023 unsigned max_hw_contexts;
1024 unsigned max_gs_threads;
1025 unsigned sx_max_export_size;
1026 unsigned sx_max_export_pos_size;
1027 unsigned sx_max_export_smx_size;
1028 unsigned sq_num_cf_insts;
1029 unsigned sx_num_of_sets;
1030 unsigned sc_prim_fifo_size;
1031 unsigned sc_hiz_tile_fifo_size;
1032 unsigned sc_earlyz_tile_fifo_size;
1033 unsigned tiling_nbanks;
1034 unsigned tiling_npipes;
1035 unsigned tiling_group_size;
1036 unsigned tile_config;
1037 struct r100_gpu_lockup lockup;
1038};
1039
1040union radeon_asic_config {
1041 struct r300_asic r300;
1042 struct r100_asic r100;
1043 struct r600_asic r600;
1044 struct rv770_asic rv770;
1045 struct evergreen_asic evergreen;
1046};
1047
1048
1049
1050
1051void radeon_agp_disable(struct radeon_device *rdev);
1052int radeon_asic_init(struct radeon_device *rdev);
1053
1054
1055
1056
1057
1058int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1059 struct drm_file *filp);
1060int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1061 struct drm_file *filp);
1062int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1063 struct drm_file *file_priv);
1064int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1065 struct drm_file *file_priv);
1066int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1067 struct drm_file *file_priv);
1068int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1069 struct drm_file *file_priv);
1070int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1071 struct drm_file *filp);
1072int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1073 struct drm_file *filp);
1074int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1075 struct drm_file *filp);
1076int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1077 struct drm_file *filp);
1078int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1079int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1080 struct drm_file *filp);
1081int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1082 struct drm_file *filp);
1083
1084
1085struct r700_vram_scratch {
1086 struct radeon_bo *robj;
1087 volatile uint32_t *ptr;
1088};
1089
1090
1091
1092
1093typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1094typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1095
1096struct radeon_device {
1097 struct device *dev;
1098 struct drm_device *ddev;
1099 struct pci_dev *pdev;
1100
1101 union radeon_asic_config config;
1102 enum radeon_family family;
1103 unsigned long flags;
1104 int usec_timeout;
1105 enum radeon_pll_errata pll_errata;
1106 int num_gb_pipes;
1107 int num_z_pipes;
1108 int disp_priority;
1109
1110 uint8_t *bios;
1111 bool is_atom_bios;
1112 uint16_t bios_header_start;
1113 struct radeon_bo *stollen_vga_memory;
1114
1115 resource_size_t rmmio_base;
1116 resource_size_t rmmio_size;
1117 void *rmmio;
1118 radeon_rreg_t mc_rreg;
1119 radeon_wreg_t mc_wreg;
1120 radeon_rreg_t pll_rreg;
1121 radeon_wreg_t pll_wreg;
1122 uint32_t pcie_reg_mask;
1123 radeon_rreg_t pciep_rreg;
1124 radeon_wreg_t pciep_wreg;
1125
1126 void __iomem *rio_mem;
1127 resource_size_t rio_mem_size;
1128 struct radeon_clock clock;
1129 struct radeon_mc mc;
1130 struct radeon_gart gart;
1131 struct radeon_mode_info mode_info;
1132 struct radeon_scratch scratch;
1133 struct radeon_mman mman;
1134 struct radeon_fence_driver fence_drv;
1135 struct radeon_cp cp;
1136 struct radeon_ib_pool ib_pool;
1137 struct radeon_irq irq;
1138 struct radeon_asic *asic;
1139 struct radeon_gem gem;
1140 struct radeon_pm pm;
1141 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1142 struct mutex cs_mutex;
1143 struct radeon_wb wb;
1144 struct radeon_dummy_page dummy_page;
1145 bool gpu_lockup;
1146 bool shutdown;
1147 bool suspend;
1148 bool need_dma32;
1149 bool accel_working;
1150 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1151 const struct firmware *me_fw;
1152 const struct firmware *pfp_fw;
1153 const struct firmware *rlc_fw;
1154 const struct firmware *mc_fw;
1155 struct r600_blit r600_blit;
1156 struct r700_vram_scratch vram_scratch;
1157 int msi_enabled;
1158 struct r600_ih ih;
1159 struct work_struct hotplug_work;
1160 int num_crtc;
1161 struct mutex dc_hw_i2c_mutex;
1162 struct mutex vram_mutex;
1163
1164
1165 bool audio_enabled;
1166 struct timer_list audio_timer;
1167 int audio_channels;
1168 int audio_rate;
1169 int audio_bits_per_sample;
1170 uint8_t audio_status_bits;
1171 uint8_t audio_category_code;
1172
1173 struct notifier_block acpi_nb;
1174
1175 struct drm_file *hyperz_filp;
1176 struct drm_file *cmask_filp;
1177
1178 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1179};
1180
1181int radeon_device_init(struct radeon_device *rdev,
1182 struct drm_device *ddev,
1183 struct pci_dev *pdev,
1184 uint32_t flags);
1185void radeon_device_fini(struct radeon_device *rdev);
1186int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1187
1188
1189int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
1190void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
1191void r600_kms_blit_copy(struct radeon_device *rdev,
1192 u64 src_gpu_addr, u64 dst_gpu_addr,
1193 int size_bytes);
1194
1195int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
1196void evergreen_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
1197void evergreen_kms_blit_copy(struct radeon_device *rdev,
1198 u64 src_gpu_addr, u64 dst_gpu_addr,
1199 int size_bytes);
1200
1201static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1202{
1203 if (reg < rdev->rmmio_size)
1204 return readl(((void __iomem *)rdev->rmmio) + reg);
1205 else {
1206 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1207 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1208 }
1209}
1210
1211static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1212{
1213 if (reg < rdev->rmmio_size)
1214 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1215 else {
1216 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1217 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1218 }
1219}
1220
1221static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
1222{
1223 if (reg < rdev->rio_mem_size)
1224 return ioread32(rdev->rio_mem + reg);
1225 else {
1226 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1227 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
1228 }
1229}
1230
1231static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1232{
1233 if (reg < rdev->rio_mem_size)
1234 iowrite32(v, rdev->rio_mem + reg);
1235 else {
1236 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1237 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
1238 }
1239}
1240
1241
1242
1243
1244#define to_radeon_fence(p) ((struct radeon_fence *)(p))
1245
1246
1247
1248
1249#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
1250#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
1251#define RREG16(reg) readw(((void __iomem *)rdev->rmmio) + (reg))
1252#define WREG16(reg, v) writew(v, ((void __iomem *)rdev->rmmio) + (reg))
1253#define RREG32(reg) r100_mm_rreg(rdev, (reg))
1254#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1255#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1256#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1257#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1258#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1259#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1260#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1261#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1262#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1263#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1264#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1265#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1266#define WREG32_P(reg, val, mask) \
1267 do { \
1268 uint32_t tmp_ = RREG32(reg); \
1269 tmp_ &= (mask); \
1270 tmp_ |= ((val) & ~(mask)); \
1271 WREG32(reg, tmp_); \
1272 } while (0)
1273#define WREG32_PLL_P(reg, val, mask) \
1274 do { \
1275 uint32_t tmp_ = RREG32_PLL(reg); \
1276 tmp_ &= (mask); \
1277 tmp_ |= ((val) & ~(mask)); \
1278 WREG32_PLL(reg, tmp_); \
1279 } while (0)
1280#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1281#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1282#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1283
1284
1285
1286
1287static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1288{
1289 uint32_t r;
1290
1291 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1292 r = RREG32(RADEON_PCIE_DATA);
1293 return r;
1294}
1295
1296static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1297{
1298 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1299 WREG32(RADEON_PCIE_DATA, (v));
1300}
1301
1302void r100_pll_errata_after_index(struct radeon_device *rdev);
1303
1304
1305
1306
1307
1308#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1309 (rdev->pdev->device == 0x5969))
1310#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1311 (rdev->family == CHIP_RV200) || \
1312 (rdev->family == CHIP_RS100) || \
1313 (rdev->family == CHIP_RS200) || \
1314 (rdev->family == CHIP_RV250) || \
1315 (rdev->family == CHIP_RV280) || \
1316 (rdev->family == CHIP_RS300))
1317#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1318 (rdev->family == CHIP_RV350) || \
1319 (rdev->family == CHIP_R350) || \
1320 (rdev->family == CHIP_RV380) || \
1321 (rdev->family == CHIP_R420) || \
1322 (rdev->family == CHIP_R423) || \
1323 (rdev->family == CHIP_RV410) || \
1324 (rdev->family == CHIP_RS400) || \
1325 (rdev->family == CHIP_RS480))
1326#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1327 (rdev->ddev->pdev->device == 0x9443) || \
1328 (rdev->ddev->pdev->device == 0x944B) || \
1329 (rdev->ddev->pdev->device == 0x9506) || \
1330 (rdev->ddev->pdev->device == 0x9509) || \
1331 (rdev->ddev->pdev->device == 0x950F) || \
1332 (rdev->ddev->pdev->device == 0x689C) || \
1333 (rdev->ddev->pdev->device == 0x689D))
1334#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1335#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1336 (rdev->family == CHIP_RS690) || \
1337 (rdev->family == CHIP_RS740) || \
1338 (rdev->family >= CHIP_R600))
1339#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1340#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1341#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1342#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1343 (rdev->flags & RADEON_IS_IGP))
1344#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1345
1346
1347
1348
1349#define RBIOS8(i) (rdev->bios[i])
1350#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1351#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1352
1353int radeon_combios_init(struct radeon_device *rdev);
1354void radeon_combios_fini(struct radeon_device *rdev);
1355int radeon_atombios_init(struct radeon_device *rdev);
1356void radeon_atombios_fini(struct radeon_device *rdev);
1357
1358
1359
1360
1361
1362static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1363{
1364#if DRM_DEBUG_CODE
1365 if (rdev->cp.count_dw <= 0) {
1366 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1367 }
1368#endif
1369 rdev->cp.ring[rdev->cp.wptr++] = v;
1370 rdev->cp.wptr &= rdev->cp.ptr_mask;
1371 rdev->cp.count_dw--;
1372 rdev->cp.ring_free_dw--;
1373}
1374
1375
1376
1377
1378
1379#define radeon_init(rdev) (rdev)->asic->init((rdev))
1380#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1381#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1382#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1383#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1384#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1385#define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
1386#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1387#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1388#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1389#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1390#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1391#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1392#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1393#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1394#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1395#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1396#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1397#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1398#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1399#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1400#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1401#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1402#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1403#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1404#define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1405#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1406#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1407#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1408#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1409#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1410#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1411#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1412#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1413#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1414#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1415#define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1416#define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1417#define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1418#define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1419#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
1420#define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc))
1421#define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base))
1422#define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc))
1423
1424
1425
1426extern int radeon_gpu_reset(struct radeon_device *rdev);
1427extern void radeon_agp_disable(struct radeon_device *rdev);
1428extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1429extern void radeon_gart_restore(struct radeon_device *rdev);
1430extern int radeon_modeset_init(struct radeon_device *rdev);
1431extern void radeon_modeset_fini(struct radeon_device *rdev);
1432extern bool radeon_card_posted(struct radeon_device *rdev);
1433extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1434extern void radeon_update_display_priority(struct radeon_device *rdev);
1435extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1436extern void radeon_scratch_init(struct radeon_device *rdev);
1437extern void radeon_wb_fini(struct radeon_device *rdev);
1438extern int radeon_wb_init(struct radeon_device *rdev);
1439extern void radeon_wb_disable(struct radeon_device *rdev);
1440extern void radeon_surface_init(struct radeon_device *rdev);
1441extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1442extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1443extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1444extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1445extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1446extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1447extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1448extern int radeon_resume_kms(struct drm_device *dev);
1449extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1450extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1451
1452
1453extern bool r600_card_posted(struct radeon_device *rdev);
1454extern void r600_cp_stop(struct radeon_device *rdev);
1455extern int r600_cp_start(struct radeon_device *rdev);
1456extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1457extern int r600_cp_resume(struct radeon_device *rdev);
1458extern void r600_cp_fini(struct radeon_device *rdev);
1459extern int r600_count_pipe_bits(uint32_t val);
1460extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1461extern int r600_pcie_gart_init(struct radeon_device *rdev);
1462extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1463extern int r600_ib_test(struct radeon_device *rdev);
1464extern int r600_ring_test(struct radeon_device *rdev);
1465extern void r600_scratch_init(struct radeon_device *rdev);
1466extern int r600_blit_init(struct radeon_device *rdev);
1467extern void r600_blit_fini(struct radeon_device *rdev);
1468extern int r600_init_microcode(struct radeon_device *rdev);
1469extern int r600_asic_reset(struct radeon_device *rdev);
1470
1471extern int r600_irq_init(struct radeon_device *rdev);
1472extern void r600_irq_fini(struct radeon_device *rdev);
1473extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1474extern int r600_irq_set(struct radeon_device *rdev);
1475extern void r600_irq_suspend(struct radeon_device *rdev);
1476extern void r600_disable_interrupts(struct radeon_device *rdev);
1477extern void r600_rlc_stop(struct radeon_device *rdev);
1478
1479extern int r600_audio_init(struct radeon_device *rdev);
1480extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1481extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1482extern int r600_audio_channels(struct radeon_device *rdev);
1483extern int r600_audio_bits_per_sample(struct radeon_device *rdev);
1484extern int r600_audio_rate(struct radeon_device *rdev);
1485extern uint8_t r600_audio_status_bits(struct radeon_device *rdev);
1486extern uint8_t r600_audio_category_code(struct radeon_device *rdev);
1487extern void r600_audio_schedule_polling(struct radeon_device *rdev);
1488extern void r600_audio_enable_polling(struct drm_encoder *encoder);
1489extern void r600_audio_disable_polling(struct drm_encoder *encoder);
1490extern void r600_audio_fini(struct radeon_device *rdev);
1491extern void r600_hdmi_init(struct drm_encoder *encoder);
1492extern void r600_hdmi_enable(struct drm_encoder *encoder);
1493extern void r600_hdmi_disable(struct drm_encoder *encoder);
1494extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1495extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1496extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
1497
1498extern void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1499extern void r700_cp_stop(struct radeon_device *rdev);
1500extern void r700_cp_fini(struct radeon_device *rdev);
1501extern void evergreen_disable_interrupt_state(struct radeon_device *rdev);
1502extern int evergreen_irq_set(struct radeon_device *rdev);
1503extern int evergreen_blit_init(struct radeon_device *rdev);
1504extern void evergreen_blit_fini(struct radeon_device *rdev);
1505
1506extern int ni_init_microcode(struct radeon_device *rdev);
1507extern int btc_mc_load_microcode(struct radeon_device *rdev);
1508
1509
1510#if defined(CONFIG_ACPI)
1511extern int radeon_acpi_init(struct radeon_device *rdev);
1512#else
1513static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1514#endif
1515
1516
1517struct evergreen_mc_save {
1518 u32 vga_control[6];
1519 u32 vga_render_control;
1520 u32 vga_hdp_control;
1521 u32 crtc_control[6];
1522};
1523
1524#include "radeon_object.h"
1525
1526#endif
1527