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30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
33#include <drm_crtc.h>
34#include <drm_mode.h>
35#include <drm_edid.h>
36#include <drm_dp_helper.h>
37#include <drm_fixed.h>
38#include <drm_crtc_helper.h>
39#include <linux/i2c.h>
40#include <linux/i2c-algo-bit.h>
41
42struct radeon_bo;
43struct radeon_device;
44
45#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
46#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
47#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
48#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
49
50enum radeon_rmx_type {
51 RMX_OFF,
52 RMX_FULL,
53 RMX_CENTER,
54 RMX_ASPECT
55};
56
57enum radeon_tv_std {
58 TV_STD_NTSC,
59 TV_STD_PAL,
60 TV_STD_PAL_M,
61 TV_STD_PAL_60,
62 TV_STD_NTSC_J,
63 TV_STD_SCART_PAL,
64 TV_STD_SECAM,
65 TV_STD_PAL_CN,
66 TV_STD_PAL_N,
67};
68
69enum radeon_underscan_type {
70 UNDERSCAN_OFF,
71 UNDERSCAN_ON,
72 UNDERSCAN_AUTO,
73};
74
75enum radeon_hpd_id {
76 RADEON_HPD_1 = 0,
77 RADEON_HPD_2,
78 RADEON_HPD_3,
79 RADEON_HPD_4,
80 RADEON_HPD_5,
81 RADEON_HPD_6,
82 RADEON_HPD_NONE = 0xff,
83};
84
85#define RADEON_MAX_I2C_BUS 16
86
87
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96
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99
100
101struct radeon_i2c_bus_rec {
102 bool valid;
103
104 uint8_t i2c_id;
105
106 enum radeon_hpd_id hpd;
107
108 bool hw_capable;
109
110 bool mm_i2c;
111
112 uint32_t mask_clk_reg;
113 uint32_t mask_data_reg;
114 uint32_t a_clk_reg;
115 uint32_t a_data_reg;
116 uint32_t en_clk_reg;
117 uint32_t en_data_reg;
118 uint32_t y_clk_reg;
119 uint32_t y_data_reg;
120 uint32_t mask_clk_mask;
121 uint32_t mask_data_mask;
122 uint32_t a_clk_mask;
123 uint32_t a_data_mask;
124 uint32_t en_clk_mask;
125 uint32_t en_data_mask;
126 uint32_t y_clk_mask;
127 uint32_t y_data_mask;
128};
129
130struct radeon_tmds_pll {
131 uint32_t freq;
132 uint32_t value;
133};
134
135#define RADEON_MAX_BIOS_CONNECTOR 16
136
137
138#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
139#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
140#define RADEON_PLL_USE_REF_DIV (1 << 2)
141#define RADEON_PLL_LEGACY (1 << 3)
142#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
143#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
144#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
145#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
146#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
147#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
148#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
149#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
150#define RADEON_PLL_USE_POST_DIV (1 << 12)
151#define RADEON_PLL_IS_LCD (1 << 13)
152#define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
153
154struct radeon_pll {
155
156 uint32_t reference_freq;
157
158
159 uint32_t reference_div;
160 uint32_t post_div;
161
162
163 uint32_t pll_in_min;
164 uint32_t pll_in_max;
165 uint32_t pll_out_min;
166 uint32_t pll_out_max;
167 uint32_t lcd_pll_out_min;
168 uint32_t lcd_pll_out_max;
169 uint32_t best_vco;
170
171
172 uint32_t min_ref_div;
173 uint32_t max_ref_div;
174 uint32_t min_post_div;
175 uint32_t max_post_div;
176 uint32_t min_feedback_div;
177 uint32_t max_feedback_div;
178 uint32_t min_frac_feedback_div;
179 uint32_t max_frac_feedback_div;
180
181
182 uint32_t flags;
183
184
185 uint32_t id;
186};
187
188struct radeon_i2c_chan {
189 struct i2c_adapter adapter;
190 struct drm_device *dev;
191 union {
192 struct i2c_algo_bit_data bit;
193 struct i2c_algo_dp_aux_data dp;
194 } algo;
195 struct radeon_i2c_bus_rec rec;
196};
197
198
199enum radeon_connector_table {
200 CT_NONE = 0,
201 CT_GENERIC,
202 CT_IBOOK,
203 CT_POWERBOOK_EXTERNAL,
204 CT_POWERBOOK_INTERNAL,
205 CT_POWERBOOK_VGA,
206 CT_MINI_EXTERNAL,
207 CT_MINI_INTERNAL,
208 CT_IMAC_G5_ISIGHT,
209 CT_EMAC,
210 CT_RN50_POWER,
211 CT_MAC_X800,
212 CT_MAC_G5_9600,
213};
214
215enum radeon_dvo_chip {
216 DVO_SIL164,
217 DVO_SIL1178,
218};
219
220struct radeon_fbdev;
221
222struct radeon_mode_info {
223 struct atom_context *atom_context;
224 struct card_info *atom_card_info;
225 enum radeon_connector_table connector_table;
226 bool mode_config_initialized;
227 struct radeon_crtc *crtcs[6];
228
229 struct drm_property *coherent_mode_property;
230
231 struct drm_property *load_detect_property;
232
233 struct drm_property *tv_std_property;
234
235 struct drm_property *tmds_pll_property;
236
237 struct drm_property *underscan_property;
238 struct drm_property *underscan_hborder_property;
239 struct drm_property *underscan_vborder_property;
240
241 struct edid *bios_hardcoded_edid;
242
243
244 struct radeon_fbdev *rfbdev;
245};
246
247#define MAX_H_CODE_TIMING_LEN 32
248#define MAX_V_CODE_TIMING_LEN 32
249
250
251
252struct radeon_tv_regs {
253 uint32_t tv_uv_adr;
254 uint32_t timing_cntl;
255 uint32_t hrestart;
256 uint32_t vrestart;
257 uint32_t frestart;
258 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
259 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
260};
261
262struct radeon_crtc {
263 struct drm_crtc base;
264 int crtc_id;
265 u16 lut_r[256], lut_g[256], lut_b[256];
266 bool enabled;
267 bool can_tile;
268 uint32_t crtc_offset;
269 struct drm_gem_object *cursor_bo;
270 uint64_t cursor_addr;
271 int cursor_width;
272 int cursor_height;
273 uint32_t legacy_display_base_addr;
274 uint32_t legacy_cursor_offset;
275 enum radeon_rmx_type rmx_type;
276 u8 h_border;
277 u8 v_border;
278 fixed20_12 vsc;
279 fixed20_12 hsc;
280 struct drm_display_mode native_mode;
281 int pll_id;
282
283 struct radeon_unpin_work *unpin_work;
284 int deferred_flip_completion;
285};
286
287struct radeon_encoder_primary_dac {
288
289 uint32_t ps2_pdac_adj;
290};
291
292struct radeon_encoder_lvds {
293
294 uint16_t panel_vcc_delay;
295 uint8_t panel_pwr_delay;
296 uint8_t panel_digon_delay;
297 uint8_t panel_blon_delay;
298 uint16_t panel_ref_divider;
299 uint8_t panel_post_divider;
300 uint16_t panel_fb_divider;
301 bool use_bios_dividers;
302 uint32_t lvds_gen_cntl;
303
304 struct drm_display_mode native_mode;
305};
306
307struct radeon_encoder_tv_dac {
308
309 uint32_t ps2_tvdac_adj;
310 uint32_t ntsc_tvdac_adj;
311 uint32_t pal_tvdac_adj;
312
313 int h_pos;
314 int v_pos;
315 int h_size;
316 int supported_tv_stds;
317 bool tv_on;
318 enum radeon_tv_std tv_std;
319 struct radeon_tv_regs tv;
320};
321
322struct radeon_encoder_int_tmds {
323
324 struct radeon_tmds_pll tmds_pll[4];
325};
326
327struct radeon_encoder_ext_tmds {
328
329 struct radeon_i2c_chan *i2c_bus;
330 uint8_t slave_addr;
331 enum radeon_dvo_chip dvo_chip;
332};
333
334
335struct radeon_atom_ss {
336 uint16_t percentage;
337 uint8_t type;
338 uint16_t step;
339 uint8_t delay;
340 uint8_t range;
341 uint8_t refdiv;
342
343 uint16_t rate;
344 uint16_t amount;
345};
346
347struct radeon_encoder_atom_dig {
348 bool linkb;
349
350 bool coherent_mode;
351 int dig_encoder;
352
353 uint32_t lcd_misc;
354 uint16_t panel_pwr_delay;
355 uint32_t lcd_ss_id;
356
357 struct drm_display_mode native_mode;
358};
359
360struct radeon_encoder_atom_dac {
361 enum radeon_tv_std tv_std;
362};
363
364struct radeon_encoder {
365 struct drm_encoder base;
366 uint32_t encoder_enum;
367 uint32_t encoder_id;
368 uint32_t devices;
369 uint32_t active_device;
370 uint32_t flags;
371 uint32_t pixel_clock;
372 enum radeon_rmx_type rmx_type;
373 enum radeon_underscan_type underscan_type;
374 uint32_t underscan_hborder;
375 uint32_t underscan_vborder;
376 struct drm_display_mode native_mode;
377 void *enc_priv;
378 int audio_polling_active;
379 int hdmi_offset;
380 int hdmi_config_offset;
381 int hdmi_audio_workaround;
382 int hdmi_buffer_status;
383 bool is_ext_encoder;
384 u16 caps;
385};
386
387struct radeon_connector_atom_dig {
388 uint32_t igp_lane_info;
389
390 struct radeon_i2c_chan *dp_i2c_bus;
391 u8 dpcd[8];
392 u8 dp_sink_type;
393 int dp_clock;
394 int dp_lane_count;
395 bool edp_on;
396};
397
398struct radeon_gpio_rec {
399 bool valid;
400 u8 id;
401 u32 reg;
402 u32 mask;
403};
404
405struct radeon_hpd {
406 enum radeon_hpd_id hpd;
407 u8 plugged_state;
408 struct radeon_gpio_rec gpio;
409};
410
411struct radeon_router {
412 u32 router_id;
413 struct radeon_i2c_bus_rec i2c_info;
414 u8 i2c_addr;
415
416 bool ddc_valid;
417 u8 ddc_mux_type;
418 u8 ddc_mux_control_pin;
419 u8 ddc_mux_state;
420
421 bool cd_valid;
422 u8 cd_mux_type;
423 u8 cd_mux_control_pin;
424 u8 cd_mux_state;
425};
426
427struct radeon_connector {
428 struct drm_connector base;
429 uint32_t connector_id;
430 uint32_t devices;
431 struct radeon_i2c_chan *ddc_bus;
432
433 bool shared_ddc;
434 bool use_digital;
435
436
437 struct edid *edid;
438 void *con_priv;
439 bool dac_load_detect;
440 uint16_t connector_object_id;
441 struct radeon_hpd hpd;
442 struct radeon_router router;
443 struct radeon_i2c_chan *router_bus;
444};
445
446struct radeon_framebuffer {
447 struct drm_framebuffer base;
448 struct drm_gem_object *obj;
449};
450
451
452extern enum radeon_tv_std
453radeon_combios_get_tv_info(struct radeon_device *rdev);
454extern enum radeon_tv_std
455radeon_atombios_get_tv_info(struct radeon_device *rdev);
456
457extern struct drm_connector *
458radeon_get_connector_for_encoder(struct drm_encoder *encoder);
459
460extern void radeon_connector_hotplug(struct drm_connector *connector);
461extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
462extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
463 struct drm_display_mode *mode);
464extern void radeon_dp_set_link_config(struct drm_connector *connector,
465 struct drm_display_mode *mode);
466extern void dp_link_train(struct drm_encoder *encoder,
467 struct drm_connector *connector);
468extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
469extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
470extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action);
471extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
472 int action, uint8_t lane_num,
473 uint8_t lane_set);
474extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
475 uint8_t write_byte, uint8_t *read_byte);
476
477extern void radeon_i2c_init(struct radeon_device *rdev);
478extern void radeon_i2c_fini(struct radeon_device *rdev);
479extern void radeon_combios_i2c_init(struct radeon_device *rdev);
480extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
481extern void radeon_i2c_add(struct radeon_device *rdev,
482 struct radeon_i2c_bus_rec *rec,
483 const char *name);
484extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
485 struct radeon_i2c_bus_rec *i2c_bus);
486extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
487 struct radeon_i2c_bus_rec *rec,
488 const char *name);
489extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
490 struct radeon_i2c_bus_rec *rec,
491 const char *name);
492extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
493extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
494 u8 slave_addr,
495 u8 addr,
496 u8 *val);
497extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
498 u8 slave_addr,
499 u8 addr,
500 u8 val);
501extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
502extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
503extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
504extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
505
506extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
507
508extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
509 struct radeon_atom_ss *ss,
510 int id);
511extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
512 struct radeon_atom_ss *ss,
513 int id, u32 clock);
514
515extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
516 uint64_t freq,
517 uint32_t *dot_clock_p,
518 uint32_t *fb_div_p,
519 uint32_t *frac_fb_div_p,
520 uint32_t *ref_div_p,
521 uint32_t *post_div_p);
522
523extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
524 u32 freq,
525 u32 *dot_clock_p,
526 u32 *fb_div_p,
527 u32 *frac_fb_div_p,
528 u32 *ref_div_p,
529 u32 *post_div_p);
530
531extern void radeon_setup_encoder_clones(struct drm_device *dev);
532
533struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
534struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
535struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
536struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
537struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
538extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
539extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
540extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
541extern void atombios_set_edp_panel_power(struct drm_connector *connector, int action);
542extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
543
544extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
545extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
546 struct drm_framebuffer *old_fb);
547extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
548 struct drm_framebuffer *fb,
549 int x, int y,
550 enum mode_set_atomic state);
551extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
552 struct drm_display_mode *mode,
553 struct drm_display_mode *adjusted_mode,
554 int x, int y,
555 struct drm_framebuffer *old_fb);
556extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
557
558extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
559 struct drm_framebuffer *old_fb);
560extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
561 struct drm_framebuffer *fb,
562 int x, int y,
563 enum mode_set_atomic state);
564extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
565 struct drm_framebuffer *fb,
566 int x, int y, int atomic);
567extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
568 struct drm_file *file_priv,
569 uint32_t handle,
570 uint32_t width,
571 uint32_t height);
572extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
573 int x, int y);
574
575extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
576 int *vpos, int *hpos);
577
578extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
579extern struct edid *
580radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
581extern bool radeon_atom_get_clock_info(struct drm_device *dev);
582extern bool radeon_combios_get_clock_info(struct drm_device *dev);
583extern struct radeon_encoder_atom_dig *
584radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
585extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
586 struct radeon_encoder_int_tmds *tmds);
587extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
588 struct radeon_encoder_int_tmds *tmds);
589extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
590 struct radeon_encoder_int_tmds *tmds);
591extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
592 struct radeon_encoder_ext_tmds *tmds);
593extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
594 struct radeon_encoder_ext_tmds *tmds);
595extern struct radeon_encoder_primary_dac *
596radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
597extern struct radeon_encoder_tv_dac *
598radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
599extern struct radeon_encoder_lvds *
600radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
601extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
602extern struct radeon_encoder_tv_dac *
603radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
604extern struct radeon_encoder_primary_dac *
605radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
606extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
607extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
608extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
609extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
610extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
611extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
612extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
613extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
614extern void
615radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
616extern void
617radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
618extern void
619radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
620extern void
621radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
622extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
623 u16 blue, int regno);
624extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
625 u16 *blue, int regno);
626void radeon_framebuffer_init(struct drm_device *dev,
627 struct radeon_framebuffer *rfb,
628 struct drm_mode_fb_cmd *mode_cmd,
629 struct drm_gem_object *obj);
630
631int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
632bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
633bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
634void radeon_atombios_init_crtc(struct drm_device *dev,
635 struct radeon_crtc *radeon_crtc);
636void radeon_legacy_init_crtc(struct drm_device *dev,
637 struct radeon_crtc *radeon_crtc);
638
639void radeon_get_clock_info(struct drm_device *dev);
640
641extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
642extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
643
644void radeon_enc_destroy(struct drm_encoder *encoder);
645void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
646void radeon_combios_asic_init(struct drm_device *dev);
647bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
648 struct drm_display_mode *mode,
649 struct drm_display_mode *adjusted_mode);
650void radeon_panel_mode_fixup(struct drm_encoder *encoder,
651 struct drm_display_mode *adjusted_mode);
652void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
653
654
655void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
656 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
657 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
658void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
659 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
660 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
661void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
662 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
663 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
664void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
665 struct drm_display_mode *mode,
666 struct drm_display_mode *adjusted_mode);
667
668
669int radeon_fbdev_init(struct radeon_device *rdev);
670void radeon_fbdev_fini(struct radeon_device *rdev);
671void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
672int radeon_fbdev_total_size(struct radeon_device *rdev);
673bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
674
675void radeon_fb_output_poll_changed(struct radeon_device *rdev);
676
677void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
678
679#endif
680
