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32#include <ttm/ttm_bo_api.h>
33#include <ttm/ttm_bo_driver.h>
34#include <ttm/ttm_placement.h>
35#include <ttm/ttm_module.h>
36#include <ttm/ttm_page_alloc.h>
37#include <drm/drmP.h>
38#include <drm/radeon_drm.h>
39#include <linux/seq_file.h>
40#include <linux/slab.h>
41#include "radeon_reg.h"
42#include "radeon.h"
43
44#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
45
46static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
47
48static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
49{
50 struct radeon_mman *mman;
51 struct radeon_device *rdev;
52
53 mman = container_of(bdev, struct radeon_mman, bdev);
54 rdev = container_of(mman, struct radeon_device, mman);
55 return rdev;
56}
57
58
59
60
61
62static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
63{
64 return ttm_mem_global_init(ref->object);
65}
66
67static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
68{
69 ttm_mem_global_release(ref->object);
70}
71
72static int radeon_ttm_global_init(struct radeon_device *rdev)
73{
74 struct drm_global_reference *global_ref;
75 int r;
76
77 rdev->mman.mem_global_referenced = false;
78 global_ref = &rdev->mman.mem_global_ref;
79 global_ref->global_type = DRM_GLOBAL_TTM_MEM;
80 global_ref->size = sizeof(struct ttm_mem_global);
81 global_ref->init = &radeon_ttm_mem_global_init;
82 global_ref->release = &radeon_ttm_mem_global_release;
83 r = drm_global_item_ref(global_ref);
84 if (r != 0) {
85 DRM_ERROR("Failed setting up TTM memory accounting "
86 "subsystem.\n");
87 return r;
88 }
89
90 rdev->mman.bo_global_ref.mem_glob =
91 rdev->mman.mem_global_ref.object;
92 global_ref = &rdev->mman.bo_global_ref.ref;
93 global_ref->global_type = DRM_GLOBAL_TTM_BO;
94 global_ref->size = sizeof(struct ttm_bo_global);
95 global_ref->init = &ttm_bo_global_init;
96 global_ref->release = &ttm_bo_global_release;
97 r = drm_global_item_ref(global_ref);
98 if (r != 0) {
99 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
100 drm_global_item_unref(&rdev->mman.mem_global_ref);
101 return r;
102 }
103
104 rdev->mman.mem_global_referenced = true;
105 return 0;
106}
107
108static void radeon_ttm_global_fini(struct radeon_device *rdev)
109{
110 if (rdev->mman.mem_global_referenced) {
111 drm_global_item_unref(&rdev->mman.bo_global_ref.ref);
112 drm_global_item_unref(&rdev->mman.mem_global_ref);
113 rdev->mman.mem_global_referenced = false;
114 }
115}
116
117struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev);
118
119static struct ttm_backend*
120radeon_create_ttm_backend_entry(struct ttm_bo_device *bdev)
121{
122 struct radeon_device *rdev;
123
124 rdev = radeon_get_rdev(bdev);
125#if __OS_HAS_AGP
126 if (rdev->flags & RADEON_IS_AGP) {
127 return ttm_agp_backend_init(bdev, rdev->ddev->agp->bridge);
128 } else
129#endif
130 {
131 return radeon_ttm_backend_create(rdev);
132 }
133}
134
135static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
136{
137 return 0;
138}
139
140static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
141 struct ttm_mem_type_manager *man)
142{
143 struct radeon_device *rdev;
144
145 rdev = radeon_get_rdev(bdev);
146
147 switch (type) {
148 case TTM_PL_SYSTEM:
149
150 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
151 man->available_caching = TTM_PL_MASK_CACHING;
152 man->default_caching = TTM_PL_FLAG_CACHED;
153 break;
154 case TTM_PL_TT:
155 man->func = &ttm_bo_manager_func;
156 man->gpu_offset = rdev->mc.gtt_start;
157 man->available_caching = TTM_PL_MASK_CACHING;
158 man->default_caching = TTM_PL_FLAG_CACHED;
159 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
160#if __OS_HAS_AGP
161 if (rdev->flags & RADEON_IS_AGP) {
162 if (!(drm_core_has_AGP(rdev->ddev) && rdev->ddev->agp)) {
163 DRM_ERROR("AGP is not enabled for memory type %u\n",
164 (unsigned)type);
165 return -EINVAL;
166 }
167 if (!rdev->ddev->agp->cant_use_aperture)
168 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
169 man->available_caching = TTM_PL_FLAG_UNCACHED |
170 TTM_PL_FLAG_WC;
171 man->default_caching = TTM_PL_FLAG_WC;
172 }
173#endif
174 break;
175 case TTM_PL_VRAM:
176
177 man->func = &ttm_bo_manager_func;
178 man->gpu_offset = rdev->mc.vram_start;
179 man->flags = TTM_MEMTYPE_FLAG_FIXED |
180 TTM_MEMTYPE_FLAG_MAPPABLE;
181 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
182 man->default_caching = TTM_PL_FLAG_WC;
183 break;
184 default:
185 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
186 return -EINVAL;
187 }
188 return 0;
189}
190
191static void radeon_evict_flags(struct ttm_buffer_object *bo,
192 struct ttm_placement *placement)
193{
194 struct radeon_bo *rbo;
195 static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
196
197 if (!radeon_ttm_bo_is_radeon_bo(bo)) {
198 placement->fpfn = 0;
199 placement->lpfn = 0;
200 placement->placement = &placements;
201 placement->busy_placement = &placements;
202 placement->num_placement = 1;
203 placement->num_busy_placement = 1;
204 return;
205 }
206 rbo = container_of(bo, struct radeon_bo, tbo);
207 switch (bo->mem.mem_type) {
208 case TTM_PL_VRAM:
209 if (rbo->rdev->cp.ready == false)
210 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
211 else
212 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
213 break;
214 case TTM_PL_TT:
215 default:
216 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
217 }
218 *placement = rbo->placement;
219}
220
221static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
222{
223 return 0;
224}
225
226static void radeon_move_null(struct ttm_buffer_object *bo,
227 struct ttm_mem_reg *new_mem)
228{
229 struct ttm_mem_reg *old_mem = &bo->mem;
230
231 BUG_ON(old_mem->mm_node != NULL);
232 *old_mem = *new_mem;
233 new_mem->mm_node = NULL;
234}
235
236static int radeon_move_blit(struct ttm_buffer_object *bo,
237 bool evict, int no_wait_reserve, bool no_wait_gpu,
238 struct ttm_mem_reg *new_mem,
239 struct ttm_mem_reg *old_mem)
240{
241 struct radeon_device *rdev;
242 uint64_t old_start, new_start;
243 struct radeon_fence *fence;
244 int r;
245
246 rdev = radeon_get_rdev(bo->bdev);
247 r = radeon_fence_create(rdev, &fence);
248 if (unlikely(r)) {
249 return r;
250 }
251 old_start = old_mem->start << PAGE_SHIFT;
252 new_start = new_mem->start << PAGE_SHIFT;
253
254 switch (old_mem->mem_type) {
255 case TTM_PL_VRAM:
256 old_start += rdev->mc.vram_start;
257 break;
258 case TTM_PL_TT:
259 old_start += rdev->mc.gtt_start;
260 break;
261 default:
262 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
263 return -EINVAL;
264 }
265 switch (new_mem->mem_type) {
266 case TTM_PL_VRAM:
267 new_start += rdev->mc.vram_start;
268 break;
269 case TTM_PL_TT:
270 new_start += rdev->mc.gtt_start;
271 break;
272 default:
273 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
274 return -EINVAL;
275 }
276 if (!rdev->cp.ready) {
277 DRM_ERROR("Trying to move memory with CP turned off.\n");
278 return -EINVAL;
279 }
280 r = radeon_copy(rdev, old_start, new_start, new_mem->num_pages, fence);
281
282 r = ttm_bo_move_accel_cleanup(bo, (void *)fence, NULL,
283 evict, no_wait_reserve, no_wait_gpu, new_mem);
284 radeon_fence_unref(&fence);
285 return r;
286}
287
288static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
289 bool evict, bool interruptible,
290 bool no_wait_reserve, bool no_wait_gpu,
291 struct ttm_mem_reg *new_mem)
292{
293 struct radeon_device *rdev;
294 struct ttm_mem_reg *old_mem = &bo->mem;
295 struct ttm_mem_reg tmp_mem;
296 u32 placements;
297 struct ttm_placement placement;
298 int r;
299
300 rdev = radeon_get_rdev(bo->bdev);
301 tmp_mem = *new_mem;
302 tmp_mem.mm_node = NULL;
303 placement.fpfn = 0;
304 placement.lpfn = 0;
305 placement.num_placement = 1;
306 placement.placement = &placements;
307 placement.num_busy_placement = 1;
308 placement.busy_placement = &placements;
309 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
310 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
311 interruptible, no_wait_reserve, no_wait_gpu);
312 if (unlikely(r)) {
313 return r;
314 }
315
316 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
317 if (unlikely(r)) {
318 goto out_cleanup;
319 }
320
321 r = ttm_tt_bind(bo->ttm, &tmp_mem);
322 if (unlikely(r)) {
323 goto out_cleanup;
324 }
325 r = radeon_move_blit(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem, old_mem);
326 if (unlikely(r)) {
327 goto out_cleanup;
328 }
329 r = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem);
330out_cleanup:
331 ttm_bo_mem_put(bo, &tmp_mem);
332 return r;
333}
334
335static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
336 bool evict, bool interruptible,
337 bool no_wait_reserve, bool no_wait_gpu,
338 struct ttm_mem_reg *new_mem)
339{
340 struct radeon_device *rdev;
341 struct ttm_mem_reg *old_mem = &bo->mem;
342 struct ttm_mem_reg tmp_mem;
343 struct ttm_placement placement;
344 u32 placements;
345 int r;
346
347 rdev = radeon_get_rdev(bo->bdev);
348 tmp_mem = *new_mem;
349 tmp_mem.mm_node = NULL;
350 placement.fpfn = 0;
351 placement.lpfn = 0;
352 placement.num_placement = 1;
353 placement.placement = &placements;
354 placement.num_busy_placement = 1;
355 placement.busy_placement = &placements;
356 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
357 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, interruptible, no_wait_reserve, no_wait_gpu);
358 if (unlikely(r)) {
359 return r;
360 }
361 r = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem);
362 if (unlikely(r)) {
363 goto out_cleanup;
364 }
365 r = radeon_move_blit(bo, true, no_wait_reserve, no_wait_gpu, new_mem, old_mem);
366 if (unlikely(r)) {
367 goto out_cleanup;
368 }
369out_cleanup:
370 ttm_bo_mem_put(bo, &tmp_mem);
371 return r;
372}
373
374static int radeon_bo_move(struct ttm_buffer_object *bo,
375 bool evict, bool interruptible,
376 bool no_wait_reserve, bool no_wait_gpu,
377 struct ttm_mem_reg *new_mem)
378{
379 struct radeon_device *rdev;
380 struct ttm_mem_reg *old_mem = &bo->mem;
381 int r;
382
383 rdev = radeon_get_rdev(bo->bdev);
384 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
385 radeon_move_null(bo, new_mem);
386 return 0;
387 }
388 if ((old_mem->mem_type == TTM_PL_TT &&
389 new_mem->mem_type == TTM_PL_SYSTEM) ||
390 (old_mem->mem_type == TTM_PL_SYSTEM &&
391 new_mem->mem_type == TTM_PL_TT)) {
392
393 radeon_move_null(bo, new_mem);
394 return 0;
395 }
396 if (!rdev->cp.ready || rdev->asic->copy == NULL) {
397
398 goto memcpy;
399 }
400
401 if (old_mem->mem_type == TTM_PL_VRAM &&
402 new_mem->mem_type == TTM_PL_SYSTEM) {
403 r = radeon_move_vram_ram(bo, evict, interruptible,
404 no_wait_reserve, no_wait_gpu, new_mem);
405 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
406 new_mem->mem_type == TTM_PL_VRAM) {
407 r = radeon_move_ram_vram(bo, evict, interruptible,
408 no_wait_reserve, no_wait_gpu, new_mem);
409 } else {
410 r = radeon_move_blit(bo, evict, no_wait_reserve, no_wait_gpu, new_mem, old_mem);
411 }
412
413 if (r) {
414memcpy:
415 r = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
416 }
417 return r;
418}
419
420static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
421{
422 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
423 struct radeon_device *rdev = radeon_get_rdev(bdev);
424
425 mem->bus.addr = NULL;
426 mem->bus.offset = 0;
427 mem->bus.size = mem->num_pages << PAGE_SHIFT;
428 mem->bus.base = 0;
429 mem->bus.is_iomem = false;
430 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
431 return -EINVAL;
432 switch (mem->mem_type) {
433 case TTM_PL_SYSTEM:
434
435 return 0;
436 case TTM_PL_TT:
437#if __OS_HAS_AGP
438 if (rdev->flags & RADEON_IS_AGP) {
439
440 mem->bus.offset = mem->start << PAGE_SHIFT;
441 mem->bus.base = rdev->mc.agp_base;
442 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
443 }
444#endif
445 break;
446 case TTM_PL_VRAM:
447 mem->bus.offset = mem->start << PAGE_SHIFT;
448
449 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
450 return -EINVAL;
451 mem->bus.base = rdev->mc.aper_base;
452 mem->bus.is_iomem = true;
453 break;
454 default:
455 return -EINVAL;
456 }
457 return 0;
458}
459
460static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
461{
462}
463
464static int radeon_sync_obj_wait(void *sync_obj, void *sync_arg,
465 bool lazy, bool interruptible)
466{
467 return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible);
468}
469
470static int radeon_sync_obj_flush(void *sync_obj, void *sync_arg)
471{
472 return 0;
473}
474
475static void radeon_sync_obj_unref(void **sync_obj)
476{
477 radeon_fence_unref((struct radeon_fence **)sync_obj);
478}
479
480static void *radeon_sync_obj_ref(void *sync_obj)
481{
482 return radeon_fence_ref((struct radeon_fence *)sync_obj);
483}
484
485static bool radeon_sync_obj_signaled(void *sync_obj, void *sync_arg)
486{
487 return radeon_fence_signaled((struct radeon_fence *)sync_obj);
488}
489
490static struct ttm_bo_driver radeon_bo_driver = {
491 .create_ttm_backend_entry = &radeon_create_ttm_backend_entry,
492 .invalidate_caches = &radeon_invalidate_caches,
493 .init_mem_type = &radeon_init_mem_type,
494 .evict_flags = &radeon_evict_flags,
495 .move = &radeon_bo_move,
496 .verify_access = &radeon_verify_access,
497 .sync_obj_signaled = &radeon_sync_obj_signaled,
498 .sync_obj_wait = &radeon_sync_obj_wait,
499 .sync_obj_flush = &radeon_sync_obj_flush,
500 .sync_obj_unref = &radeon_sync_obj_unref,
501 .sync_obj_ref = &radeon_sync_obj_ref,
502 .move_notify = &radeon_bo_move_notify,
503 .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
504 .io_mem_reserve = &radeon_ttm_io_mem_reserve,
505 .io_mem_free = &radeon_ttm_io_mem_free,
506};
507
508int radeon_ttm_init(struct radeon_device *rdev)
509{
510 int r;
511
512 r = radeon_ttm_global_init(rdev);
513 if (r) {
514 return r;
515 }
516
517 r = ttm_bo_device_init(&rdev->mman.bdev,
518 rdev->mman.bo_global_ref.ref.object,
519 &radeon_bo_driver, DRM_FILE_PAGE_OFFSET,
520 rdev->need_dma32);
521 if (r) {
522 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
523 return r;
524 }
525 rdev->mman.initialized = true;
526 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
527 rdev->mc.real_vram_size >> PAGE_SHIFT);
528 if (r) {
529 DRM_ERROR("Failed initializing VRAM heap.\n");
530 return r;
531 }
532 r = radeon_bo_create(rdev, NULL, 256 * 1024, PAGE_SIZE, true,
533 RADEON_GEM_DOMAIN_VRAM,
534 &rdev->stollen_vga_memory);
535 if (r) {
536 return r;
537 }
538 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
539 if (r)
540 return r;
541 r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
542 radeon_bo_unreserve(rdev->stollen_vga_memory);
543 if (r) {
544 radeon_bo_unref(&rdev->stollen_vga_memory);
545 return r;
546 }
547 DRM_INFO("radeon: %uM of VRAM memory ready\n",
548 (unsigned)rdev->mc.real_vram_size / (1024 * 1024));
549 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
550 rdev->mc.gtt_size >> PAGE_SHIFT);
551 if (r) {
552 DRM_ERROR("Failed initializing GTT heap.\n");
553 return r;
554 }
555 DRM_INFO("radeon: %uM of GTT memory ready.\n",
556 (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
557 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
558 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
559 }
560
561 r = radeon_ttm_debugfs_init(rdev);
562 if (r) {
563 DRM_ERROR("Failed to init debugfs\n");
564 return r;
565 }
566 return 0;
567}
568
569void radeon_ttm_fini(struct radeon_device *rdev)
570{
571 int r;
572
573 if (!rdev->mman.initialized)
574 return;
575 if (rdev->stollen_vga_memory) {
576 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
577 if (r == 0) {
578 radeon_bo_unpin(rdev->stollen_vga_memory);
579 radeon_bo_unreserve(rdev->stollen_vga_memory);
580 }
581 radeon_bo_unref(&rdev->stollen_vga_memory);
582 }
583 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
584 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
585 ttm_bo_device_release(&rdev->mman.bdev);
586 radeon_gart_fini(rdev);
587 radeon_ttm_global_fini(rdev);
588 rdev->mman.initialized = false;
589 DRM_INFO("radeon: ttm finalized\n");
590}
591
592
593
594void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
595{
596 struct ttm_mem_type_manager *man;
597
598 if (!rdev->mman.initialized)
599 return;
600
601 man = &rdev->mman.bdev.man[TTM_PL_VRAM];
602
603 man->size = size >> PAGE_SHIFT;
604}
605
606static struct vm_operations_struct radeon_ttm_vm_ops;
607static const struct vm_operations_struct *ttm_vm_ops = NULL;
608
609static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
610{
611 struct ttm_buffer_object *bo;
612 struct radeon_device *rdev;
613 int r;
614
615 bo = (struct ttm_buffer_object *)vma->vm_private_data;
616 if (bo == NULL) {
617 return VM_FAULT_NOPAGE;
618 }
619 rdev = radeon_get_rdev(bo->bdev);
620 mutex_lock(&rdev->vram_mutex);
621 r = ttm_vm_ops->fault(vma, vmf);
622 mutex_unlock(&rdev->vram_mutex);
623 return r;
624}
625
626int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
627{
628 struct drm_file *file_priv;
629 struct radeon_device *rdev;
630 int r;
631
632 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
633 return drm_mmap(filp, vma);
634 }
635
636 file_priv = filp->private_data;
637 rdev = file_priv->minor->dev->dev_private;
638 if (rdev == NULL) {
639 return -EINVAL;
640 }
641 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
642 if (unlikely(r != 0)) {
643 return r;
644 }
645 if (unlikely(ttm_vm_ops == NULL)) {
646 ttm_vm_ops = vma->vm_ops;
647 radeon_ttm_vm_ops = *ttm_vm_ops;
648 radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
649 }
650 vma->vm_ops = &radeon_ttm_vm_ops;
651 return 0;
652}
653
654
655
656
657
658struct radeon_ttm_backend {
659 struct ttm_backend backend;
660 struct radeon_device *rdev;
661 unsigned long num_pages;
662 struct page **pages;
663 struct page *dummy_read_page;
664 bool populated;
665 bool bound;
666 unsigned offset;
667};
668
669static int radeon_ttm_backend_populate(struct ttm_backend *backend,
670 unsigned long num_pages,
671 struct page **pages,
672 struct page *dummy_read_page)
673{
674 struct radeon_ttm_backend *gtt;
675
676 gtt = container_of(backend, struct radeon_ttm_backend, backend);
677 gtt->pages = pages;
678 gtt->num_pages = num_pages;
679 gtt->dummy_read_page = dummy_read_page;
680 gtt->populated = true;
681 return 0;
682}
683
684static void radeon_ttm_backend_clear(struct ttm_backend *backend)
685{
686 struct radeon_ttm_backend *gtt;
687
688 gtt = container_of(backend, struct radeon_ttm_backend, backend);
689 gtt->pages = NULL;
690 gtt->num_pages = 0;
691 gtt->dummy_read_page = NULL;
692 gtt->populated = false;
693 gtt->bound = false;
694}
695
696
697static int radeon_ttm_backend_bind(struct ttm_backend *backend,
698 struct ttm_mem_reg *bo_mem)
699{
700 struct radeon_ttm_backend *gtt;
701 int r;
702
703 gtt = container_of(backend, struct radeon_ttm_backend, backend);
704 gtt->offset = bo_mem->start << PAGE_SHIFT;
705 if (!gtt->num_pages) {
706 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
707 gtt->num_pages, bo_mem, backend);
708 }
709 r = radeon_gart_bind(gtt->rdev, gtt->offset,
710 gtt->num_pages, gtt->pages);
711 if (r) {
712 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
713 gtt->num_pages, gtt->offset);
714 return r;
715 }
716 gtt->bound = true;
717 return 0;
718}
719
720static int radeon_ttm_backend_unbind(struct ttm_backend *backend)
721{
722 struct radeon_ttm_backend *gtt;
723
724 gtt = container_of(backend, struct radeon_ttm_backend, backend);
725 radeon_gart_unbind(gtt->rdev, gtt->offset, gtt->num_pages);
726 gtt->bound = false;
727 return 0;
728}
729
730static void radeon_ttm_backend_destroy(struct ttm_backend *backend)
731{
732 struct radeon_ttm_backend *gtt;
733
734 gtt = container_of(backend, struct radeon_ttm_backend, backend);
735 if (gtt->bound) {
736 radeon_ttm_backend_unbind(backend);
737 }
738 kfree(gtt);
739}
740
741static struct ttm_backend_func radeon_backend_func = {
742 .populate = &radeon_ttm_backend_populate,
743 .clear = &radeon_ttm_backend_clear,
744 .bind = &radeon_ttm_backend_bind,
745 .unbind = &radeon_ttm_backend_unbind,
746 .destroy = &radeon_ttm_backend_destroy,
747};
748
749struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev)
750{
751 struct radeon_ttm_backend *gtt;
752
753 gtt = kzalloc(sizeof(struct radeon_ttm_backend), GFP_KERNEL);
754 if (gtt == NULL) {
755 return NULL;
756 }
757 gtt->backend.bdev = &rdev->mman.bdev;
758 gtt->backend.flags = 0;
759 gtt->backend.func = &radeon_backend_func;
760 gtt->rdev = rdev;
761 gtt->pages = NULL;
762 gtt->num_pages = 0;
763 gtt->dummy_read_page = NULL;
764 gtt->populated = false;
765 gtt->bound = false;
766 return >t->backend;
767}
768
769#define RADEON_DEBUGFS_MEM_TYPES 2
770
771#if defined(CONFIG_DEBUG_FS)
772static int radeon_mm_dump_table(struct seq_file *m, void *data)
773{
774 struct drm_info_node *node = (struct drm_info_node *)m->private;
775 struct drm_mm *mm = (struct drm_mm *)node->info_ent->data;
776 struct drm_device *dev = node->minor->dev;
777 struct radeon_device *rdev = dev->dev_private;
778 int ret;
779 struct ttm_bo_global *glob = rdev->mman.bdev.glob;
780
781 spin_lock(&glob->lru_lock);
782 ret = drm_mm_dump_table(m, mm);
783 spin_unlock(&glob->lru_lock);
784 return ret;
785}
786#endif
787
788static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
789{
790#if defined(CONFIG_DEBUG_FS)
791 static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES+1];
792 static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES+1][32];
793 unsigned i;
794
795 for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) {
796 if (i == 0)
797 sprintf(radeon_mem_types_names[i], "radeon_vram_mm");
798 else
799 sprintf(radeon_mem_types_names[i], "radeon_gtt_mm");
800 radeon_mem_types_list[i].name = radeon_mem_types_names[i];
801 radeon_mem_types_list[i].show = &radeon_mm_dump_table;
802 radeon_mem_types_list[i].driver_features = 0;
803 if (i == 0)
804 radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_VRAM].priv;
805 else
806 radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_TT].priv;
807
808 }
809
810 sprintf(radeon_mem_types_names[i], "ttm_page_pool");
811 radeon_mem_types_list[i].name = radeon_mem_types_names[i];
812 radeon_mem_types_list[i].show = &ttm_page_alloc_debugfs;
813 radeon_mem_types_list[i].driver_features = 0;
814 radeon_mem_types_list[i].data = NULL;
815 return radeon_debugfs_add_files(rdev, radeon_mem_types_list, RADEON_DEBUGFS_MEM_TYPES+1);
816
817#endif
818 return 0;
819}
820
