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28#include "drmP.h"
29#include "radeon.h"
30#include "radeon_asic.h"
31#include "atom.h"
32#include "rs690d.h"
33
34static int rs690_mc_wait_for_idle(struct radeon_device *rdev)
35{
36 unsigned i;
37 uint32_t tmp;
38
39 for (i = 0; i < rdev->usec_timeout; i++) {
40
41 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
42 if (G_000090_MC_SYSTEM_IDLE(tmp))
43 return 0;
44 udelay(1);
45 }
46 return -1;
47}
48
49static void rs690_gpu_init(struct radeon_device *rdev)
50{
51
52 r420_pipes_init(rdev);
53 if (rs690_mc_wait_for_idle(rdev)) {
54 printk(KERN_WARNING "Failed to wait MC idle while "
55 "programming pipes. Bad things might happen.\n");
56 }
57}
58
59union igp_info {
60 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
61 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
62};
63
64void rs690_pm_info(struct radeon_device *rdev)
65{
66 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
67 union igp_info *info;
68 uint16_t data_offset;
69 uint8_t frev, crev;
70 fixed20_12 tmp;
71
72 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
73 &frev, &crev, &data_offset)) {
74 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
75
76
77 switch (crev) {
78 case 1:
79 tmp.full = dfixed_const(100);
80 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock));
81 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
82 if (le16_to_cpu(info->info.usK8MemoryClock))
83 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
84 else if (rdev->clock.default_mclk) {
85 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
86 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
87 } else
88 rdev->pm.igp_system_mclk.full = dfixed_const(400);
89 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
90 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
91 break;
92 case 2:
93 tmp.full = dfixed_const(100);
94 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock));
95 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
96 if (le32_to_cpu(info->info_v2.ulBootUpUMAClock))
97 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock));
98 else if (rdev->clock.default_mclk)
99 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
100 else
101 rdev->pm.igp_system_mclk.full = dfixed_const(66700);
102 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
103 rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq));
104 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
105 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
106 break;
107 default:
108
109 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
110 rdev->pm.igp_system_mclk.full = dfixed_const(200);
111 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
112 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
113 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
114 break;
115 }
116 } else {
117
118 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
119 rdev->pm.igp_system_mclk.full = dfixed_const(200);
120 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
121 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
122 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
123 }
124
125
126 tmp.full = dfixed_const(4);
127 rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
128
129
130
131 tmp.full = dfixed_const(5);
132 rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
133 rdev->pm.igp_ht_link_width);
134 rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
135 if (tmp.full < rdev->pm.max_bandwidth.full) {
136
137 rdev->pm.max_bandwidth.full = tmp.full;
138 }
139
140
141
142 tmp.full = dfixed_const(14);
143 rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
144 tmp.full = dfixed_const(10);
145 rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
146}
147
148void rs690_mc_init(struct radeon_device *rdev)
149{
150 u64 base;
151
152 rs400_gart_adjust_size(rdev);
153 rdev->mc.vram_is_ddr = true;
154 rdev->mc.vram_width = 128;
155 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
156 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
157 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
158 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
159 rdev->mc.visible_vram_size = rdev->mc.aper_size;
160 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
161 base = G_000100_MC_FB_START(base) << 16;
162 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
163 rs690_pm_info(rdev);
164 radeon_vram_location(rdev, &rdev->mc, base);
165 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
166 radeon_gtt_location(rdev, &rdev->mc);
167 radeon_update_bandwidth_info(rdev);
168}
169
170void rs690_line_buffer_adjust(struct radeon_device *rdev,
171 struct drm_display_mode *mode1,
172 struct drm_display_mode *mode2)
173{
174 u32 tmp;
175
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189
190 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
191 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
192
193 if (mode1 && mode2) {
194 if (mode1->hdisplay > mode2->hdisplay) {
195 if (mode1->hdisplay > 2560)
196 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
197 else
198 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
199 } else if (mode2->hdisplay > mode1->hdisplay) {
200 if (mode2->hdisplay > 2560)
201 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
202 else
203 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
204 } else
205 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
206 } else if (mode1) {
207 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
208 } else if (mode2) {
209 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
210 }
211 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
212}
213
214struct rs690_watermark {
215 u32 lb_request_fifo_depth;
216 fixed20_12 num_line_pair;
217 fixed20_12 estimated_width;
218 fixed20_12 worst_case_latency;
219 fixed20_12 consumption_rate;
220 fixed20_12 active_time;
221 fixed20_12 dbpp;
222 fixed20_12 priority_mark_max;
223 fixed20_12 priority_mark;
224 fixed20_12 sclk;
225};
226
227void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
228 struct radeon_crtc *crtc,
229 struct rs690_watermark *wm)
230{
231 struct drm_display_mode *mode = &crtc->base.mode;
232 fixed20_12 a, b, c;
233 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
234 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
235
236 if (!crtc->base.enabled) {
237
238 wm->lb_request_fifo_depth = 4;
239 return;
240 }
241
242 if (crtc->vsc.full > dfixed_const(2))
243 wm->num_line_pair.full = dfixed_const(2);
244 else
245 wm->num_line_pair.full = dfixed_const(1);
246
247 b.full = dfixed_const(mode->crtc_hdisplay);
248 c.full = dfixed_const(256);
249 a.full = dfixed_div(b, c);
250 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
251 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
252 if (a.full < dfixed_const(4)) {
253 wm->lb_request_fifo_depth = 4;
254 } else {
255 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
256 }
257
258
259
260
261
262
263
264 a.full = dfixed_const(mode->clock);
265 b.full = dfixed_const(1000);
266 a.full = dfixed_div(a, b);
267 pclk.full = dfixed_div(b, a);
268 if (crtc->rmx_type != RMX_OFF) {
269 b.full = dfixed_const(2);
270 if (crtc->vsc.full > b.full)
271 b.full = crtc->vsc.full;
272 b.full = dfixed_mul(b, crtc->hsc);
273 c.full = dfixed_const(2);
274 b.full = dfixed_div(b, c);
275 consumption_time.full = dfixed_div(pclk, b);
276 } else {
277 consumption_time.full = pclk.full;
278 }
279 a.full = dfixed_const(1);
280 wm->consumption_rate.full = dfixed_div(a, consumption_time);
281
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288 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
289 line_time.full = dfixed_mul(a, pclk);
290
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296 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
297 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
298 wm->active_time.full = dfixed_mul(line_time, b);
299 wm->active_time.full = dfixed_div(wm->active_time, a);
300
301
302 rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
303 if (rdev->mc.igp_sideport_enabled) {
304 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
305 rdev->pm.sideport_bandwidth.full)
306 rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
307 read_delay_latency.full = dfixed_const(370 * 800 * 1000);
308 read_delay_latency.full = dfixed_div(read_delay_latency,
309 rdev->pm.igp_sideport_mclk);
310 } else {
311 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
312 rdev->pm.k8_bandwidth.full)
313 rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
314 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
315 rdev->pm.ht_bandwidth.full)
316 rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
317 read_delay_latency.full = dfixed_const(5000);
318 }
319
320
321 a.full = dfixed_const(16);
322 rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a);
323 a.full = dfixed_const(1000);
324 rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk);
325
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329
330 a.full = dfixed_const(256 * 13);
331 chunk_time.full = dfixed_mul(rdev->pm.sclk, a);
332 a.full = dfixed_const(10);
333 chunk_time.full = dfixed_div(chunk_time, a);
334
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341
342
343 if (dfixed_trunc(wm->num_line_pair) > 1) {
344 a.full = dfixed_const(3);
345 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
346 wm->worst_case_latency.full += read_delay_latency.full;
347 } else {
348 a.full = dfixed_const(2);
349 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
350 wm->worst_case_latency.full += read_delay_latency.full;
351 }
352
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361
362
363 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
364 tolerable_latency.full = line_time.full;
365 } else {
366 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
367 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
368 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
369 tolerable_latency.full = line_time.full - tolerable_latency.full;
370 }
371
372 wm->dbpp.full = dfixed_const(4 * 8);
373
374
375
376
377 a.full = dfixed_const(16);
378 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
379 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
380 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
381
382
383 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
384 estimated_width.full = dfixed_div(estimated_width, consumption_time);
385 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
386 wm->priority_mark.full = dfixed_const(10);
387 } else {
388 a.full = dfixed_const(16);
389 wm->priority_mark.full = dfixed_div(estimated_width, a);
390 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
391 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
392 }
393}
394
395void rs690_bandwidth_update(struct radeon_device *rdev)
396{
397 struct drm_display_mode *mode0 = NULL;
398 struct drm_display_mode *mode1 = NULL;
399 struct rs690_watermark wm0;
400 struct rs690_watermark wm1;
401 u32 tmp;
402 u32 d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
403 u32 d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
404 fixed20_12 priority_mark02, priority_mark12, fill_rate;
405 fixed20_12 a, b;
406
407 radeon_update_display_priority(rdev);
408
409 if (rdev->mode_info.crtcs[0]->base.enabled)
410 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
411 if (rdev->mode_info.crtcs[1]->base.enabled)
412 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
413
414
415
416
417
418 if ((rdev->disp_priority == 2) &&
419 ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
420 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
421 tmp &= C_000104_MC_DISP0R_INIT_LAT;
422 tmp &= C_000104_MC_DISP1R_INIT_LAT;
423 if (mode0)
424 tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
425 if (mode1)
426 tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
427 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
428 }
429 rs690_line_buffer_adjust(rdev, mode0, mode1);
430
431 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
432 WREG32(R_006C9C_DCP_CONTROL, 0);
433 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
434 WREG32(R_006C9C_DCP_CONTROL, 2);
435
436 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
437 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
438
439 tmp = (wm0.lb_request_fifo_depth - 1);
440 tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
441 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
442
443 if (mode0 && mode1) {
444 if (dfixed_trunc(wm0.dbpp) > 64)
445 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
446 else
447 a.full = wm0.num_line_pair.full;
448 if (dfixed_trunc(wm1.dbpp) > 64)
449 b.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
450 else
451 b.full = wm1.num_line_pair.full;
452 a.full += b.full;
453 fill_rate.full = dfixed_div(wm0.sclk, a);
454 if (wm0.consumption_rate.full > fill_rate.full) {
455 b.full = wm0.consumption_rate.full - fill_rate.full;
456 b.full = dfixed_mul(b, wm0.active_time);
457 a.full = dfixed_mul(wm0.worst_case_latency,
458 wm0.consumption_rate);
459 a.full = a.full + b.full;
460 b.full = dfixed_const(16 * 1000);
461 priority_mark02.full = dfixed_div(a, b);
462 } else {
463 a.full = dfixed_mul(wm0.worst_case_latency,
464 wm0.consumption_rate);
465 b.full = dfixed_const(16 * 1000);
466 priority_mark02.full = dfixed_div(a, b);
467 }
468 if (wm1.consumption_rate.full > fill_rate.full) {
469 b.full = wm1.consumption_rate.full - fill_rate.full;
470 b.full = dfixed_mul(b, wm1.active_time);
471 a.full = dfixed_mul(wm1.worst_case_latency,
472 wm1.consumption_rate);
473 a.full = a.full + b.full;
474 b.full = dfixed_const(16 * 1000);
475 priority_mark12.full = dfixed_div(a, b);
476 } else {
477 a.full = dfixed_mul(wm1.worst_case_latency,
478 wm1.consumption_rate);
479 b.full = dfixed_const(16 * 1000);
480 priority_mark12.full = dfixed_div(a, b);
481 }
482 if (wm0.priority_mark.full > priority_mark02.full)
483 priority_mark02.full = wm0.priority_mark.full;
484 if (dfixed_trunc(priority_mark02) < 0)
485 priority_mark02.full = 0;
486 if (wm0.priority_mark_max.full > priority_mark02.full)
487 priority_mark02.full = wm0.priority_mark_max.full;
488 if (wm1.priority_mark.full > priority_mark12.full)
489 priority_mark12.full = wm1.priority_mark.full;
490 if (dfixed_trunc(priority_mark12) < 0)
491 priority_mark12.full = 0;
492 if (wm1.priority_mark_max.full > priority_mark12.full)
493 priority_mark12.full = wm1.priority_mark_max.full;
494 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
495 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
496 if (rdev->disp_priority == 2) {
497 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
498 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
499 }
500 } else if (mode0) {
501 if (dfixed_trunc(wm0.dbpp) > 64)
502 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
503 else
504 a.full = wm0.num_line_pair.full;
505 fill_rate.full = dfixed_div(wm0.sclk, a);
506 if (wm0.consumption_rate.full > fill_rate.full) {
507 b.full = wm0.consumption_rate.full - fill_rate.full;
508 b.full = dfixed_mul(b, wm0.active_time);
509 a.full = dfixed_mul(wm0.worst_case_latency,
510 wm0.consumption_rate);
511 a.full = a.full + b.full;
512 b.full = dfixed_const(16 * 1000);
513 priority_mark02.full = dfixed_div(a, b);
514 } else {
515 a.full = dfixed_mul(wm0.worst_case_latency,
516 wm0.consumption_rate);
517 b.full = dfixed_const(16 * 1000);
518 priority_mark02.full = dfixed_div(a, b);
519 }
520 if (wm0.priority_mark.full > priority_mark02.full)
521 priority_mark02.full = wm0.priority_mark.full;
522 if (dfixed_trunc(priority_mark02) < 0)
523 priority_mark02.full = 0;
524 if (wm0.priority_mark_max.full > priority_mark02.full)
525 priority_mark02.full = wm0.priority_mark_max.full;
526 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
527 if (rdev->disp_priority == 2)
528 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
529 } else if (mode1) {
530 if (dfixed_trunc(wm1.dbpp) > 64)
531 a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
532 else
533 a.full = wm1.num_line_pair.full;
534 fill_rate.full = dfixed_div(wm1.sclk, a);
535 if (wm1.consumption_rate.full > fill_rate.full) {
536 b.full = wm1.consumption_rate.full - fill_rate.full;
537 b.full = dfixed_mul(b, wm1.active_time);
538 a.full = dfixed_mul(wm1.worst_case_latency,
539 wm1.consumption_rate);
540 a.full = a.full + b.full;
541 b.full = dfixed_const(16 * 1000);
542 priority_mark12.full = dfixed_div(a, b);
543 } else {
544 a.full = dfixed_mul(wm1.worst_case_latency,
545 wm1.consumption_rate);
546 b.full = dfixed_const(16 * 1000);
547 priority_mark12.full = dfixed_div(a, b);
548 }
549 if (wm1.priority_mark.full > priority_mark12.full)
550 priority_mark12.full = wm1.priority_mark.full;
551 if (dfixed_trunc(priority_mark12) < 0)
552 priority_mark12.full = 0;
553 if (wm1.priority_mark_max.full > priority_mark12.full)
554 priority_mark12.full = wm1.priority_mark_max.full;
555 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
556 if (rdev->disp_priority == 2)
557 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
558 }
559
560 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
561 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
562 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
563 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
564}
565
566uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
567{
568 uint32_t r;
569
570 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
571 r = RREG32(R_00007C_MC_DATA);
572 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
573 return r;
574}
575
576void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
577{
578 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
579 S_000078_MC_IND_WR_EN(1));
580 WREG32(R_00007C_MC_DATA, v);
581 WREG32(R_000078_MC_INDEX, 0x7F);
582}
583
584void rs690_mc_program(struct radeon_device *rdev)
585{
586 struct rv515_mc_save save;
587
588
589 rv515_mc_stop(rdev, &save);
590
591
592 if (rs690_mc_wait_for_idle(rdev))
593 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
594
595 WREG32_MC(R_000100_MCCFG_FB_LOCATION,
596 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
597 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
598 WREG32(R_000134_HDP_FB_LOCATION,
599 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
600
601 rv515_mc_resume(rdev, &save);
602}
603
604static int rs690_startup(struct radeon_device *rdev)
605{
606 int r;
607
608 rs690_mc_program(rdev);
609
610 rv515_clock_startup(rdev);
611
612 rs690_gpu_init(rdev);
613
614
615 r = rs400_gart_enable(rdev);
616 if (r)
617 return r;
618
619
620 r = radeon_wb_init(rdev);
621 if (r)
622 return r;
623
624
625 rs600_irq_set(rdev);
626 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
627
628 r = r100_cp_init(rdev, 1024 * 1024);
629 if (r) {
630 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
631 return r;
632 }
633 r = r100_ib_init(rdev);
634 if (r) {
635 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
636 return r;
637 }
638
639 r = r600_audio_init(rdev);
640 if (r) {
641 dev_err(rdev->dev, "failed initializing audio\n");
642 return r;
643 }
644
645 return 0;
646}
647
648int rs690_resume(struct radeon_device *rdev)
649{
650
651 rs400_gart_disable(rdev);
652
653 rv515_clock_startup(rdev);
654
655 if (radeon_asic_reset(rdev)) {
656 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
657 RREG32(R_000E40_RBBM_STATUS),
658 RREG32(R_0007C0_CP_STAT));
659 }
660
661 atom_asic_init(rdev->mode_info.atom_context);
662
663 rv515_clock_startup(rdev);
664
665 radeon_surface_init(rdev);
666 return rs690_startup(rdev);
667}
668
669int rs690_suspend(struct radeon_device *rdev)
670{
671 r600_audio_fini(rdev);
672 r100_cp_disable(rdev);
673 radeon_wb_disable(rdev);
674 rs600_irq_disable(rdev);
675 rs400_gart_disable(rdev);
676 return 0;
677}
678
679void rs690_fini(struct radeon_device *rdev)
680{
681 r600_audio_fini(rdev);
682 r100_cp_fini(rdev);
683 radeon_wb_fini(rdev);
684 r100_ib_fini(rdev);
685 radeon_gem_fini(rdev);
686 rs400_gart_fini(rdev);
687 radeon_irq_kms_fini(rdev);
688 radeon_fence_driver_fini(rdev);
689 radeon_bo_fini(rdev);
690 radeon_atombios_fini(rdev);
691 kfree(rdev->bios);
692 rdev->bios = NULL;
693}
694
695int rs690_init(struct radeon_device *rdev)
696{
697 int r;
698
699
700 rv515_vga_render_disable(rdev);
701
702 radeon_scratch_init(rdev);
703
704 radeon_surface_init(rdev);
705
706 r100_restore_sanity(rdev);
707
708
709 if (!radeon_get_bios(rdev)) {
710 if (ASIC_IS_AVIVO(rdev))
711 return -EINVAL;
712 }
713 if (rdev->is_atom_bios) {
714 r = radeon_atombios_init(rdev);
715 if (r)
716 return r;
717 } else {
718 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
719 return -EINVAL;
720 }
721
722 if (radeon_asic_reset(rdev)) {
723 dev_warn(rdev->dev,
724 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
725 RREG32(R_000E40_RBBM_STATUS),
726 RREG32(R_0007C0_CP_STAT));
727 }
728
729 if (radeon_boot_test_post_card(rdev) == false)
730 return -EINVAL;
731
732
733 radeon_get_clock_info(rdev->ddev);
734
735 rs690_mc_init(rdev);
736 rv515_debugfs(rdev);
737
738 r = radeon_fence_driver_init(rdev);
739 if (r)
740 return r;
741 r = radeon_irq_kms_init(rdev);
742 if (r)
743 return r;
744
745 r = radeon_bo_init(rdev);
746 if (r)
747 return r;
748 r = rs400_gart_init(rdev);
749 if (r)
750 return r;
751 rs600_set_safe_registers(rdev);
752 rdev->accel_working = true;
753 r = rs690_startup(rdev);
754 if (r) {
755
756 dev_err(rdev->dev, "Disabling GPU acceleration\n");
757 r100_cp_fini(rdev);
758 radeon_wb_fini(rdev);
759 r100_ib_fini(rdev);
760 rs400_gart_fini(rdev);
761 radeon_irq_kms_fini(rdev);
762 rdev->accel_working = false;
763 }
764 return 0;
765}
766