/*
 * hfcmulti.c  low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
 *
 * Author       Andreas Eversberg (jolly@eversberg.eu)
 * ported to mqueue mechanism:
 *              Peter Sprenger (sprengermoving-bytes.de)
 *
 * inspired by existing hfc-pci driver:
 * Copyright 1999  by Werner Cornelius (werner@isdn-development.de)
 * Copyright 2008  by Karsten Keil (kkeil@suse.de)
 * Copyright 2008  by Andreas Eversberg (jolly@eversberg.eu)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 * Thanks to Cologne Chip AG for this great controller!
 */

/*
 * module parameters:
 * type:
 *      By default (0), the card is automatically detected.
 *      Or use the following combinations:
 *      Bit 0-7   = 0x00001 = HFC-E1 (1 port)
 * or   Bit 0-7   = 0x00004 = HFC-4S (4 ports)
 * or   Bit 0-7   = 0x00008 = HFC-8S (8 ports)
 *      Bit 8     = 0x00100 = uLaw (instead of aLaw)
 *      Bit 9     = 0x00200 = Disable DTMF detect on all B-channels via hardware
 *      Bit 10    = spare
 *      Bit 11    = 0x00800 = Force PCM bus into slave mode. (otherwhise auto)
 * or   Bit 12    = 0x01000 = Force PCM bus into master mode. (otherwhise auto)
 *      Bit 13    = spare
 *      Bit 14    = 0x04000 = Use external ram (128K)
 *      Bit 15    = 0x08000 = Use external ram (512K)
 *      Bit 16    = 0x10000 = Use 64 timeslots instead of 32
 * or   Bit 17    = 0x20000 = Use 128 timeslots instead of anything else
 *      Bit 18    = spare
 *      Bit 19    = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog)
 * (all other bits are reserved and shall be 0)
 *      example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM
 *               bus (PCM master)
 *
 * port: (optional or required for all ports on all installed cards)
 *      HFC-4S/HFC-8S only bits:
 *      Bit 0     = 0x001 = Use master clock for this S/T interface
 *                          (ony once per chip).
 *      Bit 1     = 0x002 = transmitter line setup (non capacitive mode)
 *                          Don't use this unless you know what you are doing!
 *      Bit 2     = 0x004 = Disable E-channel. (No E-channel processing)
 *      example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock
 *               received from port 1
 *
 *      HFC-E1 only bits:
 *      Bit 0     = 0x0001 = interface: 0=copper, 1=optical
 *      Bit 1     = 0x0002 = reserved (later for 32 B-channels transparent mode)
 *      Bit 2     = 0x0004 = Report LOS
 *      Bit 3     = 0x0008 = Report AIS
 *      Bit 4     = 0x0010 = Report SLIP
 *      Bit 5     = 0x0020 = Report RDI
 *      Bit 8     = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame
 *                           mode instead.
 *      Bit 9     = 0x0200 = Force get clock from interface, even in NT mode.
 * or   Bit 10    = 0x0400 = Force put clock to interface, even in TE mode.
 *      Bit 11    = 0x0800 = Use direct RX clock for PCM sync rather than PLL.
 *                           (E1 only)
 *      Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0
 *                           for default.
 * (all other bits are reserved and shall be 0)
 *
 * debug:
 *      NOTE: only one debug value must be given for all cards
 *      enable debugging (see hfc_multi.h for debug options)
 *
 * poll:
 *      NOTE: only one poll value must be given for all cards
 *      Give the number of samples for each fifo process.
 *      By default 128 is used. Decrease to reduce delay, increase to
 *      reduce cpu load. If unsure, don't mess with it!
 *      Valid is 8, 16, 32, 64, 128, 256.
 *
 * pcm:
 *      NOTE: only one pcm value must be given for every card.
 *      The PCM bus id tells the mISDNdsp module about the connected PCM bus.
 *      By default (0), the PCM bus id is 100 for the card that is PCM master.
 *      If multiple cards are PCM master (because they are not interconnected),
 *      each card with PCM master will have increasing PCM id.
 *      All PCM busses with the same ID are expected to be connected and have
 *      common time slots slots.
 *      Only one chip of the PCM bus must be master, the others slave.
 *      -1 means no support of PCM bus not even.
 *      Omit this value, if all cards are interconnected or none is connected.
 *      If unsure, don't give this parameter.
 *
 * dslot:
 *      NOTE: only one dslot value must be given for every card.
 *      Also this value must be given for non-E1 cards. If omitted, the E1
 *      card has D-channel on time slot 16, which is default.
 *      If 1..15 or 17..31, an alternate time slot is used for D-channel.
 *      In this case, the application must be able to handle this.
 *      If -1 is given, the D-channel is disabled and all 31 slots can be used
 *      for B-channel. (only for specific applications)
 *      If you don't know how to use it, you don't need it!
 *
 * iomode:
 *      NOTE: only one mode value must be given for every card.
 *      -> See hfc_multi.h for HFC_IO_MODE_* values
 *      By default, the IO mode is pci memory IO (MEMIO).
 *      Some cards require specific IO mode, so it cannot be changed.
 *      It may be usefull to set IO mode to register io (REGIO) to solve
 *      PCI bridge problems.
 *      If unsure, don't give this parameter.
 *
 * clockdelay_nt:
 *      NOTE: only one clockdelay_nt value must be given once for all cards.
 *      Give the value of the clock control register (A_ST_CLK_DLY)
 *      of the S/T interfaces in NT mode.
 *      This register is needed for the TBR3 certification, so don't change it.
 *
 * clockdelay_te:
 *      NOTE: only one clockdelay_te value must be given once
 *      Give the value of the clock control register (A_ST_CLK_DLY)
 *      of the S/T interfaces in TE mode.
 *      This register is needed for the TBR3 certification, so don't change it.
 *
 * clock:
 *      NOTE: only one clock value must be given once
 *      Selects interface with clock source for mISDN and applications.
 *      Set to card number starting with 1. Set to -1 to disable.
 *      By default, the first card is used as clock source.
 *
 * hwid:
 *      NOTE: only one hwid value must be given once
 *      Enable special embedded devices with XHFC controllers.
 */

/*
 * debug register access (never use this, it will flood your system log)
 * #define HFC_REGISTER_DEBUG
 */

#define HFC_MULTI_VERSION       "2.03"

#include <linux/module.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/mISDNhw.h>
#include <linux/mISDNdsp.h>

/*
#define IRQCOUNT_DEBUG
#define IRQ_DEBUG
*/

#include "hfc_multi.h"
#ifdef ECHOPREP
#include "gaintab.h"
#endif

#define MAX_CARDS       8
#define MAX_PORTS       (8 * MAX_CARDS)

static LIST_HEAD(HFClist);
static spinlock_t HFClock; /* global hfc list lock */

static void ph_state_change(struct dchannel *);

static struct hfc_multi *syncmaster;
static int plxsd_master; /* if we have a master card (yet) */
static spinlock_t plx_lock; /* may not acquire other lock inside */

#define TYP_E1          1
#define TYP_4S          4
#define TYP_8S          8

static int poll_timer = 6;      /* default = 128 samples = 16ms */
/* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */
static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30  };
#define CLKDEL_TE       0x0f    /* CLKDEL in TE mode */
#define CLKDEL_NT       0x6c    /* CLKDEL in NT mode
                                   (0x60 MUST be included!) */

#define DIP_4S  0x1             /* DIP Switches for Beronet 1S/2S/4S cards */
#define DIP_8S  0x2             /* DIP Switches for Beronet 8S+ cards */
#define DIP_E1  0x3             /* DIP Switches for Beronet E1 cards */

/*
 * module stuff
 */

static uint     type[MAX_CARDS];
static int      pcm[MAX_CARDS];
static int      dslot[MAX_CARDS];
static uint     iomode[MAX_CARDS];
static uint     port[MAX_PORTS];
static uint     debug;
static uint     poll;
static int      clock;
static uint     timer;
static uint     clockdelay_te = CLKDEL_TE;
static uint     clockdelay_nt = CLKDEL_NT;
#define HWID_NONE       0
#define HWID_MINIP4     1
#define HWID_MINIP8     2
#define HWID_MINIP16    3
static uint     hwid = HWID_NONE;

static int      HFC_cnt, Port_cnt, PCM_cnt = 99;

MODULE_AUTHOR("Andreas Eversberg");
MODULE_LICENSE("GPL");
MODULE_VERSION(HFC_MULTI_VERSION);
module_param(debug, uint, S_IRUGO | S_IWUSR);
module_param(poll, uint, S_IRUGO | S_IWUSR);
module_param(clock, int, S_IRUGO | S_IWUSR);
module_param(timer, uint, S_IRUGO | S_IWUSR);
module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR);
module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR);
module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR);
module_param_array(pcm, int, NULL, S_IRUGO | S_IWUSR);
module_param_array(dslot, int, NULL, S_IRUGO | S_IWUSR);
module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR);
module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR);
module_param(hwid, uint, S_IRUGO | S_IWUSR); /* The hardware ID */

#ifdef HFC_REGISTER_DEBUG
#define HFC_outb(hc, reg, val) \
        (hc->HFC_outb(hc, reg, val, __func__, __LINE__))
#define HFC_outb_nodebug(hc, reg, val) \
        (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__))
#define HFC_inb(hc, reg) \
        (hc->HFC_inb(hc, reg, __func__, __LINE__))
#define HFC_inb_nodebug(hc, reg) \
        (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__))
#define HFC_inw(hc, reg) \
        (hc->HFC_inw(hc, reg, __func__, __LINE__))
#define HFC_inw_nodebug(hc, reg) \
        (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__))
#define HFC_wait(hc) \
        (hc->HFC_wait(hc, __func__, __LINE__))
#define HFC_wait_nodebug(hc) \
        (hc->HFC_wait_nodebug(hc, __func__, __LINE__))
#else
#define HFC_outb(hc, reg, val)          (hc->HFC_outb(hc, reg, val))
#define HFC_outb_nodebug(hc, reg, val)  (hc->HFC_outb_nodebug(hc, reg, val))
#define HFC_inb(hc, reg)                (hc->HFC_inb(hc, reg))
#define HFC_inb_nodebug(hc, reg)        (hc->HFC_inb_nodebug(hc, reg))
#define HFC_inw(hc, reg)                (hc->HFC_inw(hc, reg))
#define HFC_inw_nodebug(hc, reg)        (hc->HFC_inw_nodebug(hc, reg))
#define HFC_wait(hc)                    (hc->HFC_wait(hc))
#define HFC_wait_nodebug(hc)            (hc->HFC_wait_nodebug(hc))
#endif

#ifdef CONFIG_MISDN_HFCMULTI_8xx
#include "hfc_multi_8xx.h"
#endif

/* HFC_IO_MODE_PCIMEM */
static void
#ifdef HFC_REGISTER_DEBUG
HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val,
                const char *function, int line)
#else
HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val)
#endif
{
        writeb(val, hc->pci_membase + reg);
}
static u_char
#ifdef HFC_REGISTER_DEBUG
HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
#else
HFC_inb_pcimem(struct hfc_multi *hc, u_char reg)
#endif
{
        return readb(hc->pci_membase + reg);
}
static u_short
#ifdef HFC_REGISTER_DEBUG
HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
#else
HFC_inw_pcimem(struct hfc_multi *hc, u_char reg)
#endif
{
        return readw(hc->pci_membase + reg);
}
static void
#ifdef HFC_REGISTER_DEBUG
HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line)
#else
HFC_wait_pcimem(struct hfc_multi *hc)
#endif
{
        while (readb(hc->pci_membase + R_STATUS) & V_BUSY)
                cpu_relax();
}

/* HFC_IO_MODE_REGIO */
static void
#ifdef HFC_REGISTER_DEBUG
HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val,
        const char *function, int line)
#else
HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val)
#endif
{
        outb(reg, hc->pci_iobase + 4);
        outb(val, hc->pci_iobase);
}
static u_char
#ifdef HFC_REGISTER_DEBUG
HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
#else
HFC_inb_regio(struct hfc_multi *hc, u_char reg)
#endif
{
        outb(reg, hc->pci_iobase + 4);
        return inb(hc->pci_iobase);
}
static u_short
#ifdef HFC_REGISTER_DEBUG
HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
#else
HFC_inw_regio(struct hfc_multi *hc, u_char reg)
#endif
{
        outb(reg, hc->pci_iobase + 4);
        return inw(hc->pci_iobase);
}
static void
#ifdef HFC_REGISTER_DEBUG
HFC_wait_regio(struct hfc_multi *hc, const char *function, int line)
#else
HFC_wait_regio(struct hfc_multi *hc)
#endif
{
        outb(R_STATUS, hc->pci_iobase + 4);
        while (inb(hc->pci_iobase) & V_BUSY)
                cpu_relax();
}

#ifdef HFC_REGISTER_DEBUG
static void
HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val,
                const char *function, int line)
{
        char regname[256] = "", bits[9] = "xxxxxxxx";
        int i;

        i = -1;
        while (hfc_register_names[++i].name) {
                if (hfc_register_names[i].reg == reg)
                        strcat(regname, hfc_register_names[i].name);
        }
        if (regname[0] == '\0')
                strcpy(regname, "register");

        bits[7] = '0' + (!!(val & 1));
        bits[6] = '0' + (!!(val & 2));
        bits[5] = '0' + (!!(val & 4));
        bits[4] = '0' + (!!(val & 8));
        bits[3] = '0' + (!!(val & 16));
        bits[2] = '0' + (!!(val & 32));
        bits[1] = '0' + (!!(val & 64));
        bits[0] = '0' + (!!(val & 128));
        printk(KERN_DEBUG
            "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n",
            hc->id, reg, regname, val, bits, function, line);
        HFC_outb_nodebug(hc, reg, val);
}
static u_char
HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
{
        char regname[256] = "", bits[9] = "xxxxxxxx";
        u_char val = HFC_inb_nodebug(hc, reg);
        int i;

        i = 0;
        while (hfc_register_names[i++].name)
                ;
        while (hfc_register_names[++i].name) {
                if (hfc_register_names[i].reg == reg)
                        strcat(regname, hfc_register_names[i].name);
        }
        if (regname[0] == '\0')
                strcpy(regname, "register");

        bits[7] = '0' + (!!(val & 1));
        bits[6] = '0' + (!!(val & 2));
        bits[5] = '0' + (!!(val & 4));
        bits[4] = '0' + (!!(val & 8));
        bits[3] = '0' + (!!(val & 16));
        bits[2] = '0' + (!!(val & 32));
        bits[1] = '0' + (!!(val & 64));
        bits[0] = '0' + (!!(val & 128));
        printk(KERN_DEBUG
            "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n",
            hc->id, reg, regname, val, bits, function, line);
        return val;
}
static u_short
HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
{
        char regname[256] = "";
        u_short val = HFC_inw_nodebug(hc, reg);
        int i;

        i = 0;
        while (hfc_register_names[i++].name)
                ;
        while (hfc_register_names[++i].name) {
                if (hfc_register_names[i].reg == reg)
                        strcat(regname, hfc_register_names[i].name);
        }
        if (regname[0] == '\0')
                strcpy(regname, "register");

        printk(KERN_DEBUG
            "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n",
            hc->id, reg, regname, val, function, line);
        return val;
}
static void
HFC_wait_debug(struct hfc_multi *hc, const char *function, int line)
{
        printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n",
            hc->id, function, line);
        HFC_wait_nodebug(hc);
}
#endif

/* write fifo data (REGIO) */
static void
write_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
{
        outb(A_FIFO_DATA0, (hc->pci_iobase)+4);
        while (len>>2) {
                outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase);
                data += 4;
                len -= 4;
        }
        while (len>>1) {
                outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase);
                data += 2;
                len -= 2;
        }
        while (len) {
                outb(*data, hc->pci_iobase);
                data++;
                len--;
        }
}
/* write fifo data (PCIMEM) */
static void
write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
{
        while (len>>2) {
                writel(cpu_to_le32(*(u32 *)data),
                        hc->pci_membase + A_FIFO_DATA0);
                data += 4;
                len -= 4;
        }
        while (len>>1) {
                writew(cpu_to_le16(*(u16 *)data),
                        hc->pci_membase + A_FIFO_DATA0);
                data += 2;
                len -= 2;
        }
        while (len) {
                writeb(*data, hc->pci_membase + A_FIFO_DATA0);
                data++;
                len--;
        }
}

/* read fifo data (REGIO) */
static void
read_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
{
        outb(A_FIFO_DATA0, (hc->pci_iobase)+4);
        while (len>>2) {
                *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase));
                data += 4;
                len -= 4;
        }
        while (len>>1) {
                *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase));
                data += 2;
                len -= 2;
        }
        while (len) {
                *data = inb(hc->pci_iobase);
                data++;
                len--;
        }
}

/* read fifo data (PCIMEM) */
static void
read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
{
        while (len>>2) {
                *(u32 *)data =
                        le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0));
                data += 4;
                len -= 4;
        }
        while (len>>1) {
                *(u16 *)data =
                        le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0));
                data += 2;
                len -= 2;
        }
        while (len) {
                *data = readb(hc->pci_membase + A_FIFO_DATA0);
                data++;
                len--;
        }
}

static void
enable_hwirq(struct hfc_multi *hc)
{
        hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN;
        HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
}

static void
disable_hwirq(struct hfc_multi *hc)
{
        hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN);
        HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
}

#define NUM_EC 2
#define MAX_TDM_CHAN 32


inline void
enablepcibridge(struct hfc_multi *c)
{
        HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */
}

inline void
disablepcibridge(struct hfc_multi *c)
{
        HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */
}

inline unsigned char
readpcibridge(struct hfc_multi *hc, unsigned char address)
{
        unsigned short cipv;
        unsigned char data;

        if (!hc->pci_iobase)
                return 0;

        /* slow down a PCI read access by 1 PCI clock cycle */
        HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/

        if (address == 0)
                cipv = 0x4000;
        else
                cipv = 0x5800;

        /* select local bridge port address by writing to CIP port */
        /* data = HFC_inb(c, cipv); * was _io before */
        outw(cipv, hc->pci_iobase + 4);
        data = inb(hc->pci_iobase);

        /* restore R_CTRL for normal PCI read cycle speed */
        HFC_outb(hc, R_CTRL, 0x0); /* was _io before */

        return data;
}

inline void
writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data)
{
        unsigned short cipv;
        unsigned int datav;

        if (!hc->pci_iobase)
                return;

        if (address == 0)
                cipv = 0x4000;
        else
                cipv = 0x5800;

        /* select local bridge port address by writing to CIP port */
        outw(cipv, hc->pci_iobase + 4);
        /* define a 32 bit dword with 4 identical bytes for write sequence */
        datav = data | ((__u32) data << 8) | ((__u32) data << 16) |
            ((__u32) data << 24);

        /*
         * write this 32 bit dword to the bridge data port
         * this will initiate a write sequence of up to 4 writes to the same
         * address on the local bus interface the number of write accesses
         * is undefined but >=1 and depends on the next PCI transaction
         * during write sequence on the local bus
         */
        outl(datav, hc->pci_iobase);
}

inline void
cpld_set_reg(struct hfc_multi *hc, unsigned char reg)
{
        /* Do data pin read low byte */
        HFC_outb(hc, R_GPIO_OUT1, reg);
}

inline void
cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val)
{
        cpld_set_reg(hc, reg);

        enablepcibridge(hc);
        writepcibridge(hc, 1, val);
        disablepcibridge(hc);

        return;
}

inline unsigned char
cpld_read_reg(struct hfc_multi *hc, unsigned char reg)
{
        unsigned char bytein;

        cpld_set_reg(hc, reg);

        /* Do data pin read low byte */
        HFC_outb(hc, R_GPIO_OUT1, reg);

        enablepcibridge(hc);
        bytein = readpcibridge(hc, 1);
        disablepcibridge(hc);

        return bytein;
}

inline void
vpm_write_address(struct hfc_multi *hc, unsigned short addr)
{
        cpld_write_reg(hc, 0, 0xff & addr);
        cpld_write_reg(hc, 1, 0x01 & (addr >> 8));
}

inline unsigned short
vpm_read_address(struct hfc_multi *c)
{
        unsigned short addr;
        unsigned short highbit;

        addr = cpld_read_reg(c, 0);
        highbit = cpld_read_reg(c, 1);

        addr = addr | (highbit << 8);

        return addr & 0x1ff;
}

inline unsigned char
vpm_in(struct hfc_multi *c, int which, unsigned short addr)
{
        unsigned char res;

        vpm_write_address(c, addr);

        if (!which)
                cpld_set_reg(c, 2);
        else
                cpld_set_reg(c, 3);

        enablepcibridge(c);
        res = readpcibridge(c, 1);
        disablepcibridge(c);

        cpld_set_reg(c, 0);

        return res;
}

inline void
vpm_out(struct hfc_multi *c, int which, unsigned short addr,
    unsigned char data)
{
        vpm_write_address(c, addr);

        enablepcibridge(c);

        if (!which)
                cpld_set_reg(c, 2);
        else
                cpld_set_reg(c, 3);

        writepcibridge(c, 1, data);

        cpld_set_reg(c, 0);

        disablepcibridge(c);

        {
        unsigned char regin;
        regin = vpm_in(c, which, addr);
        if (regin != data)
                printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back "
                        "0x%x\n", data, addr, regin);
        }

}


static void
vpm_init(struct hfc_multi *wc)
{
        unsigned char reg;
        unsigned int mask;
        unsigned int i, x, y;
        unsigned int ver;

        for (x = 0; x < NUM_EC; x++) {
                /* Setup GPIO's */
                if (!x) {
                        ver = vpm_in(wc, x, 0x1a0);
                        printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver);
                }

                for (y = 0; y < 4; y++) {
                        vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */
                        vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */
                        vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */
                }

                /* Setup TDM path - sets fsync and tdm_clk as inputs */
                reg = vpm_in(wc, x, 0x1a3); /* misc_con */
                vpm_out(wc, x, 0x1a3, reg & ~2);

                /* Setup Echo length (256 taps) */
                vpm_out(wc, x, 0x022, 1);
                vpm_out(wc, x, 0x023, 0xff);

                /* Setup timeslots */
                vpm_out(wc, x, 0x02f, 0x00);
                mask = 0x02020202 << (x * 4);

                /* Setup the tdm channel masks for all chips */
                for (i = 0; i < 4; i++)
                        vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff);

                /* Setup convergence rate */
                printk(KERN_DEBUG "VPM: A-law mode\n");
                reg = 0x00 | 0x10 | 0x01;
                vpm_out(wc, x, 0x20, reg);
                printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg);
                /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */

                vpm_out(wc, x, 0x24, 0x02);
                reg = vpm_in(wc, x, 0x24);
                printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg);

                /* Initialize echo cans */
                for (i = 0; i < MAX_TDM_CHAN; i++) {
                        if (mask & (0x00000001 << i))
                                vpm_out(wc, x, i, 0x00);
                }

                /*
                 * ARM arch at least disallows a udelay of
                 * more than 2ms... it gives a fake "__bad_udelay"
                 * reference at link-time.
                 * long delays in kernel code are pretty sucky anyway
                 * for now work around it using 5 x 2ms instead of 1 x 10ms
                 */

                udelay(2000);
                udelay(2000);
                udelay(2000);
                udelay(2000);
                udelay(2000);

                /* Put in bypass mode */
                for (i = 0; i < MAX_TDM_CHAN; i++) {
                        if (mask & (0x00000001 << i))
                                vpm_out(wc, x, i, 0x01);
                }

                /* Enable bypass */
                for (i = 0; i < MAX_TDM_CHAN; i++) {
                        if (mask & (0x00000001 << i))
                                vpm_out(wc, x, 0x78 + i, 0x01);
                }

        }
}

#ifdef UNUSED
static void
vpm_check(struct hfc_multi *hctmp)
{
        unsigned char gpi2;

        gpi2 = HFC_inb(hctmp, R_GPI_IN2);

        if ((gpi2 & 0x3) != 0x3)
                printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2);
}
#endif /* UNUSED */


/*
 * Interface to enable/disable the HW Echocan
 *
 * these functions are called within a spin_lock_irqsave on
 * the channel instance lock, so we are not disturbed by irqs
 *
 * we can later easily change the interface to make  other
 * things configurable, for now we configure the taps
 *
 */

static void
vpm_echocan_on(struct hfc_multi *hc, int ch, int taps)
{
        unsigned int timeslot;
        unsigned int unit;
        struct bchannel *bch = hc->chan[ch].bch;
#ifdef TXADJ
        int txadj = -4;
        struct sk_buff *skb;
#endif
        if (hc->chan[ch].protocol != ISDN_P_B_RAW)
                return;

        if (!bch)
                return;

#ifdef TXADJ
        skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
                sizeof(int), &txadj, GFP_ATOMIC);
        if (skb)
                recv_Bchannel_skb(bch, skb);
#endif

        timeslot = ((ch/4)*8) + ((ch%4)*4) + 1;
        unit = ch % 4;

        printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n",
            taps, timeslot);

        vpm_out(hc, unit, timeslot, 0x7e);
}

static void
vpm_echocan_off(struct hfc_multi *hc, int ch)
{
        unsigned int timeslot;
        unsigned int unit;
        struct bchannel *bch = hc->chan[ch].bch;
#ifdef TXADJ
        int txadj = 0;
        struct sk_buff *skb;
#endif

        if (hc->chan[ch].protocol != ISDN_P_B_RAW)
                return;

        if (!bch)
                return;

#ifdef TXADJ
        skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
                sizeof(int), &txadj, GFP_ATOMIC);
        if (skb)
                recv_Bchannel_skb(bch, skb);
#endif

        timeslot = ((ch/4)*8) + ((ch%4)*4) + 1;
        unit = ch % 4;

        printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n",
            timeslot);
        /* FILLME */
        vpm_out(hc, unit, timeslot, 0x01);
}


/*
 * Speech Design resync feature
 * NOTE: This is called sometimes outside interrupt handler.
 * We must lock irqsave, so no other interrupt (other card) will occurr!
 * Also multiple interrupts may nest, so must lock each access (lists, card)!
 */
static inline void
hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
{
        struct hfc_multi *hc, *next, *pcmmaster = NULL;
        void __iomem *plx_acc_32;
        u_int pv;
        u_long flags;

        spin_lock_irqsave(&HFClock, flags);
        spin_lock(&plx_lock); /* must be locked inside other locks */

        if (debug & DEBUG_HFCMULTI_PLXSD)
                printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n",
                        __func__, syncmaster);

        /* select new master */
        if (newmaster) {
                if (debug & DEBUG_HFCMULTI_PLXSD)
                        printk(KERN_DEBUG "using provided controller\n");
        } else {
                list_for_each_entry_safe(hc, next, &HFClist, list) {
                        if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
                                if (hc->syncronized) {
                                        newmaster = hc;
                                        break;
                                }
                        }
                }
        }

        /* Disable sync of all cards */
        list_for_each_entry_safe(hc, next, &HFClist, list) {
                if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
                        plx_acc_32 = hc->plx_membase + PLX_GPIOC;
                        pv = readl(plx_acc_32);
                        pv &= ~PLX_SYNC_O_EN;
                        writel(pv, plx_acc_32);
                        if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
                                pcmmaster = hc;
                                if (hc->ctype == HFC_TYPE_E1) {
                                        if (debug & DEBUG_HFCMULTI_PLXSD)
                                                printk(KERN_DEBUG
                                                        "Schedule SYNC_I\n");
                                        hc->e1_resync |= 1; /* get SYNC_I */
                                }
                        }
                }
        }

        if (newmaster) {
                hc = newmaster;
                if (debug & DEBUG_HFCMULTI_PLXSD)
                        printk(KERN_DEBUG "id=%d (0x%p) = syncronized with "
                                "interface.\n", hc->id, hc);
                /* Enable new sync master */
                plx_acc_32 = hc->plx_membase + PLX_GPIOC;
                pv = readl(plx_acc_32);
                pv |= PLX_SYNC_O_EN;
                writel(pv, plx_acc_32);
                /* switch to jatt PLL, if not disabled by RX_SYNC */
                if (hc->ctype == HFC_TYPE_E1
                                && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
                        if (debug & DEBUG_HFCMULTI_PLXSD)
                                printk(KERN_DEBUG "Schedule jatt PLL\n");
                        hc->e1_resync |= 2; /* switch to jatt */
                }
        } else {
                if (pcmmaster) {
                        hc = pcmmaster;
                        if (debug & DEBUG_HFCMULTI_PLXSD)
                                printk(KERN_DEBUG
                                        "id=%d (0x%p) = PCM master syncronized "
                                        "with QUARTZ\n", hc->id, hc);
                        if (hc->ctype == HFC_TYPE_E1) {
                                /* Use the crystal clock for the PCM
                                   master card */
                                if (debug & DEBUG_HFCMULTI_PLXSD)
                                        printk(KERN_DEBUG
                                            "Schedule QUARTZ for HFC-E1\n");
                                hc->e1_resync |= 4; /* switch quartz */
                        } else {
                                if (debug & DEBUG_HFCMULTI_PLXSD)
                                        printk(KERN_DEBUG
                                            "QUARTZ is automatically "
                                            "enabled by HFC-%dS\n", hc->ctype);
                        }
                        plx_acc_32 = hc->plx_membase + PLX_GPIOC;
                        pv = readl(plx_acc_32);
                        pv |= PLX_SYNC_O_EN;
                        writel(pv, plx_acc_32);
                } else
                        if (!rm)

                                printk(KERN_ERR "%s no pcm master, this MUST "
                                        "not happen!\n", __func__);
        }
        syncmaster = newmaster;

        spin_unlock(&plx_lock);
        spin_unlock_irqrestore(&HFClock, flags);
}

/* This must be called AND hc must be locked irqsave!!! */
inline void
plxsd_checksync(struct hfc_multi *hc, int rm)
{
        if (hc->syncronized) {
                if (syncmaster == NULL) {
                        if (debug & DEBUG_HFCMULTI_PLXSD)
                                printk(KERN_DEBUG "%s: GOT sync on card %d"
                                        " (id=%d)\n", __func__, hc->id + 1,
                                        hc->id);
                        hfcmulti_resync(hc, hc, rm);
                }
        } else {
                if (syncmaster == hc) {
                        if (debug & DEBUG_HFCMULTI_PLXSD)
                                printk(KERN_DEBUG "%s: LOST sync on card %d"
                                        " (id=%d)\n", __func__, hc->id + 1,
                                        hc->id);
                        hfcmulti_resync(hc, NULL, rm);
                }
        }
}


/*
 * free hardware resources used by driver
 */
static void
release_io_hfcmulti(struct hfc_multi *hc)
{
        void __iomem *plx_acc_32;
        u_int   pv;
        u_long  plx_flags;

        if (debug & DEBUG_HFCMULTI_INIT)
                printk(KERN_DEBUG "%s: entered\n", __func__);

        /* soft reset also masks all interrupts */
        hc->hw.r_cirm |= V_SRES;
        HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
        udelay(1000);
        hc->hw.r_cirm &= ~V_SRES;
        HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
        udelay(1000); /* instead of 'wait' that may cause locking */

        /* release Speech Design card, if PLX was initialized */
        if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) {
                if (debug & DEBUG_HFCMULTI_PLXSD)
                        printk(KERN_DEBUG "%s: release PLXSD card %d\n",
                            __func__, hc->id + 1);
                spin_lock_irqsave(&plx_lock, plx_flags);
                plx_acc_32 = hc->plx_membase + PLX_GPIOC;
                writel(PLX_GPIOC_INIT, plx_acc_32);
                pv = readl(plx_acc_32);
                /* Termination off */
                pv &= ~PLX_TERM_ON;
                /* Disconnect the PCM */
                pv |= PLX_SLAVE_EN_N;
                pv &= ~PLX_MASTER_EN;
                pv &= ~PLX_SYNC_O_EN;
                /* Put the DSP in Reset */
                pv &= ~PLX_DSP_RES_N;
                writel(pv, plx_acc_32);
                if (debug & DEBUG_HFCMULTI_INIT)
                        printk(KERN_DEBUG "%s: PCM off: PLX_GPIO=%x\n",
                                __func__, pv);
                spin_unlock_irqrestore(&plx_lock, plx_flags);
        }

        /* disable memory mapped ports / io ports */
        test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */
        if (hc->pci_dev)
                pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
        if (hc->pci_membase)
                iounmap(hc->pci_membase);
        if (hc->plx_membase)
                iounmap(hc->plx_membase);
        if (hc->pci_iobase)
                release_region(hc->pci_iobase, 8);
        if (hc->xhfc_membase)
                iounmap((void *)hc->xhfc_membase);

        if (hc->pci_dev) {
                pci_disable_device(hc->pci_dev);
                pci_set_drvdata(hc->pci_dev, NULL);
        }
        if (debug & DEBUG_HFCMULTI_INIT)
                printk(KERN_DEBUG "%s: done\n", __func__);
}

/*
 * function called to reset the HFC chip. A complete software reset of chip
 * and fifos is done. All configuration of the chip is done.
 */

static int
init_chip(struct hfc_multi *hc)
{
        u_long                  flags, val, val2 = 0, rev;
        int                     i, err = 0;
        u_char                  r_conf_en, rval;
        void __iomem            *plx_acc_32;
        u_int                   pv;
        u_long                  plx_flags, hfc_flags;
        int                     plx_count;
        struct hfc_multi        *pos, *next, *plx_last_hc;

        spin_lock_irqsave(&hc->lock, flags);
        /* reset all registers */
        memset(&hc->hw, 0, sizeof(struct hfcm_hw));

        /* revision check */
        if (debug & DEBUG_HFCMULTI_INIT)
                printk(KERN_DEBUG "%s: entered\n", __func__);
        val = HFC_inb(hc, R_CHIP_ID);
        if ((val >> 4) != 0x8 && (val >> 4) != 0xc && (val >> 4) != 0xe &&
            (val >> 1) != 0x31) {
                printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val);
                err = -EIO;
                goto out;
        }
        rev = HFC_inb(hc, R_CHIP_RV);
        printk(KERN_INFO
            "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n",
            val, rev, (rev == 0 && (hc->ctype != HFC_TYPE_XHFC)) ?
                " (old FIFO handling)" : "");
        if (hc->ctype != HFC_TYPE_XHFC && rev == 0) {
                test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip);
                printk(KERN_WARNING
                    "HFC_multi: NOTE: Your chip is revision 0, "
                    "ask Cologne Chip for update. Newer chips "
                    "have a better FIFO handling. Old chips "
                    "still work but may have slightly lower "
                    "HDLC transmit performance.\n");
        }
        if (rev > 1) {
                printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't "
                    "consider chip revision = %ld. The chip / "
                    "bridge may not work.\n", rev);
        }

        /* set s-ram size */
        hc->Flen = 0x10;
        hc->Zmin = 0x80;
        hc->Zlen = 384;
        hc->DTMFbase = 0x1000;
        if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) {
                if (debug & DEBUG_HFCMULTI_INIT)
                        printk(KERN_DEBUG "%s: changing to 128K extenal RAM\n",
                            __func__);
                hc->hw.r_ctrl |= V_EXT_RAM;
                hc->hw.r_ram_sz = 1;
                hc->Flen = 0x20;
                hc->Zmin = 0xc0;
                hc->Zlen = 1856;
                hc->DTMFbase = 0x2000;
        }
        if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) {
                if (debug & DEBUG_HFCMULTI_INIT)
                        printk(KERN_DEBUG "%s: changing to 512K extenal RAM\n",
                            __func__);
                hc->hw.r_ctrl |= V_EXT_RAM;
                hc->hw.r_ram_sz = 2;
                hc->Flen = 0x20;
                hc->Zmin = 0xc0;
                hc->Zlen = 8000;
                hc->DTMFbase = 0x2000;
        }
        if (hc->ctype == HFC_TYPE_XHFC) {
                hc->Flen = 0x8;
                hc->Zmin = 0x0;
                hc->Zlen = 64;
                hc->DTMFbase = 0x0;
        }
        hc->max_trans = poll << 1;
        if (hc->max_trans > hc->Zlen)
                hc->max_trans = hc->Zlen;

        /* Speech Design PLX bridge */
        if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
                if (debug & DEBUG_HFCMULTI_PLXSD)
                        printk(KERN_DEBUG "%s: initializing PLXSD card %d\n",
                            __func__, hc->id + 1);
                spin_lock_irqsave(&plx_lock, plx_flags);
                plx_acc_32 = hc->plx_membase + PLX_GPIOC;
                writel(PLX_GPIOC_INIT, plx_acc_32);
                pv = readl(plx_acc_32);
                /* The first and the last cards are terminating the PCM bus */
                pv |= PLX_TERM_ON; /* hc is currently the last */
                /* Disconnect the PCM */
                pv |= PLX_SLAVE_EN_N;
                pv &= ~PLX_MASTER_EN;
                pv &= ~PLX_SYNC_O_EN;
                /* Put the DSP in Reset */
                pv &= ~PLX_DSP_RES_N;
                writel(pv, plx_acc_32);
                spin_unlock_irqrestore(&plx_lock, plx_flags);
                if (debug & DEBUG_HFCMULTI_INIT)
                        printk(KERN_DEBUG "%s: slave/term: PLX_GPIO=%x\n",
                                __func__, pv);
                /*
                 * If we are the 3rd PLXSD card or higher, we must turn
                 * termination of last PLXSD card off.
                 */
                spin_lock_irqsave(&HFClock, hfc_flags);
                plx_count = 0;
                plx_last_hc = NULL;
                list_for_each_entry_safe(pos, next, &HFClist, list) {
                        if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) {
                                plx_count++;
                                if (pos != hc)
                                        plx_last_hc = pos;
                        }
                }
                if (plx_count >= 3) {
                        if (debug & DEBUG_HFCMULTI_PLXSD)
                                printk(KERN_DEBUG "%s: card %d is between, so "
                                        "we disable termination\n",
                                    __func__, plx_last_hc->id + 1);
                        spin_lock_irqsave(&plx_lock, plx_flags);
                        plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC;
                        pv = readl(plx_acc_32);
                        pv &= ~PLX_TERM_ON;
                        writel(pv, plx_acc_32);
                        spin_unlock_irqrestore(&plx_lock, plx_flags);
                        if (debug & DEBUG_HFCMULTI_INIT)
                                printk(KERN_DEBUG
                                    "%s: term off: PLX_GPIO=%x\n",
                                    __func__, pv);
                }
                spin_unlock_irqrestore(&HFClock, hfc_flags);
                hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
        }

        if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
                hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */

        /* we only want the real Z2 read-pointer for revision > 0 */
        if (!test_bit(HFC_CHIP_REVISION0, &hc->chip))
                hc->hw.r_ram_sz |= V_FZ_MD;

        /* select pcm mode */
        if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
                if (debug & DEBUG_HFCMULTI_INIT)
                        printk(KERN_DEBUG "%s: setting PCM into slave mode\n",
                            __func__);
        } else
        if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) {
                if (debug & DEBUG_HFCMULTI_INIT)
                        printk(KERN_DEBUG "%s: setting PCM into master mode\n",
                            __func__);
                hc->hw.r_pcm_md0 |= V_PCM_MD;
        } else {
                if (debug & DEBUG_HFCMULTI_INIT)
                        printk(KERN_DEBUG "%s: performing PCM auto detect\n",
                            __func__);
        }

        /* soft reset */
        HFC_outb(hc, R_CTRL, hc->hw.r_ctrl);
        if (hc->ctype == HFC_TYPE_XHFC)
                HFC_outb(hc, 0x0C /* R_FIFO_THRES */,
                                0x11 /* 16 Bytes TX/RX */);
        else
                HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
        HFC_outb(hc, R_FIFO_MD, 0);
        if (hc->ctype == HFC_TYPE_XHFC)
                hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES;
        else
                hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES
                        | V_RLD_EPR;
        HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
        udelay(100);
        hc->hw.r_cirm = 0;
        HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
        udelay(100);
        if (hc->ctype != HFC_TYPE_XHFC)
                HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);

        /* Speech Design PLX bridge pcm and sync mode */
        if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
                spin_lock_irqsave(&plx_lock, plx_flags);
                plx_acc_32 = hc->plx_membase + PLX_GPIOC;
                pv = readl(plx_acc_32);
                /* Connect PCM */
                if (hc->hw.r_pcm_md0 & V_PCM_MD) {
                        pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
                        pv |= PLX_SYNC_O_EN;
                        if (debug & DEBUG_HFCMULTI_INIT)
                                printk(KERN_DEBUG "%s: master: PLX_GPIO=%x\n",
                                        __func__, pv);
                } else {
                        pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N);
                        pv &= ~PLX_SYNC_O_EN;
                        if (debug & DEBUG_HFCMULTI_INIT)
                                printk(KERN_DEBUG "%s: slave: PLX_GPIO=%x\n",
                                        __func__, pv);
                }
                writel(pv, plx_acc_32);
                spin_unlock_irqrestore(&plx_lock, plx_flags);
        }

        /* PCM setup */
        HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90);
        if (hc->slots == 32)
                HFC_outb(hc, R_PCM_MD1, 0x00);
        if (hc->slots == 64)
                HFC_outb(hc, R_PCM_MD1, 0x10);
        if (hc->slots == 128)
                HFC_outb(hc, R_PCM_MD1, 0x20);
        HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
        if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
                HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */
        else if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
                HFC_outb(hc, R_PCM_MD2, 0x10); /* V_C2O_EN */
        else
                HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */
        HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
        for (i = 0; i < 256; i++) {
                HFC_outb_nodebug(hc, R_SLOT, i);
                HFC_outb_nodebug(hc, A_SL_CFG, 0);
                if (hc->ctype != HFC_TYPE_XHFC)
                        HFC_outb_nodebug(hc, A_CONF, 0);
                hc->slot_owner[i] = -1;
        }

        /* set clock speed */
        if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) {
                if (debug & DEBUG_HFCMULTI_INIT)
                        printk(KERN_DEBUG
                            "%s: setting double clock\n", __func__);
                HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
        }

        if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
                HFC_outb(hc, 0x02 /* R_CLK_CFG */, 0x40 /* V_CLKO_OFF */);

        /* B410P GPIO */
        if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
                printk(KERN_NOTICE "Setting GPIOs\n");
                HFC_outb(hc, R_GPIO_SEL, 0x30);
                HFC_outb(hc, R_GPIO_EN1, 0x3);
                udelay(1000);
                printk(KERN_NOTICE "calling vpm_init\n");
                vpm_init(hc);
        }

        /* check if R_F0_CNT counts (8 kHz frame count) */
        val = HFC_inb(hc, R_F0_CNTL);
        val += HFC_inb(hc, R_F0_CNTH) << 8;
        if (debug & DEBUG_HFCMULTI_INIT)
                printk(KERN_DEBUG
                    "HFC_multi F0_CNT %ld after reset\n", val);
        spin_unlock_irqrestore(&hc->lock, flags);
        set_current_state(TASK_UNINTERRUPTIBLE);
        schedule_timeout((HZ/100)?:1); /* Timeout minimum 10ms */
        spin_lock_irqsave(&hc->lock, flags);
        val2 = HFC_inb(hc, R_F0_CNTL);
        val2 += HFC_inb(hc, R_F0_CNTH) << 8;
        if (debug & DEBUG_HFCMULTI_INIT)
                printk(KERN_DEBUG
                        "HFC_multi F0_CNT %ld after 10 ms (1st try)\n",
                    val2);
        if (val2 >= val+8) { /* 1 ms */
                /* it counts, so we keep the pcm mode */
                if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
                        printk(KERN_INFO "controller is PCM bus MASTER\n");
                else
                if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip))
                        printk(KERN_INFO "controller is PCM bus SLAVE\n");
                else {
                        test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
                        printk(KERN_INFO "controller is PCM bus SLAVE "
                                "(auto detected)\n");
                }
        } else {
                /* does not count */
                if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
controller_fail:
                        printk(KERN_ERR "HFC_multi ERROR, getting no 125us "
                            "pulse. Seems that controller fails.\n");
                        err = -EIO;
                        goto out;
                }
                if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
                        printk(KERN_INFO "controller is PCM bus SLAVE "
                                "(ignoring missing PCM clock)\n");
                } else {
                        /* only one pcm master */
                        if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
                                && plxsd_master) {
                                printk(KERN_ERR "HFC_multi ERROR, no clock "
                                    "on another Speech Design card found. "
                                    "Please be sure to connect PCM cable.\n");
                                err = -EIO;
                                goto out;
                        }
                        /* retry with master clock */
                        if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
                                spin_lock_irqsave(&plx_lock, plx_flags);
                                plx_acc_32 = hc->plx_membase + PLX_GPIOC;
                                pv = readl(plx_acc_32);
                                pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
                                pv |= PLX_SYNC_O_EN;
                                writel(pv, plx_acc_32);
                                spin_unlock_irqrestore(&plx_lock, plx_flags);
                                if (debug & DEBUG_HFCMULTI_INIT)
                                        printk(KERN_DEBUG "%s: master: "
                                            "PLX_GPIO=%x\n", __func__, pv);
                        }
                        hc->hw.r_pcm_md0 |= V_PCM_MD;
                        HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
                        spin_unlock_irqrestore(&hc->lock, flags);
                        set_current_state(TASK_UNINTERRUPTIBLE);
                        schedule_timeout((HZ/100)?:1); /* Timeout min. 10ms */
                        spin_lock_irqsave(&hc->lock, flags);
                        val2 = HFC_inb(hc, R_F0_CNTL);
                        val2 += HFC_inb(hc, R_F0_CNTH) << 8;
                        if (debug & DEBUG_HFCMULTI_INIT)
                                printk(KERN_DEBUG "HFC_multi F0_CNT %ld after "
                                        "10 ms (2nd try)\n", val2);
                        if (val2 >= val+8) { /* 1 ms */
                                test_and_set_bit(HFC_CHIP_PCM_MASTER,
                                        &hc->chip);
                                printk(KERN_INFO "controller is PCM bus MASTER "
                                        "(auto detected)\n");
                        } else
                                goto controller_fail;
                }
        }

        /* Release the DSP Reset */
        if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
                if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
                        plxsd_master = 1;
                spin_lock_irqsave(&plx_lock, plx_flags);
                plx_acc_32 = hc->plx_membase + PLX_GPIOC;
                pv = readl(plx_acc_32);
                pv |=  PLX_DSP_RES_N;
                writel(pv, plx_acc_32);
                spin_unlock_irqrestore(&plx_lock, plx_flags);
                if (debug & DEBUG_HFCMULTI_INIT)
                        printk(KERN_DEBUG "%s: reset off: PLX_GPIO=%x\n",
                                __func__, pv);
        }

        /* pcm id */
        if (hc->pcm)
                printk(KERN_INFO "controller has given PCM BUS ID %d\n",
                        hc->pcm);
        else {
                if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)
                 || test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
                        PCM_cnt++; /* SD has proprietary bridging */
                }
                hc->pcm = PCM_cnt;
                printk(KERN_INFO "controller has PCM BUS ID %d "
                        "(auto selected)\n", hc->pcm);
        }

        /* set up timer */
        HFC_outb(hc, R_TI_WD, poll_timer);
        hc->hw.r_irqmsk_misc |= V_TI_IRQMSK;

        /* set E1 state machine IRQ */
        if (hc->ctype == HFC_TYPE_E1)
                hc->hw.r_irqmsk_misc |= V_STA_IRQMSK;

        /* set DTMF detection */
        if (test_bit(HFC_CHIP_DTMF, &hc->chip)) {
                if (debug & DEBUG_HFCMULTI_INIT)
                        printk(KERN_DEBUG "%s: enabling DTMF detection "
                            "for all B-channel\n", __func__);
                hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP;
                if (test_bit(HFC_CHIP_ULAW, &hc->chip))
                        hc->hw.r_dtmf |= V_ULAW_SEL;
                HFC_outb(hc, R_DTMF_N, 102 - 1);
                hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK;
        }

        /* conference engine */
        if (test_bit(HFC_CHIP_ULAW, &hc->chip))
                r_conf_en = V_CONF_EN | V_ULAW;
        else
                r_conf_en = V_CONF_EN;
        if (hc->ctype != HFC_TYPE_XHFC)
                HFC_outb(hc, R_CONF_EN, r_conf_en);

        /* setting leds */
        switch (hc->leds) {
        case 1: /* HFC-E1 OEM */
                if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
                        HFC_outb(hc, R_GPIO_SEL, 0x32);
                else
                        HFC_outb(hc, R_GPIO_SEL, 0x30);

                HFC_outb(hc, R_GPIO_EN1, 0x0f);
                HFC_outb(hc, R_GPIO_OUT1, 0x00);

                HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
                break;

        case 2: /* HFC-4S OEM */
        case 3:
                HFC_outb(hc, R_GPIO_SEL, 0xf0);
                HFC_outb(hc, R_GPIO_EN1, 0xff);
                HFC_outb(hc, R_GPIO_OUT1, 0x00);
                break;
        }

        if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) {
                hc->hw.r_st_sync = 0x10; /* V_AUTO_SYNCI */
                HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
        }

        /* set master clock */
        if (hc->masterclk >= 0) {
                if (debug & DEBUG_HFCMULTI_INIT)
                        printk(KERN_DEBUG "%s: setting ST master clock "
                            "to port %d (0..%d)\n",
                            __func__, hc->masterclk, hc->ports-1);
                hc->hw.r_st_sync |= (hc->masterclk | V_AUTO_SYNC);
                HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
        }



        /* setting misc irq */
        HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc);
        if (debug & DEBUG_HFCMULTI_INIT)
                printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n",
                    hc->hw.r_irqmsk_misc);

        /* RAM access test */
        HFC_outb(hc, R_RAM_ADDR0, 0);
        HFC_outb(hc, R_RAM_ADDR1, 0);
        HFC_outb(hc, R_RAM_ADDR2, 0);
        for (i = 0; i < 256; i++) {
                HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
                HFC_outb_nodebug(hc, R_RAM_DATA, ((i*3)&0xff));
        }
        for (i = 0; i < 256; i++) {
                HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
                HFC_inb_nodebug(hc, R_RAM_DATA);
                rval = HFC_inb_nodebug(hc, R_INT_DATA);
                if (rval != ((i * 3) & 0xff)) {
                        printk(KERN_DEBUG
                            "addr:%x val:%x should:%x\n", i, rval,
                            (i * 3) & 0xff);
                        err++;
                }
        }
        if (err) {
                printk(KERN_DEBUG "aborting - %d RAM access errors\n", err);
                err = -EIO;
                goto out;
        }

        if (debug & DEBUG_HFCMULTI_INIT)
                printk(KERN_DEBUG "%s: done\n", __func__);
out:
        spin_unlock_irqrestore(&hc->lock, flags);
        return err;
}


/*
 * control the watchdog
 */
static void
hfcmulti_watchdog(struct hfc_multi *hc)
{
        hc->wdcount++;

        if (hc->wdcount > 10) {
                hc->wdcount = 0;
                hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ?
                    V_GPIO_OUT3 : V_GPIO_OUT2;

        /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */
                HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
                HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte);
        }
}



/*
 * output leds
 */
static void
hfcmulti_leds(struct hfc_multi *hc)
{
        unsigned long lled;
        unsigned long leddw;
        int i, state, active, leds;
        struct dchannel *dch;
        int led[4];

        hc->ledcount += poll;
        if (hc->ledcount > 4096) {
                hc->ledcount -= 4096;
                hc->ledstate = 0xAFFEAFFE;
        }

        switch (hc->leds) {
        case 1: /* HFC-E1 OEM */
                /* 2 red blinking: NT mode deactivate
                 * 2 red steady:   TE mode deactivate
                 * left green:     L1 active
                 * left red:       frame sync, but no L1
                 * right green:    L2 active
                 */
                if (hc->chan[hc->dslot].sync != 2) { /* no frame sync */
                        if (hc->chan[hc->dslot].dch->dev.D.protocol
                                != ISDN_P_NT_E1) {
                                led[0] = 1;
                                led[1] = 1;
                        } else if (hc->ledcount>>11) {
                                led[0] = 1;
                                led[1] = 1;
                        } else {
                                led[0] = 0;
                                led[1] = 0;
                        }
                        led[2] = 0;
                        led[3] = 0;
                } else { /* with frame sync */
                        /* TODO make it work */
                        led[0] = 0;
                        led[1] = 0;
                        led[2] = 0;
                        led[3] = 1;
                }
                leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF;
                        /* leds are inverted */
                if (leds != (int)hc->ledstate) {
                        HFC_outb_nodebug(hc, R_GPIO_OUT1, leds);
                        hc->ledstate = leds;
                }
                break;

        case 2: /* HFC-4S OEM */
                /* red blinking = PH_DEACTIVATE NT Mode
                 * red steady   = PH_DEACTIVATE TE Mode
                 * green steady = PH_ACTIVATE
                 */
                for (i = 0; i < 4; i++) {
                        state = 0;
                        active = -1;
                        dch = hc->chan[(i << 2) | 2].dch;
                        if (dch) {
                                state = dch->state;
                                if (dch->dev.D.protocol == ISDN_P_NT_S0)
                                        active = 3;
                                else
                                        active = 7;
                        }
                        if (state) {
                                if (state == active) {
                                        led[i] = 1; /* led green */
                                } else
                                        if (dch->dev.D.protocol == ISDN_P_TE_S0)
                                                /* TE mode: led red */
                                                led[i] = 2;
                                        else
                                                if (hc->ledcount>>11)
                                                        /* led red */
                                                        led[i] = 2;
                                                else
                                                        /* led off */
                                                        led[i] = 0;
                        } else
                                led[i] = 0; /* led off */
                }
                if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
                        leds = 0;
                        for (i = 0; i < 4; i++) {
                                if (led[i] == 1) {
                                        /*green*/
                                        leds |= (0x2 << (i * 2));
                                } else if (led[i] == 2) {
                                        /*red*/
                                        leds |= (0x1 << (i * 2));
                                }
                        }
                        if (leds != (int)hc->ledstate) {
                                vpm_out(hc, 0, 0x1a8 + 3, leds);
                                hc->ledstate = leds;
                        }
                } else {
                        leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) |
                            ((led[0] > 0) << 2) | ((led[2] > 0) << 3) |
                            ((led[3] & 1) << 4) | ((led[1] & 1) << 5) |
                            ((led[0] & 1) << 6) | ((led[2] & 1) << 7);
                        if (leds != (int)hc->ledstate) {
                                HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F);
                                HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4);
                                hc->ledstate = leds;
                        }
                }
                break;

        case 3: /* HFC 1S/2S Beronet */
                /* red blinking = PH_DEACTIVATE NT Mode
                 * red steady   = PH_DEACTIVATE TE Mode
                 * green steady = PH_ACTIVATE
                 */
                for (i = 0; i < 2; i++) {
                        state = 0;
                        active = -1;
                        dch = hc->chan[(i << 2) | 2].dch;
                        if (dch) {
                                state = dch->state;
                                if (dch->dev.D.protocol == ISDN_P_NT_S0)
                                        active = 3;
                                else
                                        active = 7;
                        }
                        if (state) {
                                if (state == active) {
                                        led[i] = 1; /* led green */
                                } else
                                        if (dch->dev.D.protocol == ISDN_P_TE_S0)
                                                /* TE mode: led red */
                                                led[i] = 2;
                                        else
                                                if (hc->ledcount >> 11)
                                                        /* led red */
                                                        led[i] = 2;
                                                else
                                                        /* led off */
                                                        led[i] = 0;
                        } else
                                led[i] = 0; /* led off */
                }


                leds = (led[0] > 0) | ((led[1] > 0)<<1) | ((led[0]&1)<<2)
                        | ((led[1]&1)<<3);
                if (leds != (int)hc->ledstate) {
                        HFC_outb_nodebug(hc, R_GPIO_EN1,
                            ((led[0] > 0) << 2) | ((led[1] > 0) << 3));
                        HFC_outb_nodebug(hc, R_GPIO_OUT1,
                            ((led[0] & 1) << 2) | ((led[1] & 1) << 3));
                        hc->ledstate = leds;
                }
                break;
        case 8: /* HFC 8S+ Beronet */
                lled = 0;

                for (i = 0; i < 8; i++) {
                        state = 0;
                        active = -1;
                        dch = hc->chan[(i << 2) | 2].dch;
                        if (dch) {
                                state = dch->state;
                                if (dch->dev.D.protocol == ISDN_P_NT_S0)
                                        active = 3;
                                else
                                        active = 7;
                        }
                        if (state) {
                                if (state == active) {
                                        lled |= 0 << i;
                                } else
                                        if (hc->ledcount >> 11)
                                                lled |= 0 << i;
                                        else
                                                lled |= 1 << i;
                        } else
                                lled |= 1 << i;
                }
                leddw = lled << 24 | lled << 16 | lled << 8 | lled;
                if (leddw != hc->ledstate) {
                        /* HFC_outb(hc, R_BRG_PCM_CFG, 1);
                        HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */
                        /* was _io before */
                        HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
                        outw(0x4000, hc->pci_iobase + 4);
                        outl(leddw, hc->pci_iobase);
                        HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK);
                        hc->ledstate = leddw;
                }
                break;
        }
}
/*
 * read dtmf coefficients
 */

static void
hfcmulti_dtmf(struct hfc_multi *hc)
{
        s32             *coeff;
        u_int           mantissa;
        int             co, ch;
        struct bchannel *bch = NULL;
        u8              exponent;
        int             dtmf = 0;
        int             addr;
        u16             w_float;
        struct sk_buff  *skb;
        struct mISDNhead *hh;

        if (debug & DEBUG_HFCMULTI_DTMF)
                printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__);
        for (ch = 0; ch <= 31; ch++) {
                /* only process enabled B-channels */
                bch = hc->chan[ch].bch;
                if (!bch)
                        continue;
                if (!hc->created[hc->chan[ch].port])
                        continue;
                if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
                        continue;
                if (debug & DEBUG_HFCMULTI_DTMF)
                        printk(KERN_DEBUG "%s: dtmf channel %d:",
                                __func__, ch);
                coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]);
                dtmf = 1;
                for (co = 0; co < 8; co++) {
                        /* read W(n-1) coefficient */
                        addr = hc->DTMFbase + ((co<<7) | (ch<<2));
                        HFC_outb_nodebug(hc, R_RAM_ADDR0, addr);
                        HFC_outb_nodebug(hc, R_RAM_ADDR1, addr>>8);
                        HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr>>16)
                                | V_ADDR_INC);
                        w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
                        w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
                        if (debug & DEBUG_HFCMULTI_DTMF)
                                printk(" %04x", w_float);

                        /* decode float (see chip doc) */
                        mantissa = w_float & 0x0fff;
                        if (w_float & 0x8000)
                                mantissa |= 0xfffff000;
                        exponent = (w_float>>12) & 0x7;
                        if (exponent) {
                                mantissa ^= 0x1000;
                                mantissa <<= (exponent-1);
                        }

                        /* store coefficient */
                        coeff[co<<1] = mantissa;

                        /* read W(n) coefficient */
                        w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
                        w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
                        if (debug & DEBUG_HFCMULTI_DTMF)
                                printk(" %04x", w_float);

                        /* decode float (see chip doc) */
                        mantissa = w_float & 0x0fff;
                        if (w_float & 0x8000)
                                mantissa |= 0xfffff000;
                        exponent = (w_float>>12) & 0x7;
                        if (exponent) {
                                mantissa ^= 0x1000;
                                mantissa <<= (exponent-1);
                        }

                        /* store coefficient */
                        coeff[(co<<1)|1] = mantissa;
                }
                if (debug & DEBUG_HFCMULTI_DTMF)
                        printk(" DTMF ready %08x %08x %08x %08x "
                            "%08x %08x %08x %08x\n",
                            coeff[0], coeff[1], coeff[2], coeff[3],
                            coeff[4], coeff[5], coeff[6], coeff[7]);
                hc->chan[ch].coeff_count++;
                if (hc->chan[ch].coeff_count == 8) {
                        hc->chan[ch].coeff_count = 0;
                        skb = mI_alloc_skb(512, GFP_ATOMIC);
                        if (!skb) {
                                printk(KERN_DEBUG "%s: No memory for skb\n",
                                    __func__);
                                continue;
                        }
                        hh = mISDN_HEAD_P(skb);
                        hh->prim = PH_CONTROL_IND;
                        hh->id = DTMF_HFC_COEF;
                        memcpy(skb_put(skb, 512), hc->chan[ch].coeff, 512);
                        recv_Bchannel_skb(bch, skb);
                }
        }

        /* restart DTMF processing */
        hc->dtmf = dtmf;
        if (dtmf)
                HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF);
}


/*
 * fill fifo as much as possible
 */

static void
hfcmulti_tx(struct hfc_multi *hc, int ch)
{
        int i, ii, temp, len = 0;
        int Zspace, z1, z2; /* must be int for calculation */
        int Fspace, f1, f2;
        u_char *d;
        int *txpending, slot_tx;
        struct  bchannel *bch;
        struct  dchannel *dch;
        struct  sk_buff **sp = NULL;
        int *idxp;

        bch = hc->chan[ch].bch;
        dch = hc->chan[ch].dch;
        if ((!dch) && (!bch))
                return;

        txpending = &hc->chan[ch].txpending;
        slot_tx = hc->chan[ch].slot_tx;
        if (dch) {
                if (!test_bit(FLG_ACTIVE, &dch->Flags))
                        return;
                sp = &dch->tx_skb;
                idxp = &dch->tx_idx;
        } else {
                if (!test_bit(FLG_ACTIVE, &bch->Flags))
                        return;
                sp = &bch->tx_skb;
                idxp = &bch->tx_idx;
        }
        if (*sp)
                len = (*sp)->len;

        if ((!len) && *txpending != 1)
                return; /* no data */

        if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
            (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
            (hc->chan[ch].slot_rx < 0) &&
            (hc->chan[ch].slot_tx < 0))
                HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1));
        else
                HFC_outb_nodebug(hc, R_FIFO, ch << 1);
        HFC_wait_nodebug(hc);

        if (*txpending == 2) {
                /* reset fifo */
                HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
                HFC_wait_nodebug(hc);
                HFC_outb(hc, A_SUBCH_CFG, 0);
                *txpending = 1;
        }
next_frame:
        if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
                f1 = HFC_inb_nodebug(hc, A_F1);
                f2 = HFC_inb_nodebug(hc, A_F2);
                while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) {
                        if (debug & DEBUG_HFCMULTI_FIFO)
                                printk(KERN_DEBUG
                                    "%s(card %d): reread f2 because %d!=%d\n",
                                    __func__, hc->id + 1, temp, f2);
                        f2 = temp; /* repeat until F2 is equal */
                }
                Fspace = f2 - f1 - 1;
                if (Fspace < 0)
                        Fspace += hc->Flen;
                /*
                 * Old FIFO handling doesn't give us the current Z2 read
                 * pointer, so we cannot send the next frame before the fifo
                 * is empty. It makes no difference except for a slightly
                 * lower performance.
                 */
                if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) {
                        if (f1 != f2)
                                Fspace = 0;
                        else
                                Fspace = 1;
                }
                /* one frame only for ST D-channels, to allow resending */
                if (hc->ctype != HFC_TYPE_E1 && dch) {
                        if (f1 != f2)
                                Fspace = 0;
                }
                /* F-counter full condition */
                if (Fspace == 0)
                        return;
        }
        z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
        z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
        while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) {
                if (debug & DEBUG_HFCMULTI_FIFO)
                        printk(KERN_DEBUG "%s(card %d): reread z2 because "

                                "%d!=%d\n", __func__, hc->id + 1, temp, z2);
                z2 = temp; /* repeat unti Z2 is equal */
        }
        hc->chan[ch].Zfill = z1 - z2;
        if (hc->chan[ch].Zfill < 0)
                hc->chan[ch].Zfill += hc->Zlen;
        Zspace = z2 - z1;
        if (Zspace <= 0)
                Zspace += hc->Zlen;
        Zspace -= 4; /* keep not too full, so pointers will not overrun */
        /* fill transparent data only to maxinum transparent load (minus 4) */
        if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
                Zspace = Zspace - hc->Zlen + hc->max_trans;
        if (Zspace <= 0) /* no space of 4 bytes */
                return;

        /* if no data */
        if (!len) {
                if (z1 == z2) { /* empty */
                        /* if done with FIFO audio data during PCM connection */
                        if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) &&
                            *txpending && slot_tx >= 0) {
                                if (debug & DEBUG_HFCMULTI_MODE)
                                        printk(KERN_DEBUG
                                            "%s: reconnecting PCM due to no "
                                            "more FIFO data: channel %d "
                                            "slot_tx %d\n",
                                            __func__, ch, slot_tx);
                                /* connect slot */
                                if (hc->ctype == HFC_TYPE_XHFC)
                                        HFC_outb(hc, A_CON_HDLC, 0xc0
                                            | 0x07 << 2 | V_HDLC_TRP | V_IFF);
                                                /* Enable FIFO, no interrupt */
                                else
                                        HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
                                            V_HDLC_TRP | V_IFF);
                                HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
                                HFC_wait_nodebug(hc);
                                if (hc->ctype == HFC_TYPE_XHFC)
                                        HFC_outb(hc, A_CON_HDLC, 0xc0
                                            | 0x07 << 2 | V_HDLC_TRP | V_IFF);
                                                /* Enable FIFO, no interrupt */
                                else
                                        HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
                                            V_HDLC_TRP | V_IFF);
                                HFC_outb_nodebug(hc, R_FIFO, ch<<1);
                                HFC_wait_nodebug(hc);
                        }
                        *txpending = 0;
                }
                return; /* no data */
        }

        /* "fill fifo if empty" feature */
        if (bch && test_bit(FLG_FILLEMPTY, &bch->Flags)
                && !test_bit(FLG_HDLC, &bch->Flags) && z2 == z1) {
                if (debug & DEBUG_HFCMULTI_FILL)
                        printk(KERN_DEBUG "%s: buffer empty, so we have "
                                "underrun\n", __func__);
                /* fill buffer, to prevent future underrun */
                hc->write_fifo(hc, hc->silence_data, poll >> 1);
                Zspace -= (poll >> 1);
        }

        /* if audio data and connected slot */
        if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending)
                && slot_tx >= 0) {
                if (debug & DEBUG_HFCMULTI_MODE)
                        printk(KERN_DEBUG "%s: disconnecting PCM due to "
                            "FIFO data: channel %d slot_tx %d\n",
                            __func__, ch, slot_tx);
                /* disconnect slot */
                if (hc->ctype == HFC_TYPE_XHFC)
                        HFC_outb(hc, A_CON_HDLC, 0x80
                            | 0x07 << 2 | V_HDLC_TRP | V_IFF);
                                /* Enable FIFO, no interrupt */
                else
                        HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
                            V_HDLC_TRP | V_IFF);
                HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
                HFC_wait_nodebug(hc);
                if (hc->ctype == HFC_TYPE_XHFC)
                        HFC_outb(hc, A_CON_HDLC, 0x80
                            | 0x07 << 2 | V_HDLC_TRP | V_IFF);
                                /* Enable FIFO, no interrupt */
                else
                        HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
                            V_HDLC_TRP | V_IFF);
                HFC_outb_nodebug(hc, R_FIFO, ch<<1);
                HFC_wait_nodebug(hc);
        }
        *txpending = 1;

        /* show activity */
        hc->activity[hc->chan[ch].port] = 1;

        /* fill fifo to what we have left */
        ii = len;
        if (dch || test_bit(FLG_HDLC, &bch->Flags))
                temp = 1;
        else
                temp = 0;
        i = *idxp;
        d = (*sp)->data + i;
        if (ii - i > Zspace)
                ii = Zspace + i;
        if (debug & DEBUG_HFCMULTI_FIFO)
                printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space "
                    "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n",
                        __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i,
                        temp ? "HDLC" : "TRANS");

        /* Have to prep the audio data */
        hc->write_fifo(hc, d, ii - i);
        hc->chan[ch].Zfill += ii - i;
        *idxp = ii;

        /* if not all data has been written */
        if (ii != len) {
                /* NOTE: fifo is started by the calling function */
                return;
        }

        /* if all data has been written, terminate frame */
        if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
                /* increment f-counter */
                HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
                HFC_wait_nodebug(hc);
        }

        /* send confirm, since get_net_bframe will not do it with trans */
        if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
                confirm_Bsend(bch);

        /* check for next frame */
        dev_kfree_skb(*sp);
        if (bch && get_next_bframe(bch)) { /* hdlc is confirmed here */
                len = (*sp)->len;
                goto next_frame;
        }
        if (dch && get_next_dframe(dch)) {
                len = (*sp)->len;
                goto next_frame;
        }

        /*
         * now we have no more data, so in case of transparent,
         * we set the last byte in fifo to 'silence' in case we will get
         * no more data at all. this prevents sending an undefined value.
         */
        if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
                HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
}


/* NOTE: only called if E1 card is in active state */
static void
hfcmulti_rx(struct hfc_multi *hc, int ch)
{
        int temp;
        int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */
        int f1 = 0, f2 = 0; /* = 0, to make GCC happy */
        int again = 0;
        struct  bchannel *bch;
        struct  dchannel *dch;
        struct sk_buff  *skb, **sp = NULL;
        int     maxlen;

        bch = hc->chan[ch].bch;
        dch = hc->chan[ch].dch;
        if ((!dch) && (!bch))
                return;
        if (dch) {
                if (!test_bit(FLG_ACTIVE, &dch->Flags))
                        return;
                sp = &dch->rx_skb;
                maxlen = dch->maxlen;
        } else {
                if (!test_bit(FLG_ACTIVE, &bch->Flags))
                        return;
                sp = &bch->rx_skb;
                maxlen = bch->maxlen;
        }
next_frame:
        /* on first AND before getting next valid frame, R_FIFO must be written
           to. */
        if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
            (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
            (hc->chan[ch].slot_rx < 0) &&
            (hc->chan[ch].slot_tx < 0))
                HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch<<1) | 1);
        else
                HFC_outb_nodebug(hc, R_FIFO, (ch<<1)|1);
        HFC_wait_nodebug(hc);

        /* ignore if rx is off BUT change fifo (above) to start pending TX */
        if (hc->chan[ch].rx_off)
                return;

        if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
                f1 = HFC_inb_nodebug(hc, A_F1);
                while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) {
                        if (debug & DEBUG_HFCMULTI_FIFO)
                                printk(KERN_DEBUG
                                    "%s(card %d): reread f1 because %d!=%d\n",
                                    __func__, hc->id + 1, temp, f1);
                        f1 = temp; /* repeat until F1 is equal */
                }
                f2 = HFC_inb_nodebug(hc, A_F2);
        }
        z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
        while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) {
                if (debug & DEBUG_HFCMULTI_FIFO)
                        printk(KERN_DEBUG "%s(card %d): reread z2 because "
                                "%d!=%d\n", __func__, hc->id + 1, temp, z2);
                z1 = temp; /* repeat until Z1 is equal */
        }
        z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
        Zsize = z1 - z2;
        if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2)
                /* complete hdlc frame */
                Zsize++;
        if (Zsize < 0)
                Zsize += hc->Zlen;
        /* if buffer is empty */
        if (Zsize <= 0)
                return;

        if (*sp == NULL) {
                *sp = mI_alloc_skb(maxlen + 3, GFP_ATOMIC);
                if (*sp == NULL) {
                        printk(KERN_DEBUG "%s: No mem for rx_skb\n",
                            __func__);
                        return;
                }
        }
        /* show activity */
        hc->activity[hc->chan[ch].port] = 1;

        /* empty fifo with what we have */
        if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
                if (debug & DEBUG_HFCMULTI_FIFO)
                        printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d "
                            "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) "
                            "got=%d (again %d)\n", __func__, hc->id + 1, ch,
                            Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE",
                            f1, f2, Zsize + (*sp)->len, again);
                /* HDLC */
                if ((Zsize + (*sp)->len) > (maxlen + 3)) {
                        if (debug & DEBUG_HFCMULTI_FIFO)
                                printk(KERN_DEBUG
                                    "%s(card %d): hdlc-frame too large.\n",
                                    __func__, hc->id + 1);
                        skb_trim(*sp, 0);
                        HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
                        HFC_wait_nodebug(hc);
                        return;
                }

                hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);

                if (f1 != f2) {
                        /* increment Z2,F2-counter */
                        HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
                        HFC_wait_nodebug(hc);
                        /* check size */
                        if ((*sp)->len < 4) {
                                if (debug & DEBUG_HFCMULTI_FIFO)
                                        printk(KERN_DEBUG
                                            "%s(card %d): Frame below minimum "
                                            "size\n", __func__, hc->id + 1);
                                skb_trim(*sp, 0);
                                goto next_frame;
                        }
                        /* there is at least one complete frame, check crc */
                        if ((*sp)->data[(*sp)->len - 1]) {
                                if (debug & DEBUG_HFCMULTI_CRC)
                                        printk(KERN_DEBUG
                                            "%s: CRC-error\n", __func__);
                                skb_trim(*sp, 0);
                                goto next_frame;
                        }
                        skb_trim(*sp, (*sp)->len - 3);
                        if ((*sp)->len < MISDN_COPY_SIZE) {
                                skb = *sp;
                                *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
                                if (*sp) {
                                        memcpy(skb_put(*sp, skb->len),
                                            skb->data, skb->len);
                                        skb_trim(skb, 0);
                                } else {
                                        printk(KERN_DEBUG "%s: No mem\n",
                                            __func__);
                                        *sp = skb;
                                        skb = NULL;
                                }
                        } else {
                                skb = NULL;
                        }
                        if (debug & DEBUG_HFCMULTI_FIFO) {
                                printk(KERN_DEBUG "%s(card %d):",
                                        __func__, hc->id + 1);
                                temp = 0;
                                while (temp < (*sp)->len)
                                        printk(" %02x", (*sp)->data[temp++]);
                                printk("\n");
                        }
                        if (dch)
                                recv_Dchannel(dch);
                        else
                                recv_Bchannel(bch, MISDN_ID_ANY);
                        *sp = skb;
                        again++;
                        goto next_frame;
                }
                /* there is an incomplete frame */
        } else {
                /* transparent */
                if (Zsize > skb_tailroom(*sp))
                        Zsize = skb_tailroom(*sp);
                hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
                if (((*sp)->len) < MISDN_COPY_SIZE) {
                        skb = *sp;
                        *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
                        if (*sp) {
                                memcpy(skb_put(*sp, skb->len),
                                    skb->data, skb->len);
                                skb_trim(skb, 0);
                        } else {
                                printk(KERN_DEBUG "%s: No mem\n", __func__);
                                *sp = skb;
                                skb = NULL;
                        }
                } else {
                        skb = NULL;
                }
                if (debug & DEBUG_HFCMULTI_FIFO)
                        printk(KERN_DEBUG
                            "%s(card %d): fifo(%d) reading %d bytes "
                            "(z1=%04x, z2=%04x) TRANS\n",
                                __func__, hc->id + 1, ch, Zsize, z1, z2);
                /* only bch is transparent */
                recv_Bchannel(bch, hc->chan[ch].Zfill);
                *sp = skb;
        }
}


/*
 * Interrupt handler
 */
static void
signal_state_up(struct dchannel *dch, int info, char *msg)
{
        struct sk_buff  *skb;
        int             id, data = info;

        if (debug & DEBUG_HFCMULTI_STATE)
                printk(KERN_DEBUG "%s: %s\n", __func__, msg);

        id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */

        skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data,
                GFP_ATOMIC);
        if (!skb)
                return;
        recv_Dchannel_skb(dch, skb);
}

static inline void
handle_timer_irq(struct hfc_multi *hc)
{
        int             ch, temp;
        struct dchannel *dch;
        u_long          flags;

        /* process queued resync jobs */
        if (hc->e1_resync) {
                /* lock, so e1_resync gets not changed */
                spin_lock_irqsave(&HFClock, flags);
                if (hc->e1_resync & 1) {
                        if (debug & DEBUG_HFCMULTI_PLXSD)
                                printk(KERN_DEBUG "Enable SYNC_I\n");
                        HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC);
                        /* disable JATT, if RX_SYNC is set */
                        if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
                                HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
                }
                if (hc->e1_resync & 2) {
                        if (debug & DEBUG_HFCMULTI_PLXSD)
                                printk(KERN_DEBUG "Enable jatt PLL\n");
                        HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
                }
                if (hc->e1_resync & 4) {
                        if (debug & DEBUG_HFCMULTI_PLXSD)
                                printk(KERN_DEBUG
                                    "Enable QUARTZ for HFC-E1\n");
                        /* set jatt to quartz */
                        HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC
                                | V_JATT_OFF);
                        /* switch to JATT, in case it is not already */
                        HFC_outb(hc, R_SYNC_OUT, 0);
                }
                hc->e1_resync = 0;
                spin_unlock_irqrestore(&HFClock, flags);
        }

        if (hc->ctype != HFC_TYPE_E1 || hc->e1_state == 1)
                for (ch = 0; ch <= 31; ch++) {
                        if (hc->created[hc->chan[ch].port]) {
                                hfcmulti_tx(hc, ch);
                                /* fifo is started when switching to rx-fifo */
                                hfcmulti_rx(hc, ch);
                                if (hc->chan[ch].dch &&
                                    hc->chan[ch].nt_timer > -1) {
                                        dch = hc->chan[ch].dch;
                                        if (!(--hc->chan[ch].nt_timer)) {
                                                schedule_event(dch,
                                                    FLG_PHCHANGE);
                                                if (debug &
                                                    DEBUG_HFCMULTI_STATE)
                                                        printk(KERN_DEBUG
                                                            "%s: nt_timer at "
                                                            "state %x\n",
                                                            __func__,
                                                            dch->state);
                                        }
                                }
                        }
                }
        if (hc->ctype == HFC_TYPE_E1 && hc->created[0]) {
                dch = hc->chan[hc->dslot].dch;
                if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
                        /* LOS */
                        temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS;
                        if (!temp && hc->chan[hc->dslot].los)
                                signal_state_up(dch, L1_SIGNAL_LOS_ON,
                                    "LOS detected");
                        if (temp && !hc->chan[hc->dslot].los)
                                signal_state_up(dch, L1_SIGNAL_LOS_OFF,
                                    "LOS gone");
                        hc->chan[hc->dslot].los = temp;
                }
                if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dslot].cfg)) {
                        /* AIS */
                        temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS;
                        if (!temp && hc->chan[hc->dslot].ais)
                                signal_state_up(dch, L1_SIGNAL_AIS_ON,
                                    "AIS detected");
                        if (temp && !hc->chan[hc->dslot].ais)
                                signal_state_up(dch, L1_SIGNAL_AIS_OFF,
                                    "AIS gone");
                        hc->chan[hc->dslot].ais = temp;
                }
                if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dslot].cfg)) {
                        /* SLIP */
                        temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX;
                        if (!temp && hc->chan[hc->dslot].slip_rx)
                                signal_state_up(dch, L1_SIGNAL_SLIP_RX,
                                    " bit SLIP detected RX");
                        hc->chan[hc->dslot].slip_rx = temp;
                        temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX;
                        if (!temp && hc->chan[hc->dslot].slip_tx)
                                signal_state_up(dch, L1_SIGNAL_SLIP_TX,
                                    " bit SLIP detected TX");
                        hc->chan[hc->dslot].slip_tx = temp;
                }
                if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dslot].cfg)) {
                        /* RDI */
                        temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A;
                        if (!temp && hc->chan[hc->dslot].rdi)
                                signal_state_up(dch, L1_SIGNAL_RDI_ON,
                                    "RDI detected");
                        if (temp && !hc->chan[hc->dslot].rdi)
                                signal_state_up(dch, L1_SIGNAL_RDI_OFF,
                                    "RDI gone");
                        hc->chan[hc->dslot].rdi = temp;
                }
                temp = HFC_inb_nodebug(hc, R_JATT_DIR);
                switch (hc->chan[hc->dslot].sync) {
                case 0:
                        if ((temp & 0x60) == 0x60) {
                                if (debug & DEBUG_HFCMULTI_SYNC)
                                        printk(KERN_DEBUG
                                            "%s: (id=%d) E1 now "
                                            "in clock sync\n",
                                            __func__, hc->id);
                                HFC_outb(hc, R_RX_OFF,
                                    hc->chan[hc->dslot].jitter | V_RX_INIT);
                                HFC_outb(hc, R_TX_OFF,
                                    hc->chan[hc->dslot].jitter | V_RX_INIT);
                                hc->chan[hc->dslot].sync = 1;
                                goto check_framesync;
                        }
                        break;
                case 1:
                        if ((temp & 0x60) != 0x60) {
                                if (debug & DEBUG_HFCMULTI_SYNC)
                                        printk(KERN_DEBUG
                                            "%s: (id=%d) E1 "
                                            "lost clock sync\n",
                                            __func__, hc->id);
                                hc->chan[hc->dslot].sync = 0;
                                break;
                        }
check_framesync:
                        temp = HFC_inb_nodebug(hc, R_SYNC_STA);
                        if (temp == 0x27) {
                                if (debug & DEBUG_HFCMULTI_SYNC)
                                        printk(KERN_DEBUG
                                            "%s: (id=%d) E1 "
                                            "now in frame sync\n",
                                            __func__, hc->id);
                                hc->chan[hc->dslot].sync = 2;
                        }
                        break;
                case 2:
                        if ((temp & 0x60) != 0x60) {
                                if (debug & DEBUG_HFCMULTI_SYNC)
                                        printk(KERN_DEBUG
                                            "%s: (id=%d) E1 lost "
                                            "clock & frame sync\n",
                                            __func__, hc->id);
                                hc->chan[hc->dslot].sync = 0;
                                break;
                        }
                        temp = HFC_inb_nodebug(hc, R_SYNC_STA);
                        if (temp != 0x27) {
                                if (debug & DEBUG_HFCMULTI_SYNC)
                                        printk(KERN_DEBUG
                                            "%s: (id=%d) E1 "
                                            "lost frame sync\n",
                                            __func__, hc->id);
                                hc->chan[hc->dslot].sync = 1;
                        }
                        break;
                }
        }

        if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
                hfcmulti_watchdog(hc);

        if (hc->leds)
                hfcmulti_leds(hc);
}

static void
ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech)
{
        struct dchannel *dch;
        int             ch;
        int             active;
        u_char          st_status, temp;

        /* state machine */
        for (ch = 0; ch <= 31; ch++) {
                if (hc->chan[ch].dch) {
                        dch = hc->chan[ch].dch;
                        if (r_irq_statech & 1) {
                                HFC_outb_nodebug(hc, R_ST_SEL,
                                        hc->chan[ch].port);
                                /* undocumented: delay after R_ST_SEL */
                                udelay(1);
                                /* undocumented: status changes during read */
                                st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE);
                                while (st_status != (temp =
                                        HFC_inb_nodebug(hc, A_ST_RD_STATE))) {
                                        if (debug & DEBUG_HFCMULTI_STATE)
                                                printk(KERN_DEBUG "%s: reread "
                                                    "STATE because %d!=%d\n",
                                                    __func__, temp,
                                                    st_status);
                                        st_status = temp; /* repeat */
                                }

                                /* Speech Design TE-sync indication */
                                if (test_bit(HFC_CHIP_PLXSD, &hc->chip) &&
                                        dch->dev.D.protocol == ISDN_P_TE_S0) {
                                        if (st_status & V_FR_SYNC_ST)
                                                hc->syncronized |=
                                                    (1 << hc->chan[ch].port);
                                        else
                                                hc->syncronized &=
                                                   ~(1 << hc->chan[ch].port);
                                }
                                dch->state = st_status & 0x0f;
                                if (dch->dev.D.protocol == ISDN_P_NT_S0)
                                        active = 3;
                                else
                                        active = 7;
                                if (dch->state == active) {
                                        HFC_outb_nodebug(hc, R_FIFO,
                                                (ch << 1) | 1);
                                        HFC_wait_nodebug(hc);
                                        HFC_outb_nodebug(hc,
                                                R_INC_RES_FIFO, V_RES_F);
                                        HFC_wait_nodebug(hc);
                                        dch->tx_idx = 0;
                                }
                                schedule_event(dch, FLG_PHCHANGE);
                                if (debug & DEBUG_HFCMULTI_STATE)
                                        printk(KERN_DEBUG
                                            "%s: S/T newstate %x port %d\n",
                                            __func__, dch->state,
                                            hc->chan[ch].port);
                        }
                        r_irq_statech >>= 1;
                }
        }
        if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
                plxsd_checksync(hc, 0);
}

static void
fifo_irq(struct hfc_multi *hc, int block)
{
        int     ch, j;
        struct dchannel *dch;
        struct bchannel *bch;
        u_char r_irq_fifo_bl;

        r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block);
        j = 0;
        while (j < 8) {
                ch = (block << 2) + (j >> 1);
                dch = hc->chan[ch].dch;
                bch = hc->chan[ch].bch;
                if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) {
                        j += 2;
                        continue;
                }
                if (dch && (r_irq_fifo_bl & (1 << j)) &&
                    test_bit(FLG_ACTIVE, &dch->Flags)) {
                        hfcmulti_tx(hc, ch);
                        /* start fifo */
                        HFC_outb_nodebug(hc, R_FIFO, 0);
                        HFC_wait_nodebug(hc);
                }
                if (bch && (r_irq_fifo_bl & (1 << j)) &&
                    test_bit(FLG_ACTIVE, &bch->Flags)) {
                        hfcmulti_tx(hc, ch);
                        /* start fifo */
                        HFC_outb_nodebug(hc, R_FIFO, 0);
                        HFC_wait_nodebug(hc);
                }
                j++;
                if (dch && (r_irq_fifo_bl & (1 << j)) &&
                    test_bit(FLG_ACTIVE, &dch->Flags)) {
                        hfcmulti_rx(hc, ch);
                }
                if (bch && (r_irq_fifo_bl & (1 << j)) &&
                    test_bit(FLG_ACTIVE, &bch->Flags)) {
                        hfcmulti_rx(hc, ch);
                }
                j++;
        }
}

#ifdef IRQ_DEBUG
int irqsem;
#endif
static irqreturn_t
hfcmulti_interrupt(int intno, void *dev_id)
{
#ifdef IRQCOUNT_DEBUG
        static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0,
            iq5 = 0, iq6 = 0, iqcnt = 0;
#endif
        struct hfc_multi        *hc = dev_id;
        struct dchannel         *dch;
        u_char                  r_irq_statech, status, r_irq_misc, r_irq_oview;
        int                     i;
        void __iomem            *plx_acc;
        u_short                 wval;
        u_char                  e1_syncsta, temp;
        u_long                  flags;

        if (!hc) {
                printk(KERN_ERR "HFC-multi: Spurious interrupt!\n");
                return IRQ_NONE;
        }

        spin_lock(&hc->lock);

#ifdef IRQ_DEBUG
        if (irqsem)
                printk(KERN_ERR "irq for card %d during irq from "
                "card %d, this is no bug.\n", hc->id + 1, irqsem);
        irqsem = hc->id + 1;
#endif
#ifdef CONFIG_MISDN_HFCMULTI_8xx
        if (hc->immap->im_cpm.cp_pbdat & hc->pb_irqmsk)
                goto irq_notforus;
#endif
        if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
                spin_lock_irqsave(&plx_lock, flags);
                plx_acc = hc->plx_membase + PLX_INTCSR;
                wval = readw(plx_acc);
                spin_unlock_irqrestore(&plx_lock, flags);
                if (!(wval & PLX_INTCSR_LINTI1_STATUS))
                        goto irq_notforus;
        }

        status = HFC_inb_nodebug(hc, R_STATUS);
        r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH);
#ifdef IRQCOUNT_DEBUG
        if (r_irq_statech)
                iq1++;
        if (status & V_DTMF_STA)
                iq2++;
        if (status & V_LOST_STA)
                iq3++;
        if (status & V_EXT_IRQSTA)
                iq4++;
        if (status & V_MISC_IRQSTA)
                iq5++;
        if (status & V_FR_IRQSTA)
                iq6++;
        if (iqcnt++ > 5000) {
                printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n",
                    iq1, iq2, iq3, iq4, iq5, iq6);
                iqcnt = 0;
        }
#endif

        if (!r_irq_statech &&
            !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA |
            V_MISC_IRQSTA | V_FR_IRQSTA))) {
                /* irq is not for us */
                goto irq_notforus;
        }
        hc->irqcnt++;
        if (r_irq_statech) {
                if (hc->ctype != HFC_TYPE_E1)
                        ph_state_irq(hc, r_irq_statech);
        }
        if (status & V_EXT_IRQSTA)
                ; /* external IRQ */
        if (status & V_LOST_STA) {
                /* LOST IRQ */
                HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */
        }
        if (status & V_MISC_IRQSTA) {
                /* misc IRQ */
                r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC);
                r_irq_misc &= hc->hw.r_irqmsk_misc; /* ignore disabled irqs */
                if (r_irq_misc & V_STA_IRQ) {
                        if (hc->ctype == HFC_TYPE_E1) {
                                /* state machine */
                                dch = hc->chan[hc->dslot].dch;
                                e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA);
                                if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
                                 && hc->e1_getclock) {
                                        if (e1_syncsta & V_FR_SYNC_E1)
                                                hc->syncronized = 1;
                                        else
                                                hc->syncronized = 0;
                                }
                                /* undocumented: status changes during read */
                                dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA);
                                while (dch->state != (temp =
                                        HFC_inb_nodebug(hc, R_E1_RD_STA))) {
                                        if (debug & DEBUG_HFCMULTI_STATE)
                                                printk(KERN_DEBUG "%s: reread "
                                                    "STATE because %d!=%d\n",
                                                    __func__, temp,
                                                    dch->state);
                                        dch->state = temp; /* repeat */
                                }
                                dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA)
                                        & 0x7;
                                schedule_event(dch, FLG_PHCHANGE);
                                if (debug & DEBUG_HFCMULTI_STATE)
                                        printk(KERN_DEBUG
                                            "%s: E1 (id=%d) newstate %x\n",
                                            __func__, hc->id, dch->state);
                                if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
                                        plxsd_checksync(hc, 0);
                        }
                }
                if (r_irq_misc & V_TI_IRQ) {
                        if (hc->iclock_on)
                                mISDN_clock_update(hc->iclock, poll, NULL);
                        handle_timer_irq(hc);
                }

                if (r_irq_misc & V_DTMF_IRQ)
                        hfcmulti_dtmf(hc);

                if (r_irq_misc & V_IRQ_PROC) {
                        static int irq_proc_cnt;
                        if (!irq_proc_cnt++)
                                printk(KERN_DEBUG "%s: got V_IRQ_PROC -"
                                    " this should not happen\n", __func__);
                }

        }
        if (status & V_FR_IRQSTA) {
                /* FIFO IRQ */
                r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW);
                for (i = 0; i < 8; i++) {
                        if (r_irq_oview & (1 << i))
                                fifo_irq(hc, i);
                }
        }

#ifdef IRQ_DEBUG
        irqsem = 0;
#endif
        spin_unlock(&hc->lock);
        return IRQ_HANDLED;

irq_notforus:
#ifdef IRQ_DEBUG
        irqsem = 0;
#endif
        spin_unlock(&hc->lock);
        return IRQ_NONE;
}


/*
 * timer callback for D-chan busy resolution. Currently no function
 */

static void
hfcmulti_dbusy_timer(struct hfc_multi *hc)
{
}


/*
 * activate/deactivate hardware for selected channels and mode
 *
 * configure B-channel with the given protocol
 * ch eqals to the HFC-channel (0-31)
 * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31
 * for S/T, 1-31 for E1)
 * the hdlc interrupts will be set/unset
 */
static int
mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
    int bank_tx, int slot_rx, int bank_rx)
{
        int flow_tx = 0, flow_rx = 0, routing = 0;
        int oslot_tx, oslot_rx;
        int conf;

        if (ch < 0 || ch > 31)
                return -EINVAL;
        oslot_tx = hc->chan[ch].slot_tx;
        oslot_rx = hc->chan[ch].slot_rx;
        conf = hc->chan[ch].conf;

        if (debug & DEBUG_HFCMULTI_MODE)
                printk(KERN_DEBUG
                    "%s: card %d channel %d protocol %x slot old=%d new=%d "
                    "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n",
                    __func__, hc->id, ch, protocol, oslot_tx, slot_tx,
                    bank_tx, oslot_rx, slot_rx, bank_rx);

        if (oslot_tx >= 0 && slot_tx != oslot_tx) {
                /* remove from slot */
                if (debug & DEBUG_HFCMULTI_MODE)
                        printk(KERN_DEBUG "%s: remove from slot %d (TX)\n",
                            __func__, oslot_tx);
                if (hc->slot_owner[oslot_tx<<1] == ch) {
                        HFC_outb(hc, R_SLOT, oslot_tx << 1);
                        HFC_outb(hc, A_SL_CFG, 0);
                        if (hc->ctype != HFC_TYPE_XHFC)
                                HFC_outb(hc, A_CONF, 0);
                        hc->slot_owner[oslot_tx<<1] = -1;
                } else {
                        if (debug & DEBUG_HFCMULTI_MODE)
                                printk(KERN_DEBUG
                                    "%s: we are not owner of this tx slot "
                                    "anymore, channel %d is.\n",
                                    __func__, hc->slot_owner[oslot_tx<<1]);
                }
        }

        if (oslot_rx >= 0 && slot_rx != oslot_rx) {
                /* remove from slot */
                if (debug & DEBUG_HFCMULTI_MODE)
                        printk(KERN_DEBUG
                            "%s: remove from slot %d (RX)\n",
                            __func__, oslot_rx);
                if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) {
                        HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR);
                        HFC_outb(hc, A_SL_CFG, 0);
                        hc->slot_owner[(oslot_rx << 1) | 1] = -1;
                } else {
                        if (debug & DEBUG_HFCMULTI_MODE)
                                printk(KERN_DEBUG
                                    "%s: we are not owner of this rx slot "
                                    "anymore, channel %d is.\n",
                                    __func__,
                                    hc->slot_owner[(oslot_rx << 1) | 1]);
                }
        }

        if (slot_tx < 0) {
                flow_tx = 0x80; /* FIFO->ST */
                /* disable pcm slot */
                hc->chan[ch].slot_tx = -1;
                hc->chan[ch].bank_tx = 0;
        } else {
                /* set pcm slot */
                if (hc->chan[ch].txpending)
                        flow_tx = 0x80; /* FIFO->ST */
                else
                        flow_tx = 0xc0; /* PCM->ST */
                /* put on slot */
                routing = bank_tx ? 0xc0 : 0x80;
                if (conf >= 0 || bank_tx > 1)
                        routing = 0x40; /* loop */
                if (debug & DEBUG_HFCMULTI_MODE)
                        printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
                            " %d flow %02x routing %02x conf %d (TX)\n",
                            __func__, ch, slot_tx, bank_tx,
                            flow_tx, routing, conf);
                HFC_outb(hc, R_SLOT, slot_tx << 1);
                HFC_outb(hc, A_SL_CFG, (ch<<1) | routing);
                if (hc->ctype != HFC_TYPE_XHFC)
                        HFC_outb(hc, A_CONF,
                                (conf < 0) ? 0 : (conf | V_CONF_SL));
                hc->slot_owner[slot_tx << 1] = ch;
                hc->chan[ch].slot_tx = slot_tx;
                hc->chan[ch].bank_tx = bank_tx;
        }
        if (slot_rx < 0) {
                /* disable pcm slot */
                flow_rx = 0x80; /* ST->FIFO */
                hc->chan[ch].slot_rx = -1;
                hc->chan[ch].bank_rx = 0;
        } else {
                /* set pcm slot */
                if (hc->chan[ch].txpending)
                        flow_rx = 0x80; /* ST->FIFO */
                else
                        flow_rx = 0xc0; /* ST->(FIFO,PCM) */
                /* put on slot */
                routing = bank_rx ? 0x80 : 0xc0; /* reversed */
                if (conf >= 0 || bank_rx > 1)
                        routing = 0x40; /* loop */
                if (debug & DEBUG_HFCMULTI_MODE)
                        printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
                            " %d flow %02x routing %02x conf %d (RX)\n",
                            __func__, ch, slot_rx, bank_rx,
                            flow_rx, routing, conf);
                HFC_outb(hc, R_SLOT, (slot_rx<<1) | V_SL_DIR);
                HFC_outb(hc, A_SL_CFG, (ch<<1) | V_CH_DIR | routing);
                hc->slot_owner[(slot_rx<<1)|1] = ch;
                hc->chan[ch].slot_rx = slot_rx;
                hc->chan[ch].bank_rx = bank_rx;
        }

        switch (protocol) {
        case (ISDN_P_NONE):
                /* disable TX fifo */
                HFC_outb(hc, R_FIFO, ch << 1);
                HFC_wait(hc);
                HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF);
                HFC_outb(hc, A_SUBCH_CFG, 0);
                HFC_outb(hc, A_IRQ_MSK, 0);
                HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
                HFC_wait(hc);
                /* disable RX fifo */
                HFC_outb(hc, R_FIFO, (ch<<1)|1);
                HFC_wait(hc);
                HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00);
                HFC_outb(hc, A_SUBCH_CFG, 0);
                HFC_outb(hc, A_IRQ_MSK, 0);
                HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
                HFC_wait(hc);
                if (hc->chan[ch].bch && hc->ctype != HFC_TYPE_E1) {
                        hc->hw.a_st_ctrl0[hc->chan[ch].port] &=
                            ((ch & 0x3) == 0) ? ~V_B1_EN : ~V_B2_EN;
                        HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
                        /* undocumented: delay after R_ST_SEL */
                        udelay(1);
                        HFC_outb(hc, A_ST_CTRL0,
                            hc->hw.a_st_ctrl0[hc->chan[ch].port]);
                }
                if (hc->chan[ch].bch) {
                        test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
                        test_and_clear_bit(FLG_TRANSPARENT,
                            &hc->chan[ch].bch->Flags);
                }
                break;
        case (ISDN_P_B_RAW): /* B-channel */

                if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
                    (hc->chan[ch].slot_rx < 0) &&
                    (hc->chan[ch].slot_tx < 0)) {

                        printk(KERN_DEBUG
                            "Setting B-channel %d to echo cancelable "
                            "state on PCM slot %d\n", ch,
                            ((ch / 4) * 8) + ((ch % 4) * 4) + 1);