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22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/pci.h>
25#include <linux/delay.h>
26#include <media/cx25840.h>
27
28#include "cx23885.h"
29#include "tuner-xc2028.h"
30#include "netup-init.h"
31#include "cx23888-ir.h"
32
33static unsigned int enable_885_ir;
34module_param(enable_885_ir, int, 0644);
35MODULE_PARM_DESC(enable_885_ir,
36 "Enable integrated IR controller for supported\n"
37 "\t\t CX2388[57] boards that are wired for it:\n"
38 "\t\t\tHVR-1250 (reported safe)\n"
39 "\t\t\tTeVii S470 (reported unsafe)\n"
40 "\t\t This can cause an interrupt storm with some cards.\n"
41 "\t\t Default: 0 [Disabled]");
42
43
44
45
46struct cx23885_board cx23885_boards[] = {
47 [CX23885_BOARD_UNKNOWN] = {
48 .name = "UNKNOWN/GENERIC",
49
50 .clk_freq = 0,
51 .input = {{
52 .type = CX23885_VMUX_COMPOSITE1,
53 .vmux = 0,
54 }, {
55 .type = CX23885_VMUX_COMPOSITE2,
56 .vmux = 1,
57 }, {
58 .type = CX23885_VMUX_COMPOSITE3,
59 .vmux = 2,
60 }, {
61 .type = CX23885_VMUX_COMPOSITE4,
62 .vmux = 3,
63 } },
64 },
65 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
66 .name = "Hauppauge WinTV-HVR1800lp",
67 .portc = CX23885_MPEG_DVB,
68 .input = {{
69 .type = CX23885_VMUX_TELEVISION,
70 .vmux = 0,
71 .gpio0 = 0xff00,
72 }, {
73 .type = CX23885_VMUX_DEBUG,
74 .vmux = 0,
75 .gpio0 = 0xff01,
76 }, {
77 .type = CX23885_VMUX_COMPOSITE1,
78 .vmux = 1,
79 .gpio0 = 0xff02,
80 }, {
81 .type = CX23885_VMUX_SVIDEO,
82 .vmux = 2,
83 .gpio0 = 0xff02,
84 } },
85 },
86 [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
87 .name = "Hauppauge WinTV-HVR1800",
88 .porta = CX23885_ANALOG_VIDEO,
89 .portb = CX23885_MPEG_ENCODER,
90 .portc = CX23885_MPEG_DVB,
91 .tuner_type = TUNER_PHILIPS_TDA8290,
92 .tuner_addr = 0x42,
93 .input = {{
94 .type = CX23885_VMUX_TELEVISION,
95 .vmux = CX25840_VIN7_CH3 |
96 CX25840_VIN5_CH2 |
97 CX25840_VIN2_CH1,
98 .gpio0 = 0,
99 }, {
100 .type = CX23885_VMUX_COMPOSITE1,
101 .vmux = CX25840_VIN7_CH3 |
102 CX25840_VIN4_CH2 |
103 CX25840_VIN6_CH1,
104 .gpio0 = 0,
105 }, {
106 .type = CX23885_VMUX_SVIDEO,
107 .vmux = CX25840_VIN7_CH3 |
108 CX25840_VIN4_CH2 |
109 CX25840_VIN8_CH1 |
110 CX25840_SVIDEO_ON,
111 .gpio0 = 0,
112 } },
113 },
114 [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
115 .name = "Hauppauge WinTV-HVR1250",
116 .portc = CX23885_MPEG_DVB,
117 .input = {{
118 .type = CX23885_VMUX_TELEVISION,
119 .vmux = 0,
120 .gpio0 = 0xff00,
121 }, {
122 .type = CX23885_VMUX_DEBUG,
123 .vmux = 0,
124 .gpio0 = 0xff01,
125 }, {
126 .type = CX23885_VMUX_COMPOSITE1,
127 .vmux = 1,
128 .gpio0 = 0xff02,
129 }, {
130 .type = CX23885_VMUX_SVIDEO,
131 .vmux = 2,
132 .gpio0 = 0xff02,
133 } },
134 },
135 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
136 .name = "DViCO FusionHDTV5 Express",
137 .portb = CX23885_MPEG_DVB,
138 },
139 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
140 .name = "Hauppauge WinTV-HVR1500Q",
141 .portc = CX23885_MPEG_DVB,
142 },
143 [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
144 .name = "Hauppauge WinTV-HVR1500",
145 .portc = CX23885_MPEG_DVB,
146 },
147 [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
148 .name = "Hauppauge WinTV-HVR1200",
149 .portc = CX23885_MPEG_DVB,
150 },
151 [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
152 .name = "Hauppauge WinTV-HVR1700",
153 .portc = CX23885_MPEG_DVB,
154 },
155 [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
156 .name = "Hauppauge WinTV-HVR1400",
157 .portc = CX23885_MPEG_DVB,
158 },
159 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
160 .name = "DViCO FusionHDTV7 Dual Express",
161 .portb = CX23885_MPEG_DVB,
162 .portc = CX23885_MPEG_DVB,
163 },
164 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
165 .name = "DViCO FusionHDTV DVB-T Dual Express",
166 .portb = CX23885_MPEG_DVB,
167 .portc = CX23885_MPEG_DVB,
168 },
169 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
170 .name = "Leadtek Winfast PxDVR3200 H",
171 .portc = CX23885_MPEG_DVB,
172 },
173 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
174 .name = "Compro VideoMate E650F",
175 .portc = CX23885_MPEG_DVB,
176 },
177 [CX23885_BOARD_TBS_6920] = {
178 .name = "TurboSight TBS 6920",
179 .portb = CX23885_MPEG_DVB,
180 },
181 [CX23885_BOARD_TEVII_S470] = {
182 .name = "TeVii S470",
183 .portb = CX23885_MPEG_DVB,
184 },
185 [CX23885_BOARD_DVBWORLD_2005] = {
186 .name = "DVBWorld DVB-S2 2005",
187 .portb = CX23885_MPEG_DVB,
188 },
189 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
190 .cimax = 1,
191 .name = "NetUP Dual DVB-S2 CI",
192 .portb = CX23885_MPEG_DVB,
193 .portc = CX23885_MPEG_DVB,
194 },
195 [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
196 .name = "Hauppauge WinTV-HVR1270",
197 .portc = CX23885_MPEG_DVB,
198 },
199 [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
200 .name = "Hauppauge WinTV-HVR1275",
201 .portc = CX23885_MPEG_DVB,
202 },
203 [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
204 .name = "Hauppauge WinTV-HVR1255",
205 .portc = CX23885_MPEG_DVB,
206 },
207 [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
208 .name = "Hauppauge WinTV-HVR1210",
209 .portc = CX23885_MPEG_DVB,
210 },
211 [CX23885_BOARD_MYGICA_X8506] = {
212 .name = "Mygica X8506 DMB-TH",
213 .tuner_type = TUNER_XC5000,
214 .tuner_addr = 0x61,
215 .porta = CX23885_ANALOG_VIDEO,
216 .portb = CX23885_MPEG_DVB,
217 .input = {
218 {
219 .type = CX23885_VMUX_TELEVISION,
220 .vmux = CX25840_COMPOSITE2,
221 },
222 {
223 .type = CX23885_VMUX_COMPOSITE1,
224 .vmux = CX25840_COMPOSITE8,
225 },
226 {
227 .type = CX23885_VMUX_SVIDEO,
228 .vmux = CX25840_SVIDEO_LUMA3 |
229 CX25840_SVIDEO_CHROMA4,
230 },
231 {
232 .type = CX23885_VMUX_COMPONENT,
233 .vmux = CX25840_COMPONENT_ON |
234 CX25840_VIN1_CH1 |
235 CX25840_VIN6_CH2 |
236 CX25840_VIN7_CH3,
237 },
238 },
239 },
240 [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
241 .name = "Magic-Pro ProHDTV Extreme 2",
242 .tuner_type = TUNER_XC5000,
243 .tuner_addr = 0x61,
244 .porta = CX23885_ANALOG_VIDEO,
245 .portb = CX23885_MPEG_DVB,
246 .input = {
247 {
248 .type = CX23885_VMUX_TELEVISION,
249 .vmux = CX25840_COMPOSITE2,
250 },
251 {
252 .type = CX23885_VMUX_COMPOSITE1,
253 .vmux = CX25840_COMPOSITE8,
254 },
255 {
256 .type = CX23885_VMUX_SVIDEO,
257 .vmux = CX25840_SVIDEO_LUMA3 |
258 CX25840_SVIDEO_CHROMA4,
259 },
260 {
261 .type = CX23885_VMUX_COMPONENT,
262 .vmux = CX25840_COMPONENT_ON |
263 CX25840_VIN1_CH1 |
264 CX25840_VIN6_CH2 |
265 CX25840_VIN7_CH3,
266 },
267 },
268 },
269 [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
270 .name = "Hauppauge WinTV-HVR1850",
271 .portb = CX23885_MPEG_ENCODER,
272 .portc = CX23885_MPEG_DVB,
273 },
274 [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
275 .name = "Compro VideoMate E800",
276 .portc = CX23885_MPEG_DVB,
277 },
278 [CX23885_BOARD_HAUPPAUGE_HVR1290] = {
279 .name = "Hauppauge WinTV-HVR1290",
280 .portc = CX23885_MPEG_DVB,
281 },
282 [CX23885_BOARD_MYGICA_X8558PRO] = {
283 .name = "Mygica X8558 PRO DMB-TH",
284 .portb = CX23885_MPEG_DVB,
285 .portc = CX23885_MPEG_DVB,
286 },
287 [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
288 .name = "LEADTEK WinFast PxTV1200",
289 .porta = CX23885_ANALOG_VIDEO,
290 .tuner_type = TUNER_XC2028,
291 .tuner_addr = 0x61,
292 .input = {{
293 .type = CX23885_VMUX_TELEVISION,
294 .vmux = CX25840_VIN2_CH1 |
295 CX25840_VIN5_CH2 |
296 CX25840_NONE0_CH3,
297 }, {
298 .type = CX23885_VMUX_COMPOSITE1,
299 .vmux = CX25840_COMPOSITE1,
300 }, {
301 .type = CX23885_VMUX_SVIDEO,
302 .vmux = CX25840_SVIDEO_LUMA3 |
303 CX25840_SVIDEO_CHROMA4,
304 }, {
305 .type = CX23885_VMUX_COMPONENT,
306 .vmux = CX25840_VIN7_CH1 |
307 CX25840_VIN6_CH2 |
308 CX25840_VIN8_CH3 |
309 CX25840_COMPONENT_ON,
310 } },
311 },
312 [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = {
313 .name = "GoTView X5 3D Hybrid",
314 .tuner_type = TUNER_XC5000,
315 .tuner_addr = 0x64,
316 .porta = CX23885_ANALOG_VIDEO,
317 .portb = CX23885_MPEG_DVB,
318 .input = {{
319 .type = CX23885_VMUX_TELEVISION,
320 .vmux = CX25840_VIN2_CH1 |
321 CX25840_VIN5_CH2,
322 .gpio0 = 0x02,
323 }, {
324 .type = CX23885_VMUX_COMPOSITE1,
325 .vmux = CX23885_VMUX_COMPOSITE1,
326 }, {
327 .type = CX23885_VMUX_SVIDEO,
328 .vmux = CX25840_SVIDEO_LUMA3 |
329 CX25840_SVIDEO_CHROMA4,
330 } },
331 },
332};
333const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
334
335
336
337
338struct cx23885_subid cx23885_subids[] = {
339 {
340 .subvendor = 0x0070,
341 .subdevice = 0x3400,
342 .card = CX23885_BOARD_UNKNOWN,
343 }, {
344 .subvendor = 0x0070,
345 .subdevice = 0x7600,
346 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
347 }, {
348 .subvendor = 0x0070,
349 .subdevice = 0x7800,
350 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
351 }, {
352 .subvendor = 0x0070,
353 .subdevice = 0x7801,
354 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
355 }, {
356 .subvendor = 0x0070,
357 .subdevice = 0x7809,
358 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
359 }, {
360 .subvendor = 0x0070,
361 .subdevice = 0x7911,
362 .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
363 }, {
364 .subvendor = 0x18ac,
365 .subdevice = 0xd500,
366 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
367 }, {
368 .subvendor = 0x0070,
369 .subdevice = 0x7790,
370 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
371 }, {
372 .subvendor = 0x0070,
373 .subdevice = 0x7797,
374 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
375 }, {
376 .subvendor = 0x0070,
377 .subdevice = 0x7710,
378 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
379 }, {
380 .subvendor = 0x0070,
381 .subdevice = 0x7717,
382 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
383 }, {
384 .subvendor = 0x0070,
385 .subdevice = 0x71d1,
386 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
387 }, {
388 .subvendor = 0x0070,
389 .subdevice = 0x71d3,
390 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
391 }, {
392 .subvendor = 0x0070,
393 .subdevice = 0x8101,
394 .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
395 }, {
396 .subvendor = 0x0070,
397 .subdevice = 0x8010,
398 .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
399 }, {
400 .subvendor = 0x18ac,
401 .subdevice = 0xd618,
402 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
403 }, {
404 .subvendor = 0x18ac,
405 .subdevice = 0xdb78,
406 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
407 }, {
408 .subvendor = 0x107d,
409 .subdevice = 0x6681,
410 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
411 }, {
412 .subvendor = 0x185b,
413 .subdevice = 0xe800,
414 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
415 }, {
416 .subvendor = 0x6920,
417 .subdevice = 0x8888,
418 .card = CX23885_BOARD_TBS_6920,
419 }, {
420 .subvendor = 0xd470,
421 .subdevice = 0x9022,
422 .card = CX23885_BOARD_TEVII_S470,
423 }, {
424 .subvendor = 0x0001,
425 .subdevice = 0x2005,
426 .card = CX23885_BOARD_DVBWORLD_2005,
427 }, {
428 .subvendor = 0x1b55,
429 .subdevice = 0x2a2c,
430 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
431 }, {
432 .subvendor = 0x0070,
433 .subdevice = 0x2211,
434 .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
435 }, {
436 .subvendor = 0x0070,
437 .subdevice = 0x2215,
438 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
439 }, {
440 .subvendor = 0x0070,
441 .subdevice = 0x221d,
442 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
443 }, {
444 .subvendor = 0x0070,
445 .subdevice = 0x2251,
446 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
447 }, {
448 .subvendor = 0x0070,
449 .subdevice = 0x2259,
450 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
451 }, {
452 .subvendor = 0x0070,
453 .subdevice = 0x2291,
454 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
455 }, {
456 .subvendor = 0x0070,
457 .subdevice = 0x2295,
458 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
459 }, {
460 .subvendor = 0x0070,
461 .subdevice = 0x2299,
462 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
463 }, {
464 .subvendor = 0x0070,
465 .subdevice = 0x229d,
466 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
467 }, {
468 .subvendor = 0x0070,
469 .subdevice = 0x22f0,
470 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
471 }, {
472 .subvendor = 0x0070,
473 .subdevice = 0x22f1,
474 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
475 }, {
476 .subvendor = 0x0070,
477 .subdevice = 0x22f2,
478 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
479 }, {
480 .subvendor = 0x0070,
481 .subdevice = 0x22f3,
482 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
483 }, {
484 .subvendor = 0x0070,
485 .subdevice = 0x22f4,
486 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
487 }, {
488 .subvendor = 0x0070,
489 .subdevice = 0x22f5,
490 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
491 }, {
492 .subvendor = 0x14f1,
493 .subdevice = 0x8651,
494 .card = CX23885_BOARD_MYGICA_X8506,
495 }, {
496 .subvendor = 0x14f1,
497 .subdevice = 0x8657,
498 .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
499 }, {
500 .subvendor = 0x0070,
501 .subdevice = 0x8541,
502 .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
503 }, {
504 .subvendor = 0x1858,
505 .subdevice = 0xe800,
506 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
507 }, {
508 .subvendor = 0x0070,
509 .subdevice = 0x8551,
510 .card = CX23885_BOARD_HAUPPAUGE_HVR1290,
511 }, {
512 .subvendor = 0x14f1,
513 .subdevice = 0x8578,
514 .card = CX23885_BOARD_MYGICA_X8558PRO,
515 }, {
516 .subvendor = 0x107d,
517 .subdevice = 0x6f22,
518 .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
519 }, {
520 .subvendor = 0x5654,
521 .subdevice = 0x2390,
522 .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID,
523 },
524};
525const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
526
527void cx23885_card_list(struct cx23885_dev *dev)
528{
529 int i;
530
531 if (0 == dev->pci->subsystem_vendor &&
532 0 == dev->pci->subsystem_device) {
533 printk(KERN_INFO
534 "%s: Board has no valid PCIe Subsystem ID and can't\n"
535 "%s: be autodetected. Pass card=<n> insmod option\n"
536 "%s: to workaround that. Redirect complaints to the\n"
537 "%s: vendor of the TV card. Best regards,\n"
538 "%s: -- tux\n",
539 dev->name, dev->name, dev->name, dev->name, dev->name);
540 } else {
541 printk(KERN_INFO
542 "%s: Your board isn't known (yet) to the driver.\n"
543 "%s: Try to pick one of the existing card configs via\n"
544 "%s: card=<n> insmod option. Updating to the latest\n"
545 "%s: version might help as well.\n",
546 dev->name, dev->name, dev->name, dev->name);
547 }
548 printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
549 dev->name);
550 for (i = 0; i < cx23885_bcount; i++)
551 printk(KERN_INFO "%s: card=%d -> %s\n",
552 dev->name, i, cx23885_boards[i].name);
553}
554
555static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
556{
557 struct tveeprom tv;
558
559 tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
560 eeprom_data);
561
562
563 switch (tv.model) {
564 case 22001:
565
566
567 case 22009:
568
569
570 case 22011:
571
572
573 case 22019:
574
575
576 case 22021:
577
578
579 case 22029:
580
581
582 case 22101:
583
584
585 case 22109:
586
587
588 case 22111:
589
590
591 case 22119:
592
593
594 case 22121:
595
596
597 case 22129:
598
599
600 case 71009:
601
602
603 case 71359:
604
605
606 case 71439:
607
608
609 case 71449:
610
611
612 case 71939:
613
614
615 case 71949:
616
617
618 case 71959:
619
620
621 case 71979:
622
623
624 case 71999:
625
626
627 case 76601:
628
629
630 case 77001:
631
632
633 case 77011:
634
635
636 case 77041:
637
638
639 case 77051:
640
641
642 case 78011:
643
644
645 case 78501:
646
647
648 case 78521:
649
650
651 case 78531:
652
653
654 case 78631:
655
656
657 case 79001:
658
659
660 case 79101:
661
662
663 case 79501:
664
665
666 case 79561:
667
668
669 case 79571:
670
671
672 case 79671:
673
674
675 case 80019:
676
677
678 case 81509:
679
680
681 case 81519:
682
683
684 break;
685 case 85021:
686
687
688 break;
689 case 85721:
690
691
692 break;
693 default:
694 printk(KERN_WARNING "%s: warning: "
695 "unknown hauppauge model #%d\n",
696 dev->name, tv.model);
697 break;
698 }
699
700 printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
701 dev->name, tv.model);
702}
703
704int cx23885_tuner_callback(void *priv, int component, int command, int arg)
705{
706 struct cx23885_tsport *port = priv;
707 struct cx23885_dev *dev = port->dev;
708 u32 bitmask = 0;
709
710 if (command == XC2028_RESET_CLK)
711 return 0;
712
713 if (command != 0) {
714 printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
715 __func__, command);
716 return -EINVAL;
717 }
718
719 switch (dev->board) {
720 case CX23885_BOARD_HAUPPAUGE_HVR1400:
721 case CX23885_BOARD_HAUPPAUGE_HVR1500:
722 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
723 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
724 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
725 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
726 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
727
728 bitmask = 0x04;
729 break;
730 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
731 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
732
733
734 if (port->nr == 1)
735 bitmask = 0x01;
736 else if (port->nr == 2)
737 bitmask = 0x04;
738 break;
739 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
740
741 bitmask = 0x02;
742 break;
743 }
744
745 if (bitmask) {
746
747 cx_clear(GP0_IO, bitmask);
748 mdelay(200);
749 cx_set(GP0_IO, bitmask);
750 }
751
752 return 0;
753}
754
755void cx23885_gpio_setup(struct cx23885_dev *dev)
756{
757 switch (dev->board) {
758 case CX23885_BOARD_HAUPPAUGE_HVR1250:
759
760 cx_set(GP0_IO, 0x00010001);
761 break;
762 case CX23885_BOARD_HAUPPAUGE_HVR1500:
763
764
765
766
767 cx_set(GP0_IO, 0x00050000);
768 cx_clear(GP0_IO, 0x00000005);
769 msleep(5);
770
771
772 cx_set(GP0_IO, 0x00050005);
773 break;
774 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
775
776
777 cx_set(GP0_IO, 0x00050005);
778 break;
779 case CX23885_BOARD_HAUPPAUGE_HVR1800:
780
781
782
783
784
785
786
787
788
789
790
791 mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
792
793
794 mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
795 mdelay(100);
796
797
798 mc417_gpio_set(dev, GPIO_15 | GPIO_14);
799 mdelay(100);
800
801
802 cx23885_gpio_enable(dev, GPIO_2, 1);
803 cx23885_gpio_set(dev, GPIO_2);
804 mdelay(20);
805 cx23885_gpio_clear(dev, GPIO_2);
806 mdelay(20);
807 cx23885_gpio_set(dev, GPIO_2);
808 mdelay(20);
809 break;
810 case CX23885_BOARD_HAUPPAUGE_HVR1200:
811
812
813
814
815 cx_set(GP0_IO, 0x00050000);
816 mdelay(20);
817 cx_clear(GP0_IO, 0x00000005);
818 mdelay(20);
819 cx_set(GP0_IO, 0x00050005);
820 break;
821 case CX23885_BOARD_HAUPPAUGE_HVR1700:
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836 cx_set(GP0_IO, 0x00050000);
837 mdelay(20);
838 cx_clear(GP0_IO, 0x00000005);
839 mdelay(20);
840 cx_set(GP0_IO, 0x00050005);
841 break;
842 case CX23885_BOARD_HAUPPAUGE_HVR1400:
843
844
845
846
847
848 cx_set(GP0_IO, 0x00050000);
849 mdelay(20);
850 cx_clear(GP0_IO, 0x00000005);
851 mdelay(20);
852 cx_set(GP0_IO, 0x00050005);
853 break;
854 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
855
856
857
858
859
860
861 cx_set(GP0_IO, 0x000f0000);
862 mdelay(20);
863 cx_clear(GP0_IO, 0x0000000f);
864 mdelay(20);
865 cx_set(GP0_IO, 0x000f000f);
866 break;
867 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
868
869
870
871
872
873
874 cx_set(GP0_IO, 0x000f0000);
875 mdelay(20);
876 cx_clear(GP0_IO, 0x0000000f);
877 mdelay(20);
878 cx_set(GP0_IO, 0x000f000f);
879 break;
880 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
881 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
882 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
883 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
884
885
886
887
888
889
890 cx_set(GP0_IO, 0x00040000);
891 mdelay(20);
892 cx_clear(GP0_IO, 0x00000004);
893 mdelay(20);
894 cx_set(GP0_IO, 0x00040004);
895 break;
896 case CX23885_BOARD_TBS_6920:
897 cx_write(MC417_CTL, 0x00000036);
898 cx_write(MC417_OEN, 0x00001000);
899 cx_set(MC417_RWD, 0x00000002);
900 mdelay(200);
901 cx_clear(MC417_RWD, 0x00000800);
902 mdelay(200);
903 cx_set(MC417_RWD, 0x00000800);
904 mdelay(200);
905 break;
906 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
907
908
909
910
911
912
913
914
915
916
917
918
919 cx_set(GP0_IO, 0x00040000);
920
921 cx_clear(GP0_IO, 0x00030004);
922 mdelay(100);
923 cx_set(GP0_IO, 0x00040004);
924 cx_write(MC417_CTL, 0x00000037);
925
926 cx_write(MC417_OEN, 0x00001000);
927
928 cx_write(MC417_RWD, 0x0000c300);
929
930 cx_write(GPIO_ISM, 0x00000000);
931 break;
932 case CX23885_BOARD_HAUPPAUGE_HVR1270:
933 case CX23885_BOARD_HAUPPAUGE_HVR1275:
934 case CX23885_BOARD_HAUPPAUGE_HVR1255:
935 case CX23885_BOARD_HAUPPAUGE_HVR1210:
936
937
938
939
940
941 cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
942 cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
943 cx23885_gpio_clear(dev, GPIO_9);
944 mdelay(20);
945 cx23885_gpio_set(dev, GPIO_9);
946 break;
947 case CX23885_BOARD_MYGICA_X8506:
948 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
949
950
951
952 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
953 cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
954 mdelay(100);
955 cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
956 mdelay(100);
957 break;
958 case CX23885_BOARD_MYGICA_X8558PRO:
959
960
961 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
962 cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
963 mdelay(100);
964 cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
965 mdelay(100);
966 break;
967 case CX23885_BOARD_HAUPPAUGE_HVR1850:
968 case CX23885_BOARD_HAUPPAUGE_HVR1290:
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985 mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
986
987
988 mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
989 mdelay(100);
990
991
992 mc417_gpio_set(dev, GPIO_14);
993 mdelay(100);
994
995
996
997 break;
998 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
999 cx_set(GP0_IO, 0x00010001);
1000 break;
1001 }
1002}
1003
1004int cx23885_ir_init(struct cx23885_dev *dev)
1005{
1006 static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = {
1007 {
1008 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1009 .pin = CX23885_PIN_IR_RX_GPIO19,
1010 .function = CX23885_PAD_IR_RX,
1011 .value = 0,
1012 .strength = CX25840_PIN_DRIVE_MEDIUM,
1013 }, {
1014 .flags = V4L2_SUBDEV_IO_PIN_OUTPUT,
1015 .pin = CX23885_PIN_IR_TX_GPIO20,
1016 .function = CX23885_PAD_IR_TX,
1017 .value = 0,
1018 .strength = CX25840_PIN_DRIVE_MEDIUM,
1019 }
1020 };
1021 const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg);
1022
1023 static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = {
1024 {
1025 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1026 .pin = CX23885_PIN_IR_RX_GPIO19,
1027 .function = CX23885_PAD_IR_RX,
1028 .value = 0,
1029 .strength = CX25840_PIN_DRIVE_MEDIUM,
1030 }
1031 };
1032 const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg);
1033
1034 struct v4l2_subdev_ir_parameters params;
1035 int ret = 0;
1036 switch (dev->board) {
1037 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1038 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1039 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1040 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1041 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1042 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1043 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1044 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1045 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1046
1047 break;
1048 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1049 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1050 ret = cx23888_ir_probe(dev);
1051 if (ret)
1052 break;
1053 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
1054 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1055 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
1056
1057
1058
1059
1060 v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, ¶ms);
1061 params.enable = false;
1062 params.shutdown = false;
1063 params.invert_level = true;
1064 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, ¶ms);
1065 params.shutdown = true;
1066 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, ¶ms);
1067 break;
1068 case CX23885_BOARD_TEVII_S470:
1069 if (!enable_885_ir)
1070 break;
1071 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1072 if (dev->sd_ir == NULL) {
1073 ret = -ENODEV;
1074 break;
1075 }
1076 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1077 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
1078 break;
1079 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1080 if (!enable_885_ir)
1081 break;
1082 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1083 if (dev->sd_ir == NULL) {
1084 ret = -ENODEV;
1085 break;
1086 }
1087 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1088 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
1089 break;
1090 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1091 request_module("ir-kbd-i2c");
1092 break;
1093 }
1094
1095 return ret;
1096}
1097
1098void cx23885_ir_fini(struct cx23885_dev *dev)
1099{
1100 switch (dev->board) {
1101 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1102 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1103 cx23885_irq_remove(dev, PCI_MSK_IR);
1104 cx23888_ir_remove(dev);
1105 dev->sd_ir = NULL;
1106 break;
1107 case CX23885_BOARD_TEVII_S470:
1108 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1109 cx23885_irq_remove(dev, PCI_MSK_AV_CORE);
1110
1111 dev->sd_ir = NULL;
1112 break;
1113 }
1114}
1115
1116void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
1117{
1118 switch (dev->board) {
1119 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1120 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1121 if (dev->sd_ir)
1122 cx23885_irq_add_enable(dev, PCI_MSK_IR);
1123 break;
1124 case CX23885_BOARD_TEVII_S470:
1125 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1126 if (dev->sd_ir)
1127 cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE);
1128 break;
1129 }
1130}
1131
1132void cx23885_card_setup(struct cx23885_dev *dev)
1133{
1134 struct cx23885_tsport *ts1 = &dev->ts1;
1135 struct cx23885_tsport *ts2 = &dev->ts2;
1136
1137 static u8 eeprom[256];
1138
1139 if (dev->i2c_bus[0].i2c_rc == 0) {
1140 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
1141 tveeprom_read(&dev->i2c_bus[0].i2c_client,
1142 eeprom, sizeof(eeprom));
1143 }
1144
1145 switch (dev->board) {
1146 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1147 if (dev->i2c_bus[0].i2c_rc == 0) {
1148 if (eeprom[0x80] != 0x84)
1149 hauppauge_eeprom(dev, eeprom+0xc0);
1150 else
1151 hauppauge_eeprom(dev, eeprom+0x80);
1152 }
1153 break;
1154 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1155 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1156 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1157 if (dev->i2c_bus[0].i2c_rc == 0)
1158 hauppauge_eeprom(dev, eeprom+0x80);
1159 break;
1160 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1161 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1162 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1163 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1164 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1165 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1166 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1167 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1168 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1169 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1170 if (dev->i2c_bus[0].i2c_rc == 0)
1171 hauppauge_eeprom(dev, eeprom+0xc0);
1172 break;
1173 }
1174
1175 switch (dev->board) {
1176 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1177 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1178 ts2->gen_ctrl_val = 0xc;
1179 ts2->ts_clk_en_val = 0x1;
1180 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1181
1182 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
1183 ts1->gen_ctrl_val = 0xc;
1184 ts1->ts_clk_en_val = 0x1;
1185 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1186 break;
1187 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1188
1189
1190 ts1->gen_ctrl_val = 0x10e;
1191 ts1->ts_clk_en_val = 0x1;
1192 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1193
1194
1195 ts1->vld_misc_val = 0x2000;
1196 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
1197
1198
1199 ts2->gen_ctrl_val = 0xc;
1200 ts2->ts_clk_en_val = 0x1;
1201 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1202 break;
1203 case CX23885_BOARD_TBS_6920:
1204 ts1->gen_ctrl_val = 0x4;
1205 ts1->ts_clk_en_val = 0x1;
1206 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1207 break;
1208 case CX23885_BOARD_TEVII_S470:
1209 case CX23885_BOARD_DVBWORLD_2005:
1210 ts1->gen_ctrl_val = 0x5;
1211 ts1->ts_clk_en_val = 0x1;
1212 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1213 break;
1214 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1215 ts1->gen_ctrl_val = 0xc;
1216 ts1->ts_clk_en_val = 0x1;
1217 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1218 ts2->gen_ctrl_val = 0xc;
1219 ts2->ts_clk_en_val = 0x1;
1220 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1221 break;
1222 case CX23885_BOARD_MYGICA_X8506:
1223 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1224 ts1->gen_ctrl_val = 0x5;
1225 ts1->ts_clk_en_val = 0x1;
1226 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1227 break;
1228 case CX23885_BOARD_MYGICA_X8558PRO:
1229 ts1->gen_ctrl_val = 0x5;
1230 ts1->ts_clk_en_val = 0x1;
1231 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1232 ts2->gen_ctrl_val = 0xc;
1233 ts2->ts_clk_en_val = 0x1;
1234 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1235 break;
1236 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1237 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1238 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1239 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1240 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1241 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1242 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1243 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1244 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1245 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1246 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1247 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1248 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1249 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1250 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1251 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1252 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1253 default:
1254 ts2->gen_ctrl_val = 0xc;
1255 ts2->ts_clk_en_val = 0x1;
1256 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1257 }
1258
1259
1260
1261
1262 switch (dev->board) {
1263 case CX23885_BOARD_TEVII_S470:
1264 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1265
1266 if (!enable_885_ir)
1267 break;
1268 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1269 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1270 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1271 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1272 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1273 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1274 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1275 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1276 case CX23885_BOARD_MYGICA_X8506:
1277 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1278 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1279 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
1280 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1281 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
1282 &dev->i2c_bus[2].i2c_adap,
1283 "cx25840", 0x88 >> 1, NULL);
1284 if (dev->sd_cx25840) {
1285 dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE;
1286 v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
1287 }
1288 break;
1289 }
1290
1291
1292 switch (dev->board) {
1293 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1294 netup_initialize(dev);
1295 break;
1296 }
1297}
1298
1299
1300
