linux/drivers/media/video/pvrusb2/pvrusb2-hdw.c
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   1/*
   2 *
   3 *
   4 *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5 *
   6 *  This program is free software; you can redistribute it and/or modify
   7 *  it under the terms of the GNU General Public License as published by
   8 *  the Free Software Foundation; either version 2 of the License
   9 *
  10 *  This program is distributed in the hope that it will be useful,
  11 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 *  GNU General Public License for more details.
  14 *
  15 *  You should have received a copy of the GNU General Public License
  16 *  along with this program; if not, write to the Free Software
  17 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18 *
  19 */
  20
  21#include <linux/errno.h>
  22#include <linux/string.h>
  23#include <linux/slab.h>
  24#include <linux/firmware.h>
  25#include <linux/videodev2.h>
  26#include <media/v4l2-common.h>
  27#include <media/tuner.h>
  28#include "pvrusb2.h"
  29#include "pvrusb2-std.h"
  30#include "pvrusb2-util.h"
  31#include "pvrusb2-hdw.h"
  32#include "pvrusb2-i2c-core.h"
  33#include "pvrusb2-eeprom.h"
  34#include "pvrusb2-hdw-internal.h"
  35#include "pvrusb2-encoder.h"
  36#include "pvrusb2-debug.h"
  37#include "pvrusb2-fx2-cmd.h"
  38#include "pvrusb2-wm8775.h"
  39#include "pvrusb2-video-v4l.h"
  40#include "pvrusb2-cx2584x-v4l.h"
  41#include "pvrusb2-cs53l32a.h"
  42#include "pvrusb2-audio.h"
  43
  44#define TV_MIN_FREQ     55250000L
  45#define TV_MAX_FREQ    850000000L
  46
  47/* This defines a minimum interval that the decoder must remain quiet
  48   before we are allowed to start it running. */
  49#define TIME_MSEC_DECODER_WAIT 50
  50
  51/* This defines a minimum interval that the decoder must be allowed to run
  52   before we can safely begin using its streaming output. */
  53#define TIME_MSEC_DECODER_STABILIZATION_WAIT 300
  54
  55/* This defines a minimum interval that the encoder must remain quiet
  56   before we are allowed to configure it. */
  57#define TIME_MSEC_ENCODER_WAIT 50
  58
  59/* This defines the minimum interval that the encoder must successfully run
  60   before we consider that the encoder has run at least once since its
  61   firmware has been loaded.  This measurement is in important for cases
  62   where we can't do something until we know that the encoder has been run
  63   at least once. */
  64#define TIME_MSEC_ENCODER_OK 250
  65
  66static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  67static DEFINE_MUTEX(pvr2_unit_mtx);
  68
  69static int ctlchg;
  70static int procreload;
  71static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  72static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  73static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  74static int init_pause_msec;
  75
  76module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  77MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  78module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  79MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  80module_param(procreload, int, S_IRUGO|S_IWUSR);
  81MODULE_PARM_DESC(procreload,
  82                 "Attempt init failure recovery with firmware reload");
  83module_param_array(tuner,    int, NULL, 0444);
  84MODULE_PARM_DESC(tuner,"specify installed tuner type");
  85module_param_array(video_std,    int, NULL, 0444);
  86MODULE_PARM_DESC(video_std,"specify initial video standard");
  87module_param_array(tolerance,    int, NULL, 0444);
  88MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  89
  90/* US Broadcast channel 3 (61.25 MHz), to help with testing */
  91static int default_tv_freq    = 61250000L;
  92/* 104.3 MHz, a usable FM station for my area */
  93static int default_radio_freq = 104300000L;
  94
  95module_param_named(tv_freq, default_tv_freq, int, 0444);
  96MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  97module_param_named(radio_freq, default_radio_freq, int, 0444);
  98MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
  99
 100#define PVR2_CTL_WRITE_ENDPOINT  0x01
 101#define PVR2_CTL_READ_ENDPOINT   0x81
 102
 103#define PVR2_GPIO_IN 0x9008
 104#define PVR2_GPIO_OUT 0x900c
 105#define PVR2_GPIO_DIR 0x9020
 106
 107#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 108
 109#define PVR2_FIRMWARE_ENDPOINT   0x02
 110
 111/* size of a firmware chunk */
 112#define FIRMWARE_CHUNK_SIZE 0x2000
 113
 114typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
 115                                        struct v4l2_subdev *);
 116
 117static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
 118        [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
 119        [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
 120        [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
 121        [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
 122        [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
 123};
 124
 125static const char *module_names[] = {
 126        [PVR2_CLIENT_ID_MSP3400] = "msp3400",
 127        [PVR2_CLIENT_ID_CX25840] = "cx25840",
 128        [PVR2_CLIENT_ID_SAA7115] = "saa7115",
 129        [PVR2_CLIENT_ID_TUNER] = "tuner",
 130        [PVR2_CLIENT_ID_DEMOD] = "tuner",
 131        [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
 132        [PVR2_CLIENT_ID_WM8775] = "wm8775",
 133};
 134
 135
 136static const unsigned char *module_i2c_addresses[] = {
 137        [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
 138        [PVR2_CLIENT_ID_DEMOD] = "\x43",
 139        [PVR2_CLIENT_ID_MSP3400] = "\x40",
 140        [PVR2_CLIENT_ID_SAA7115] = "\x21",
 141        [PVR2_CLIENT_ID_WM8775] = "\x1b",
 142        [PVR2_CLIENT_ID_CX25840] = "\x44",
 143        [PVR2_CLIENT_ID_CS53L32A] = "\x11",
 144};
 145
 146
 147static const char *ir_scheme_names[] = {
 148        [PVR2_IR_SCHEME_NONE] = "none",
 149        [PVR2_IR_SCHEME_29XXX] = "29xxx",
 150        [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
 151        [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
 152        [PVR2_IR_SCHEME_ZILOG] = "Zilog",
 153};
 154
 155
 156/* Define the list of additional controls we'll dynamically construct based
 157   on query of the cx2341x module. */
 158struct pvr2_mpeg_ids {
 159        const char *strid;
 160        int id;
 161};
 162static const struct pvr2_mpeg_ids mpeg_ids[] = {
 163        {
 164                .strid = "audio_layer",
 165                .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 166        },{
 167                .strid = "audio_bitrate",
 168                .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 169        },{
 170                /* Already using audio_mode elsewhere :-( */
 171                .strid = "mpeg_audio_mode",
 172                .id = V4L2_CID_MPEG_AUDIO_MODE,
 173        },{
 174                .strid = "mpeg_audio_mode_extension",
 175                .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 176        },{
 177                .strid = "audio_emphasis",
 178                .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 179        },{
 180                .strid = "audio_crc",
 181                .id = V4L2_CID_MPEG_AUDIO_CRC,
 182        },{
 183                .strid = "video_aspect",
 184                .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 185        },{
 186                .strid = "video_b_frames",
 187                .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 188        },{
 189                .strid = "video_gop_size",
 190                .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 191        },{
 192                .strid = "video_gop_closure",
 193                .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 194        },{
 195                .strid = "video_bitrate_mode",
 196                .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 197        },{
 198                .strid = "video_bitrate",
 199                .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 200        },{
 201                .strid = "video_bitrate_peak",
 202                .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 203        },{
 204                .strid = "video_temporal_decimation",
 205                .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 206        },{
 207                .strid = "stream_type",
 208                .id = V4L2_CID_MPEG_STREAM_TYPE,
 209        },{
 210                .strid = "video_spatial_filter_mode",
 211                .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 212        },{
 213                .strid = "video_spatial_filter",
 214                .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 215        },{
 216                .strid = "video_luma_spatial_filter_type",
 217                .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 218        },{
 219                .strid = "video_chroma_spatial_filter_type",
 220                .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 221        },{
 222                .strid = "video_temporal_filter_mode",
 223                .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 224        },{
 225                .strid = "video_temporal_filter",
 226                .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 227        },{
 228                .strid = "video_median_filter_type",
 229                .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 230        },{
 231                .strid = "video_luma_median_filter_top",
 232                .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 233        },{
 234                .strid = "video_luma_median_filter_bottom",
 235                .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 236        },{
 237                .strid = "video_chroma_median_filter_top",
 238                .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 239        },{
 240                .strid = "video_chroma_median_filter_bottom",
 241                .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 242        }
 243};
 244#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 245
 246
 247static const char *control_values_srate[] = {
 248        [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 249        [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 250        [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 251};
 252
 253
 254
 255static const char *control_values_input[] = {
 256        [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 257        [PVR2_CVAL_INPUT_DTV]       = "dtv",
 258        [PVR2_CVAL_INPUT_RADIO]     = "radio",
 259        [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 260        [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 261};
 262
 263
 264static const char *control_values_audiomode[] = {
 265        [V4L2_TUNER_MODE_MONO]   = "Mono",
 266        [V4L2_TUNER_MODE_STEREO] = "Stereo",
 267        [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 268        [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 269        [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 270};
 271
 272
 273static const char *control_values_hsm[] = {
 274        [PVR2_CVAL_HSM_FAIL] = "Fail",
 275        [PVR2_CVAL_HSM_HIGH] = "High",
 276        [PVR2_CVAL_HSM_FULL] = "Full",
 277};
 278
 279
 280static const char *pvr2_state_names[] = {
 281        [PVR2_STATE_NONE] =    "none",
 282        [PVR2_STATE_DEAD] =    "dead",
 283        [PVR2_STATE_COLD] =    "cold",
 284        [PVR2_STATE_WARM] =    "warm",
 285        [PVR2_STATE_ERROR] =   "error",
 286        [PVR2_STATE_READY] =   "ready",
 287        [PVR2_STATE_RUN] =     "run",
 288};
 289
 290
 291struct pvr2_fx2cmd_descdef {
 292        unsigned char id;
 293        unsigned char *desc;
 294};
 295
 296static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 297        {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 298        {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 299        {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 300        {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 301        {FX2CMD_REG_WRITE, "write encoder register"},
 302        {FX2CMD_REG_READ, "read encoder register"},
 303        {FX2CMD_MEMSEL, "encoder memsel"},
 304        {FX2CMD_I2C_WRITE, "i2c write"},
 305        {FX2CMD_I2C_READ, "i2c read"},
 306        {FX2CMD_GET_USB_SPEED, "get USB speed"},
 307        {FX2CMD_STREAMING_ON, "stream on"},
 308        {FX2CMD_STREAMING_OFF, "stream off"},
 309        {FX2CMD_FWPOST1, "fwpost1"},
 310        {FX2CMD_POWER_OFF, "power off"},
 311        {FX2CMD_POWER_ON, "power on"},
 312        {FX2CMD_DEEP_RESET, "deep reset"},
 313        {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 314        {FX2CMD_GET_IR_CODE, "get IR code"},
 315        {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 316        {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 317        {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 318        {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 319        {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 320        {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 321        {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 322};
 323
 324
 325static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 326static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 327static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 328static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 329static void pvr2_hdw_worker_poll(struct work_struct *work);
 330static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 331static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 332static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 333static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 334static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 335static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 336static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 337static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 338static void pvr2_hdw_quiescent_timeout(unsigned long);
 339static void pvr2_hdw_decoder_stabilization_timeout(unsigned long);
 340static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 341static void pvr2_hdw_encoder_run_timeout(unsigned long);
 342static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 343static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 344                                unsigned int timeout,int probe_fl,
 345                                void *write_data,unsigned int write_len,
 346                                void *read_data,unsigned int read_len);
 347static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 348
 349
 350static void trace_stbit(const char *name,int val)
 351{
 352        pvr2_trace(PVR2_TRACE_STBITS,
 353                   "State bit %s <-- %s",
 354                   name,(val ? "true" : "false"));
 355}
 356
 357static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 358{
 359        struct pvr2_hdw *hdw = cptr->hdw;
 360        if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 361                *vp = hdw->freqTable[hdw->freqProgSlot-1];
 362        } else {
 363                *vp = 0;
 364        }
 365        return 0;
 366}
 367
 368static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 369{
 370        struct pvr2_hdw *hdw = cptr->hdw;
 371        unsigned int slotId = hdw->freqProgSlot;
 372        if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 373                hdw->freqTable[slotId-1] = v;
 374                /* Handle side effects correctly - if we're tuned to this
 375                   slot, then forgot the slot id relation since the stored
 376                   frequency has been changed. */
 377                if (hdw->freqSelector) {
 378                        if (hdw->freqSlotRadio == slotId) {
 379                                hdw->freqSlotRadio = 0;
 380                        }
 381                } else {
 382                        if (hdw->freqSlotTelevision == slotId) {
 383                                hdw->freqSlotTelevision = 0;
 384                        }
 385                }
 386        }
 387        return 0;
 388}
 389
 390static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 391{
 392        *vp = cptr->hdw->freqProgSlot;
 393        return 0;
 394}
 395
 396static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 397{
 398        struct pvr2_hdw *hdw = cptr->hdw;
 399        if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 400                hdw->freqProgSlot = v;
 401        }
 402        return 0;
 403}
 404
 405static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 406{
 407        struct pvr2_hdw *hdw = cptr->hdw;
 408        *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 409        return 0;
 410}
 411
 412static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 413{
 414        unsigned freq = 0;
 415        struct pvr2_hdw *hdw = cptr->hdw;
 416        if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 417        if (slotId > 0) {
 418                freq = hdw->freqTable[slotId-1];
 419                if (!freq) return 0;
 420                pvr2_hdw_set_cur_freq(hdw,freq);
 421        }
 422        if (hdw->freqSelector) {
 423                hdw->freqSlotRadio = slotId;
 424        } else {
 425                hdw->freqSlotTelevision = slotId;
 426        }
 427        return 0;
 428}
 429
 430static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 431{
 432        *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 433        return 0;
 434}
 435
 436static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 437{
 438        return cptr->hdw->freqDirty != 0;
 439}
 440
 441static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 442{
 443        cptr->hdw->freqDirty = 0;
 444}
 445
 446static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 447{
 448        pvr2_hdw_set_cur_freq(cptr->hdw,v);
 449        return 0;
 450}
 451
 452static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 453{
 454        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 455        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 456        if (stat != 0) {
 457                return stat;
 458        }
 459        *left = cap->bounds.left;
 460        return 0;
 461}
 462
 463static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 464{
 465        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 466        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 467        if (stat != 0) {
 468                return stat;
 469        }
 470        *left = cap->bounds.left;
 471        if (cap->bounds.width > cptr->hdw->cropw_val) {
 472                *left += cap->bounds.width - cptr->hdw->cropw_val;
 473        }
 474        return 0;
 475}
 476
 477static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 478{
 479        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 480        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 481        if (stat != 0) {
 482                return stat;
 483        }
 484        *top = cap->bounds.top;
 485        return 0;
 486}
 487
 488static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 489{
 490        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 491        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 492        if (stat != 0) {
 493                return stat;
 494        }
 495        *top = cap->bounds.top;
 496        if (cap->bounds.height > cptr->hdw->croph_val) {
 497                *top += cap->bounds.height - cptr->hdw->croph_val;
 498        }
 499        return 0;
 500}
 501
 502static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
 503{
 504        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 505        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 506        if (stat != 0) {
 507                return stat;
 508        }
 509        *val = 0;
 510        if (cap->bounds.width > cptr->hdw->cropl_val) {
 511                *val = cap->bounds.width - cptr->hdw->cropl_val;
 512        }
 513        return 0;
 514}
 515
 516static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
 517{
 518        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 519        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 520        if (stat != 0) {
 521                return stat;
 522        }
 523        *val = 0;
 524        if (cap->bounds.height > cptr->hdw->cropt_val) {
 525                *val = cap->bounds.height - cptr->hdw->cropt_val;
 526        }
 527        return 0;
 528}
 529
 530static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 531{
 532        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 533        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 534        if (stat != 0) {
 535                return stat;
 536        }
 537        *val = cap->bounds.left;
 538        return 0;
 539}
 540
 541static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 542{
 543        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 544        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 545        if (stat != 0) {
 546                return stat;
 547        }
 548        *val = cap->bounds.top;
 549        return 0;
 550}
 551
 552static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 553{
 554        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 555        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 556        if (stat != 0) {
 557                return stat;
 558        }
 559        *val = cap->bounds.width;
 560        return 0;
 561}
 562
 563static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 564{
 565        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 566        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 567        if (stat != 0) {
 568                return stat;
 569        }
 570        *val = cap->bounds.height;
 571        return 0;
 572}
 573
 574static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 575{
 576        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 577        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 578        if (stat != 0) {
 579                return stat;
 580        }
 581        *val = cap->defrect.left;
 582        return 0;
 583}
 584
 585static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 586{
 587        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 588        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 589        if (stat != 0) {
 590                return stat;
 591        }
 592        *val = cap->defrect.top;
 593        return 0;
 594}
 595
 596static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 597{
 598        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 599        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 600        if (stat != 0) {
 601                return stat;
 602        }
 603        *val = cap->defrect.width;
 604        return 0;
 605}
 606
 607static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 608{
 609        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 610        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 611        if (stat != 0) {
 612                return stat;
 613        }
 614        *val = cap->defrect.height;
 615        return 0;
 616}
 617
 618static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 619{
 620        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 621        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 622        if (stat != 0) {
 623                return stat;
 624        }
 625        *val = cap->pixelaspect.numerator;
 626        return 0;
 627}
 628
 629static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 630{
 631        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 632        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 633        if (stat != 0) {
 634                return stat;
 635        }
 636        *val = cap->pixelaspect.denominator;
 637        return 0;
 638}
 639
 640static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 641{
 642        /* Actual maximum depends on the video standard in effect. */
 643        if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 644                *vp = 480;
 645        } else {
 646                *vp = 576;
 647        }
 648        return 0;
 649}
 650
 651static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 652{
 653        /* Actual minimum depends on device digitizer type. */
 654        if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 655                *vp = 75;
 656        } else {
 657                *vp = 17;
 658        }
 659        return 0;
 660}
 661
 662static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 663{
 664        *vp = cptr->hdw->input_val;
 665        return 0;
 666}
 667
 668static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 669{
 670        return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 671}
 672
 673static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 674{
 675        return pvr2_hdw_set_input(cptr->hdw,v);
 676}
 677
 678static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 679{
 680        return cptr->hdw->input_dirty != 0;
 681}
 682
 683static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 684{
 685        cptr->hdw->input_dirty = 0;
 686}
 687
 688
 689static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 690{
 691        unsigned long fv;
 692        struct pvr2_hdw *hdw = cptr->hdw;
 693        if (hdw->tuner_signal_stale) {
 694                pvr2_hdw_status_poll(hdw);
 695        }
 696        fv = hdw->tuner_signal_info.rangehigh;
 697        if (!fv) {
 698                /* Safety fallback */
 699                *vp = TV_MAX_FREQ;
 700                return 0;
 701        }
 702        if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 703                fv = (fv * 125) / 2;
 704        } else {
 705                fv = fv * 62500;
 706        }
 707        *vp = fv;
 708        return 0;
 709}
 710
 711static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 712{
 713        unsigned long fv;
 714        struct pvr2_hdw *hdw = cptr->hdw;
 715        if (hdw->tuner_signal_stale) {
 716                pvr2_hdw_status_poll(hdw);
 717        }
 718        fv = hdw->tuner_signal_info.rangelow;
 719        if (!fv) {
 720                /* Safety fallback */
 721                *vp = TV_MIN_FREQ;
 722                return 0;
 723        }
 724        if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 725                fv = (fv * 125) / 2;
 726        } else {
 727                fv = fv * 62500;
 728        }
 729        *vp = fv;
 730        return 0;
 731}
 732
 733static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 734{
 735        return cptr->hdw->enc_stale != 0;
 736}
 737
 738static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 739{
 740        cptr->hdw->enc_stale = 0;
 741        cptr->hdw->enc_unsafe_stale = 0;
 742}
 743
 744static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 745{
 746        int ret;
 747        struct v4l2_ext_controls cs;
 748        struct v4l2_ext_control c1;
 749        memset(&cs,0,sizeof(cs));
 750        memset(&c1,0,sizeof(c1));
 751        cs.controls = &c1;
 752        cs.count = 1;
 753        c1.id = cptr->info->v4l_id;
 754        ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 755                                VIDIOC_G_EXT_CTRLS);
 756        if (ret) return ret;
 757        *vp = c1.value;
 758        return 0;
 759}
 760
 761static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 762{
 763        int ret;
 764        struct pvr2_hdw *hdw = cptr->hdw;
 765        struct v4l2_ext_controls cs;
 766        struct v4l2_ext_control c1;
 767        memset(&cs,0,sizeof(cs));
 768        memset(&c1,0,sizeof(c1));
 769        cs.controls = &c1;
 770        cs.count = 1;
 771        c1.id = cptr->info->v4l_id;
 772        c1.value = v;
 773        ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 774                                hdw->state_encoder_run, &cs,
 775                                VIDIOC_S_EXT_CTRLS);
 776        if (ret == -EBUSY) {
 777                /* Oops.  cx2341x is telling us it's not safe to change
 778                   this control while we're capturing.  Make a note of this
 779                   fact so that the pipeline will be stopped the next time
 780                   controls are committed.  Then go on ahead and store this
 781                   change anyway. */
 782                ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 783                                        0, &cs,
 784                                        VIDIOC_S_EXT_CTRLS);
 785                if (!ret) hdw->enc_unsafe_stale = !0;
 786        }
 787        if (ret) return ret;
 788        hdw->enc_stale = !0;
 789        return 0;
 790}
 791
 792static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 793{
 794        struct v4l2_queryctrl qctrl;
 795        struct pvr2_ctl_info *info;
 796        qctrl.id = cptr->info->v4l_id;
 797        cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 798        /* Strip out the const so we can adjust a function pointer.  It's
 799           OK to do this here because we know this is a dynamically created
 800           control, so the underlying storage for the info pointer is (a)
 801           private to us, and (b) not in read-only storage.  Either we do
 802           this or we significantly complicate the underlying control
 803           implementation. */
 804        info = (struct pvr2_ctl_info *)(cptr->info);
 805        if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 806                if (info->set_value) {
 807                        info->set_value = NULL;
 808                }
 809        } else {
 810                if (!(info->set_value)) {
 811                        info->set_value = ctrl_cx2341x_set;
 812                }
 813        }
 814        return qctrl.flags;
 815}
 816
 817static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 818{
 819        *vp = cptr->hdw->state_pipeline_req;
 820        return 0;
 821}
 822
 823static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 824{
 825        *vp = cptr->hdw->master_state;
 826        return 0;
 827}
 828
 829static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 830{
 831        int result = pvr2_hdw_is_hsm(cptr->hdw);
 832        *vp = PVR2_CVAL_HSM_FULL;
 833        if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 834        if (result) *vp = PVR2_CVAL_HSM_HIGH;
 835        return 0;
 836}
 837
 838static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 839{
 840        *vp = cptr->hdw->std_mask_avail;
 841        return 0;
 842}
 843
 844static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 845{
 846        struct pvr2_hdw *hdw = cptr->hdw;
 847        v4l2_std_id ns;
 848        ns = hdw->std_mask_avail;
 849        ns = (ns & ~m) | (v & m);
 850        if (ns == hdw->std_mask_avail) return 0;
 851        hdw->std_mask_avail = ns;
 852        pvr2_hdw_internal_set_std_avail(hdw);
 853        pvr2_hdw_internal_find_stdenum(hdw);
 854        return 0;
 855}
 856
 857static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 858                               char *bufPtr,unsigned int bufSize,
 859                               unsigned int *len)
 860{
 861        *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 862        return 0;
 863}
 864
 865static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 866                               const char *bufPtr,unsigned int bufSize,
 867                               int *mskp,int *valp)
 868{
 869        int ret;
 870        v4l2_std_id id;
 871        ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 872        if (ret < 0) return ret;
 873        if (mskp) *mskp = id;
 874        if (valp) *valp = id;
 875        return 0;
 876}
 877
 878static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 879{
 880        *vp = cptr->hdw->std_mask_cur;
 881        return 0;
 882}
 883
 884static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 885{
 886        struct pvr2_hdw *hdw = cptr->hdw;
 887        v4l2_std_id ns;
 888        ns = hdw->std_mask_cur;
 889        ns = (ns & ~m) | (v & m);
 890        if (ns == hdw->std_mask_cur) return 0;
 891        hdw->std_mask_cur = ns;
 892        hdw->std_dirty = !0;
 893        pvr2_hdw_internal_find_stdenum(hdw);
 894        return 0;
 895}
 896
 897static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 898{
 899        return cptr->hdw->std_dirty != 0;
 900}
 901
 902static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 903{
 904        cptr->hdw->std_dirty = 0;
 905}
 906
 907static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 908{
 909        struct pvr2_hdw *hdw = cptr->hdw;
 910        pvr2_hdw_status_poll(hdw);
 911        *vp = hdw->tuner_signal_info.signal;
 912        return 0;
 913}
 914
 915static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 916{
 917        int val = 0;
 918        unsigned int subchan;
 919        struct pvr2_hdw *hdw = cptr->hdw;
 920        pvr2_hdw_status_poll(hdw);
 921        subchan = hdw->tuner_signal_info.rxsubchans;
 922        if (subchan & V4L2_TUNER_SUB_MONO) {
 923                val |= (1 << V4L2_TUNER_MODE_MONO);
 924        }
 925        if (subchan & V4L2_TUNER_SUB_STEREO) {
 926                val |= (1 << V4L2_TUNER_MODE_STEREO);
 927        }
 928        if (subchan & V4L2_TUNER_SUB_LANG1) {
 929                val |= (1 << V4L2_TUNER_MODE_LANG1);
 930        }
 931        if (subchan & V4L2_TUNER_SUB_LANG2) {
 932                val |= (1 << V4L2_TUNER_MODE_LANG2);
 933        }
 934        *vp = val;
 935        return 0;
 936}
 937
 938
 939static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 940{
 941        struct pvr2_hdw *hdw = cptr->hdw;
 942        if (v < 0) return -EINVAL;
 943        if (v > hdw->std_enum_cnt) return -EINVAL;
 944        hdw->std_enum_cur = v;
 945        if (!v) return 0;
 946        v--;
 947        if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 948        hdw->std_mask_cur = hdw->std_defs[v].id;
 949        hdw->std_dirty = !0;
 950        return 0;
 951}
 952
 953
 954static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 955{
 956        *vp = cptr->hdw->std_enum_cur;
 957        return 0;
 958}
 959
 960
 961static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 962{
 963        return cptr->hdw->std_dirty != 0;
 964}
 965
 966
 967static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 968{
 969        cptr->hdw->std_dirty = 0;
 970}
 971
 972
 973#define DEFINT(vmin,vmax) \
 974        .type = pvr2_ctl_int, \
 975        .def.type_int.min_value = vmin, \
 976        .def.type_int.max_value = vmax
 977
 978#define DEFENUM(tab) \
 979        .type = pvr2_ctl_enum, \
 980        .def.type_enum.count = ARRAY_SIZE(tab), \
 981        .def.type_enum.value_names = tab
 982
 983#define DEFBOOL \
 984        .type = pvr2_ctl_bool
 985
 986#define DEFMASK(msk,tab) \
 987        .type = pvr2_ctl_bitmask, \
 988        .def.type_bitmask.valid_bits = msk, \
 989        .def.type_bitmask.bit_names = tab
 990
 991#define DEFREF(vname) \
 992        .set_value = ctrl_set_##vname, \
 993        .get_value = ctrl_get_##vname, \
 994        .is_dirty = ctrl_isdirty_##vname, \
 995        .clear_dirty = ctrl_cleardirty_##vname
 996
 997
 998#define VCREATE_FUNCS(vname) \
 999static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
1000{*vp = cptr->hdw->vname##_val; return 0;} \
1001static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
1002{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
1003static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
1004{return cptr->hdw->vname##_dirty != 0;} \
1005static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
1006{cptr->hdw->vname##_dirty = 0;}
1007
1008VCREATE_FUNCS(brightness)
1009VCREATE_FUNCS(contrast)
1010VCREATE_FUNCS(saturation)
1011VCREATE_FUNCS(hue)
1012VCREATE_FUNCS(volume)
1013VCREATE_FUNCS(balance)
1014VCREATE_FUNCS(bass)
1015VCREATE_FUNCS(treble)
1016VCREATE_FUNCS(mute)
1017VCREATE_FUNCS(cropl)
1018VCREATE_FUNCS(cropt)
1019VCREATE_FUNCS(cropw)
1020VCREATE_FUNCS(croph)
1021VCREATE_FUNCS(audiomode)
1022VCREATE_FUNCS(res_hor)
1023VCREATE_FUNCS(res_ver)
1024VCREATE_FUNCS(srate)
1025
1026/* Table definition of all controls which can be manipulated */
1027static const struct pvr2_ctl_info control_defs[] = {
1028        {
1029                .v4l_id = V4L2_CID_BRIGHTNESS,
1030                .desc = "Brightness",
1031                .name = "brightness",
1032                .default_value = 128,
1033                DEFREF(brightness),
1034                DEFINT(0,255),
1035        },{
1036                .v4l_id = V4L2_CID_CONTRAST,
1037                .desc = "Contrast",
1038                .name = "contrast",
1039                .default_value = 68,
1040                DEFREF(contrast),
1041                DEFINT(0,127),
1042        },{
1043                .v4l_id = V4L2_CID_SATURATION,
1044                .desc = "Saturation",
1045                .name = "saturation",
1046                .default_value = 64,
1047                DEFREF(saturation),
1048                DEFINT(0,127),
1049        },{
1050                .v4l_id = V4L2_CID_HUE,
1051                .desc = "Hue",
1052                .name = "hue",
1053                .default_value = 0,
1054                DEFREF(hue),
1055                DEFINT(-128,127),
1056        },{
1057                .v4l_id = V4L2_CID_AUDIO_VOLUME,
1058                .desc = "Volume",
1059                .name = "volume",
1060                .default_value = 62000,
1061                DEFREF(volume),
1062                DEFINT(0,65535),
1063        },{
1064                .v4l_id = V4L2_CID_AUDIO_BALANCE,
1065                .desc = "Balance",
1066                .name = "balance",
1067                .default_value = 0,
1068                DEFREF(balance),
1069                DEFINT(-32768,32767),
1070        },{
1071                .v4l_id = V4L2_CID_AUDIO_BASS,
1072                .desc = "Bass",
1073                .name = "bass",
1074                .default_value = 0,
1075                DEFREF(bass),
1076                DEFINT(-32768,32767),
1077        },{
1078                .v4l_id = V4L2_CID_AUDIO_TREBLE,
1079                .desc = "Treble",
1080                .name = "treble",
1081                .default_value = 0,
1082                DEFREF(treble),
1083                DEFINT(-32768,32767),
1084        },{
1085                .v4l_id = V4L2_CID_AUDIO_MUTE,
1086                .desc = "Mute",
1087                .name = "mute",
1088                .default_value = 0,
1089                DEFREF(mute),
1090                DEFBOOL,
1091        }, {
1092                .desc = "Capture crop left margin",
1093                .name = "crop_left",
1094                .internal_id = PVR2_CID_CROPL,
1095                .default_value = 0,
1096                DEFREF(cropl),
1097                DEFINT(-129, 340),
1098                .get_min_value = ctrl_cropl_min_get,
1099                .get_max_value = ctrl_cropl_max_get,
1100                .get_def_value = ctrl_get_cropcapdl,
1101        }, {
1102                .desc = "Capture crop top margin",
1103                .name = "crop_top",
1104                .internal_id = PVR2_CID_CROPT,
1105                .default_value = 0,
1106                DEFREF(cropt),
1107                DEFINT(-35, 544),
1108                .get_min_value = ctrl_cropt_min_get,
1109                .get_max_value = ctrl_cropt_max_get,
1110                .get_def_value = ctrl_get_cropcapdt,
1111        }, {
1112                .desc = "Capture crop width",
1113                .name = "crop_width",
1114                .internal_id = PVR2_CID_CROPW,
1115                .default_value = 720,
1116                DEFREF(cropw),
1117                .get_max_value = ctrl_cropw_max_get,
1118                .get_def_value = ctrl_get_cropcapdw,
1119        }, {
1120                .desc = "Capture crop height",
1121                .name = "crop_height",
1122                .internal_id = PVR2_CID_CROPH,
1123                .default_value = 480,
1124                DEFREF(croph),
1125                .get_max_value = ctrl_croph_max_get,
1126                .get_def_value = ctrl_get_cropcapdh,
1127        }, {
1128                .desc = "Capture capability pixel aspect numerator",
1129                .name = "cropcap_pixel_numerator",
1130                .internal_id = PVR2_CID_CROPCAPPAN,
1131                .get_value = ctrl_get_cropcappan,
1132        }, {
1133                .desc = "Capture capability pixel aspect denominator",
1134                .name = "cropcap_pixel_denominator",
1135                .internal_id = PVR2_CID_CROPCAPPAD,
1136                .get_value = ctrl_get_cropcappad,
1137        }, {
1138                .desc = "Capture capability bounds top",
1139                .name = "cropcap_bounds_top",
1140                .internal_id = PVR2_CID_CROPCAPBT,
1141                .get_value = ctrl_get_cropcapbt,
1142        }, {
1143                .desc = "Capture capability bounds left",
1144                .name = "cropcap_bounds_left",
1145                .internal_id = PVR2_CID_CROPCAPBL,
1146                .get_value = ctrl_get_cropcapbl,
1147        }, {
1148                .desc = "Capture capability bounds width",
1149                .name = "cropcap_bounds_width",
1150                .internal_id = PVR2_CID_CROPCAPBW,
1151                .get_value = ctrl_get_cropcapbw,
1152        }, {
1153                .desc = "Capture capability bounds height",
1154                .name = "cropcap_bounds_height",
1155                .internal_id = PVR2_CID_CROPCAPBH,
1156                .get_value = ctrl_get_cropcapbh,
1157        },{
1158                .desc = "Video Source",
1159                .name = "input",
1160                .internal_id = PVR2_CID_INPUT,
1161                .default_value = PVR2_CVAL_INPUT_TV,
1162                .check_value = ctrl_check_input,
1163                DEFREF(input),
1164                DEFENUM(control_values_input),
1165        },{
1166                .desc = "Audio Mode",
1167                .name = "audio_mode",
1168                .internal_id = PVR2_CID_AUDIOMODE,
1169                .default_value = V4L2_TUNER_MODE_STEREO,
1170                DEFREF(audiomode),
1171                DEFENUM(control_values_audiomode),
1172        },{
1173                .desc = "Horizontal capture resolution",
1174                .name = "resolution_hor",
1175                .internal_id = PVR2_CID_HRES,
1176                .default_value = 720,
1177                DEFREF(res_hor),
1178                DEFINT(19,720),
1179        },{
1180                .desc = "Vertical capture resolution",
1181                .name = "resolution_ver",
1182                .internal_id = PVR2_CID_VRES,
1183                .default_value = 480,
1184                DEFREF(res_ver),
1185                DEFINT(17,576),
1186                /* Hook in check for video standard and adjust maximum
1187                   depending on the standard. */
1188                .get_max_value = ctrl_vres_max_get,
1189                .get_min_value = ctrl_vres_min_get,
1190        },{
1191                .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1192                .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1193                .desc = "Audio Sampling Frequency",
1194                .name = "srate",
1195                DEFREF(srate),
1196                DEFENUM(control_values_srate),
1197        },{
1198                .desc = "Tuner Frequency (Hz)",
1199                .name = "frequency",
1200                .internal_id = PVR2_CID_FREQUENCY,
1201                .default_value = 0,
1202                .set_value = ctrl_freq_set,
1203                .get_value = ctrl_freq_get,
1204                .is_dirty = ctrl_freq_is_dirty,
1205                .clear_dirty = ctrl_freq_clear_dirty,
1206                DEFINT(0,0),
1207                /* Hook in check for input value (tv/radio) and adjust
1208                   max/min values accordingly */
1209                .get_max_value = ctrl_freq_max_get,
1210                .get_min_value = ctrl_freq_min_get,
1211        },{
1212                .desc = "Channel",
1213                .name = "channel",
1214                .set_value = ctrl_channel_set,
1215                .get_value = ctrl_channel_get,
1216                DEFINT(0,FREQTABLE_SIZE),
1217        },{
1218                .desc = "Channel Program Frequency",
1219                .name = "freq_table_value",
1220                .set_value = ctrl_channelfreq_set,
1221                .get_value = ctrl_channelfreq_get,
1222                DEFINT(0,0),
1223                /* Hook in check for input value (tv/radio) and adjust
1224                   max/min values accordingly */
1225                .get_max_value = ctrl_freq_max_get,
1226                .get_min_value = ctrl_freq_min_get,
1227        },{
1228                .desc = "Channel Program ID",
1229                .name = "freq_table_channel",
1230                .set_value = ctrl_channelprog_set,
1231                .get_value = ctrl_channelprog_get,
1232                DEFINT(0,FREQTABLE_SIZE),
1233        },{
1234                .desc = "Streaming Enabled",
1235                .name = "streaming_enabled",
1236                .get_value = ctrl_streamingenabled_get,
1237                DEFBOOL,
1238        },{
1239                .desc = "USB Speed",
1240                .name = "usb_speed",
1241                .get_value = ctrl_hsm_get,
1242                DEFENUM(control_values_hsm),
1243        },{
1244                .desc = "Master State",
1245                .name = "master_state",
1246                .get_value = ctrl_masterstate_get,
1247                DEFENUM(pvr2_state_names),
1248        },{
1249                .desc = "Signal Present",
1250                .name = "signal_present",
1251                .get_value = ctrl_signal_get,
1252                DEFINT(0,65535),
1253        },{
1254                .desc = "Audio Modes Present",
1255                .name = "audio_modes_present",
1256                .get_value = ctrl_audio_modes_present_get,
1257                /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1258                   v4l.  Nothing outside of this module cares about this,
1259                   but I reuse it in order to also reuse the
1260                   control_values_audiomode string table. */
1261                DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1262                         (1 << V4L2_TUNER_MODE_STEREO)|
1263                         (1 << V4L2_TUNER_MODE_LANG1)|
1264                         (1 << V4L2_TUNER_MODE_LANG2)),
1265                        control_values_audiomode),
1266        },{
1267                .desc = "Video Standards Available Mask",
1268                .name = "video_standard_mask_available",
1269                .internal_id = PVR2_CID_STDAVAIL,
1270                .skip_init = !0,
1271                .get_value = ctrl_stdavail_get,
1272                .set_value = ctrl_stdavail_set,
1273                .val_to_sym = ctrl_std_val_to_sym,
1274                .sym_to_val = ctrl_std_sym_to_val,
1275                .type = pvr2_ctl_bitmask,
1276        },{
1277                .desc = "Video Standards In Use Mask",
1278                .name = "video_standard_mask_active",
1279                .internal_id = PVR2_CID_STDCUR,
1280                .skip_init = !0,
1281                .get_value = ctrl_stdcur_get,
1282                .set_value = ctrl_stdcur_set,
1283                .is_dirty = ctrl_stdcur_is_dirty,
1284                .clear_dirty = ctrl_stdcur_clear_dirty,
1285                .val_to_sym = ctrl_std_val_to_sym,
1286                .sym_to_val = ctrl_std_sym_to_val,
1287                .type = pvr2_ctl_bitmask,
1288        },{
1289                .desc = "Video Standard Name",
1290                .name = "video_standard",
1291                .internal_id = PVR2_CID_STDENUM,
1292                .skip_init = !0,
1293                .get_value = ctrl_stdenumcur_get,
1294                .set_value = ctrl_stdenumcur_set,
1295                .is_dirty = ctrl_stdenumcur_is_dirty,
1296                .clear_dirty = ctrl_stdenumcur_clear_dirty,
1297                .type = pvr2_ctl_enum,
1298        }
1299};
1300
1301#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1302
1303
1304const char *pvr2_config_get_name(enum pvr2_config cfg)
1305{
1306        switch (cfg) {
1307        case pvr2_config_empty: return "empty";
1308        case pvr2_config_mpeg: return "mpeg";
1309        case pvr2_config_vbi: return "vbi";
1310        case pvr2_config_pcm: return "pcm";
1311        case pvr2_config_rawvideo: return "raw video";
1312        }
1313        return "<unknown>";
1314}
1315
1316
1317struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1318{
1319        return hdw->usb_dev;
1320}
1321
1322
1323unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1324{
1325        return hdw->serial_number;
1326}
1327
1328
1329const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1330{
1331        return hdw->bus_info;
1332}
1333
1334
1335const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1336{
1337        return hdw->identifier;
1338}
1339
1340
1341unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1342{
1343        return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1344}
1345
1346/* Set the currently tuned frequency and account for all possible
1347   driver-core side effects of this action. */
1348static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1349{
1350        if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1351                if (hdw->freqSelector) {
1352                        /* Swing over to radio frequency selection */
1353                        hdw->freqSelector = 0;
1354                        hdw->freqDirty = !0;
1355                }
1356                if (hdw->freqValRadio != val) {
1357                        hdw->freqValRadio = val;
1358                        hdw->freqSlotRadio = 0;
1359                        hdw->freqDirty = !0;
1360                }
1361        } else {
1362                if (!(hdw->freqSelector)) {
1363                        /* Swing over to television frequency selection */
1364                        hdw->freqSelector = 1;
1365                        hdw->freqDirty = !0;
1366                }
1367                if (hdw->freqValTelevision != val) {
1368                        hdw->freqValTelevision = val;
1369                        hdw->freqSlotTelevision = 0;
1370                        hdw->freqDirty = !0;
1371                }
1372        }
1373}
1374
1375int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1376{
1377        return hdw->unit_number;
1378}
1379
1380
1381/* Attempt to locate one of the given set of files.  Messages are logged
1382   appropriate to what has been found.  The return value will be 0 or
1383   greater on success (it will be the index of the file name found) and
1384   fw_entry will be filled in.  Otherwise a negative error is returned on
1385   failure.  If the return value is -ENOENT then no viable firmware file
1386   could be located. */
1387static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1388                                const struct firmware **fw_entry,
1389                                const char *fwtypename,
1390                                unsigned int fwcount,
1391                                const char *fwnames[])
1392{
1393        unsigned int idx;
1394        int ret = -EINVAL;
1395        for (idx = 0; idx < fwcount; idx++) {
1396                ret = request_firmware(fw_entry,
1397                                       fwnames[idx],
1398                                       &hdw->usb_dev->dev);
1399                if (!ret) {
1400                        trace_firmware("Located %s firmware: %s;"
1401                                       " uploading...",
1402                                       fwtypename,
1403                                       fwnames[idx]);
1404                        return idx;
1405                }
1406                if (ret == -ENOENT) continue;
1407                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1408                           "request_firmware fatal error with code=%d",ret);
1409                return ret;
1410        }
1411        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1412                   "***WARNING***"
1413                   " Device %s firmware"
1414                   " seems to be missing.",
1415                   fwtypename);
1416        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1417                   "Did you install the pvrusb2 firmware files"
1418                   " in their proper location?");
1419        if (fwcount == 1) {
1420                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1421                           "request_firmware unable to locate %s file %s",
1422                           fwtypename,fwnames[0]);
1423        } else {
1424                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1425                           "request_firmware unable to locate"
1426                           " one of the following %s files:",
1427                           fwtypename);
1428                for (idx = 0; idx < fwcount; idx++) {
1429                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1430                                   "request_firmware: Failed to find %s",
1431                                   fwnames[idx]);
1432                }
1433        }
1434        return ret;
1435}
1436
1437
1438/*
1439 * pvr2_upload_firmware1().
1440 *
1441 * Send the 8051 firmware to the device.  After the upload, arrange for
1442 * device to re-enumerate.
1443 *
1444 * NOTE : the pointer to the firmware data given by request_firmware()
1445 * is not suitable for an usb transaction.
1446 *
1447 */
1448static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1449{
1450        const struct firmware *fw_entry = NULL;
1451        void  *fw_ptr;
1452        unsigned int pipe;
1453        unsigned int fwsize;
1454        int ret;
1455        u16 address;
1456
1457        if (!hdw->hdw_desc->fx2_firmware.cnt) {
1458                hdw->fw1_state = FW1_STATE_OK;
1459                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1460                           "Connected device type defines"
1461                           " no firmware to upload; ignoring firmware");
1462                return -ENOTTY;
1463        }
1464
1465        hdw->fw1_state = FW1_STATE_FAILED; // default result
1466
1467        trace_firmware("pvr2_upload_firmware1");
1468
1469        ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1470                                   hdw->hdw_desc->fx2_firmware.cnt,
1471                                   hdw->hdw_desc->fx2_firmware.lst);
1472        if (ret < 0) {
1473                if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1474                return ret;
1475        }
1476
1477        usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1478
1479        pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1480        fwsize = fw_entry->size;
1481
1482        if ((fwsize != 0x2000) &&
1483            (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
1484                if (hdw->hdw_desc->flag_fx2_16kb) {
1485                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1486                                   "Wrong fx2 firmware size"
1487                                   " (expected 8192 or 16384, got %u)",
1488                                   fwsize);
1489                } else {
1490                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1491                                   "Wrong fx2 firmware size"
1492                                   " (expected 8192, got %u)",
1493                                   fwsize);
1494                }
1495                release_firmware(fw_entry);
1496                return -ENOMEM;
1497        }
1498
1499        fw_ptr = kmalloc(0x800, GFP_KERNEL);
1500        if (fw_ptr == NULL){
1501                release_firmware(fw_entry);
1502                return -ENOMEM;
1503        }
1504
1505        /* We have to hold the CPU during firmware upload. */
1506        pvr2_hdw_cpureset_assert(hdw,1);
1507
1508        /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1509           chunk. */
1510
1511        ret = 0;
1512        for (address = 0; address < fwsize; address += 0x800) {
1513                memcpy(fw_ptr, fw_entry->data + address, 0x800);
1514                ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1515                                       0, fw_ptr, 0x800, HZ);
1516        }
1517
1518        trace_firmware("Upload done, releasing device's CPU");
1519
1520        /* Now release the CPU.  It will disconnect and reconnect later. */
1521        pvr2_hdw_cpureset_assert(hdw,0);
1522
1523        kfree(fw_ptr);
1524        release_firmware(fw_entry);
1525
1526        trace_firmware("Upload done (%d bytes sent)",ret);
1527
1528        /* We should have written fwsize bytes */
1529        if (ret == fwsize) {
1530                hdw->fw1_state = FW1_STATE_RELOAD;
1531                return 0;
1532        }
1533
1534        return -EIO;
1535}
1536
1537
1538/*
1539 * pvr2_upload_firmware2()
1540 *
1541 * This uploads encoder firmware on endpoint 2.
1542 *
1543 */
1544
1545int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1546{
1547        const struct firmware *fw_entry = NULL;
1548        void  *fw_ptr;
1549        unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1550        int actual_length;
1551        int ret = 0;
1552        int fwidx;
1553        static const char *fw_files[] = {
1554                CX2341X_FIRM_ENC_FILENAME,
1555        };
1556
1557        if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1558                return 0;
1559        }
1560
1561        trace_firmware("pvr2_upload_firmware2");
1562
1563        ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1564                                   ARRAY_SIZE(fw_files), fw_files);
1565        if (ret < 0) return ret;
1566        fwidx = ret;
1567        ret = 0;
1568        /* Since we're about to completely reinitialize the encoder,
1569           invalidate our cached copy of its configuration state.  Next
1570           time we configure the encoder, then we'll fully configure it. */
1571        hdw->enc_cur_valid = 0;
1572
1573        /* Encoder is about to be reset so note that as far as we're
1574           concerned now, the encoder has never been run. */
1575        del_timer_sync(&hdw->encoder_run_timer);
1576        if (hdw->state_encoder_runok) {
1577                hdw->state_encoder_runok = 0;
1578                trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1579        }
1580
1581        /* First prepare firmware loading */
1582        ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1583        ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1584        ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1585        ret |= pvr2_hdw_cmd_deep_reset(hdw);
1586        ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1587        ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1588        ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1589        ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1590        ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1591        ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1592        ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1593        ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1594        ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1595        ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1596        ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1597        ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1598        ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1599        ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1600
1601        if (ret) {
1602                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1603                           "firmware2 upload prep failed, ret=%d",ret);
1604                release_firmware(fw_entry);
1605                goto done;
1606        }
1607
1608        /* Now send firmware */
1609
1610        fw_len = fw_entry->size;
1611
1612        if (fw_len % sizeof(u32)) {
1613                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1614                           "size of %s firmware"
1615                           " must be a multiple of %zu bytes",
1616                           fw_files[fwidx],sizeof(u32));
1617                release_firmware(fw_entry);
1618                ret = -EINVAL;
1619                goto done;
1620        }
1621
1622        fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1623        if (fw_ptr == NULL){
1624                release_firmware(fw_entry);
1625                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1626                           "failed to allocate memory for firmware2 upload");
1627                ret = -ENOMEM;
1628                goto done;
1629        }
1630
1631        pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1632
1633        fw_done = 0;
1634        for (fw_done = 0; fw_done < fw_len;) {
1635                bcnt = fw_len - fw_done;
1636                if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1637                memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1638                /* Usbsnoop log shows that we must swap bytes... */
1639                /* Some background info: The data being swapped here is a
1640                   firmware image destined for the mpeg encoder chip that
1641                   lives at the other end of a USB endpoint.  The encoder
1642                   chip always talks in 32 bit chunks and its storage is
1643                   organized into 32 bit words.  However from the file
1644                   system to the encoder chip everything is purely a byte
1645                   stream.  The firmware file's contents are always 32 bit
1646                   swapped from what the encoder expects.  Thus the need
1647                   always exists to swap the bytes regardless of the endian
1648                   type of the host processor and therefore swab32() makes
1649                   the most sense. */
1650                for (icnt = 0; icnt < bcnt/4 ; icnt++)
1651                        ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1652
1653                ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1654                                    &actual_length, HZ);
1655                ret |= (actual_length != bcnt);
1656                if (ret) break;
1657                fw_done += bcnt;
1658        }
1659
1660        trace_firmware("upload of %s : %i / %i ",
1661                       fw_files[fwidx],fw_done,fw_len);
1662
1663        kfree(fw_ptr);
1664        release_firmware(fw_entry);
1665
1666        if (ret) {
1667                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1668                           "firmware2 upload transfer failure");
1669                goto done;
1670        }
1671
1672        /* Finish upload */
1673
1674        ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1675        ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1676        ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1677
1678        if (ret) {
1679                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1680                           "firmware2 upload post-proc failure");
1681        }
1682
1683 done:
1684        if (hdw->hdw_desc->signal_routing_scheme ==
1685            PVR2_ROUTING_SCHEME_GOTVIEW) {
1686                /* Ensure that GPIO 11 is set to output for GOTVIEW
1687                   hardware. */
1688                pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1689        }
1690        return ret;
1691}
1692
1693
1694static const char *pvr2_get_state_name(unsigned int st)
1695{
1696        if (st < ARRAY_SIZE(pvr2_state_names)) {
1697                return pvr2_state_names[st];
1698        }
1699        return "???";
1700}
1701
1702static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1703{
1704        /* Even though we really only care about the video decoder chip at
1705           this point, we'll broadcast stream on/off to all sub-devices
1706           anyway, just in case somebody else wants to hear the
1707           command... */
1708        pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1709                   (enablefl ? "on" : "off"));
1710        v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1711        v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
1712        if (hdw->decoder_client_id) {
1713                /* We get here if the encoder has been noticed.  Otherwise
1714                   we'll issue a warning to the user (which should
1715                   normally never happen). */
1716                return 0;
1717        }
1718        if (!hdw->flag_decoder_missed) {
1719                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1720                           "WARNING: No decoder present");
1721                hdw->flag_decoder_missed = !0;
1722                trace_stbit("flag_decoder_missed",
1723                            hdw->flag_decoder_missed);
1724        }
1725        return -EIO;
1726}
1727
1728
1729int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1730{
1731        return hdw->master_state;
1732}
1733
1734
1735static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1736{
1737        if (!hdw->flag_tripped) return 0;
1738        hdw->flag_tripped = 0;
1739        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1740                   "Clearing driver error statuss");
1741        return !0;
1742}
1743
1744
1745int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1746{
1747        int fl;
1748        LOCK_TAKE(hdw->big_lock); do {
1749                fl = pvr2_hdw_untrip_unlocked(hdw);
1750        } while (0); LOCK_GIVE(hdw->big_lock);
1751        if (fl) pvr2_hdw_state_sched(hdw);
1752        return 0;
1753}
1754
1755
1756
1757
1758int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1759{
1760        return hdw->state_pipeline_req != 0;
1761}
1762
1763
1764int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1765{
1766        int ret,st;
1767        LOCK_TAKE(hdw->big_lock); do {
1768                pvr2_hdw_untrip_unlocked(hdw);
1769                if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1770                        hdw->state_pipeline_req = enable_flag != 0;
1771                        pvr2_trace(PVR2_TRACE_START_STOP,
1772                                   "/*--TRACE_STREAM--*/ %s",
1773                                   enable_flag ? "enable" : "disable");
1774                }
1775                pvr2_hdw_state_sched(hdw);
1776        } while (0); LOCK_GIVE(hdw->big_lock);
1777        if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1778        if (enable_flag) {
1779                while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1780                        if (st != PVR2_STATE_READY) return -EIO;
1781                        if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1782                }
1783        }
1784        return 0;
1785}
1786
1787
1788int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1789{
1790        int fl;
1791        LOCK_TAKE(hdw->big_lock);
1792        if ((fl = (hdw->desired_stream_type != config)) != 0) {
1793                hdw->desired_stream_type = config;
1794                hdw->state_pipeline_config = 0;
1795                trace_stbit("state_pipeline_config",
1796                            hdw->state_pipeline_config);
1797                pvr2_hdw_state_sched(hdw);
1798        }
1799        LOCK_GIVE(hdw->big_lock);
1800        if (fl) return 0;
1801        return pvr2_hdw_wait(hdw,0);
1802}
1803
1804
1805static int get_default_tuner_type(struct pvr2_hdw *hdw)
1806{
1807        int unit_number = hdw->unit_number;
1808        int tp = -1;
1809        if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1810                tp = tuner[unit_number];
1811        }
1812        if (tp < 0) return -EINVAL;
1813        hdw->tuner_type = tp;
1814        hdw->tuner_updated = !0;
1815        return 0;
1816}
1817
1818
1819static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1820{
1821        int unit_number = hdw->unit_number;
1822        int tp = 0;
1823        if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1824                tp = video_std[unit_number];
1825                if (tp) return tp;
1826        }
1827        return 0;
1828}
1829
1830
1831static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1832{
1833        int unit_number = hdw->unit_number;
1834        int tp = 0;
1835        if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1836                tp = tolerance[unit_number];
1837        }
1838        return tp;
1839}
1840
1841
1842static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1843{
1844        /* Try a harmless request to fetch the eeprom's address over
1845           endpoint 1.  See what happens.  Only the full FX2 image can
1846           respond to this.  If this probe fails then likely the FX2
1847           firmware needs be loaded. */
1848        int result;
1849        LOCK_TAKE(hdw->ctl_lock); do {
1850                hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1851                result = pvr2_send_request_ex(hdw,HZ*1,!0,
1852                                           hdw->cmd_buffer,1,
1853                                           hdw->cmd_buffer,1);
1854                if (result < 0) break;
1855        } while(0); LOCK_GIVE(hdw->ctl_lock);
1856        if (result) {
1857                pvr2_trace(PVR2_TRACE_INIT,
1858                           "Probe of device endpoint 1 result status %d",
1859                           result);
1860        } else {
1861                pvr2_trace(PVR2_TRACE_INIT,
1862                           "Probe of device endpoint 1 succeeded");
1863        }
1864        return result == 0;
1865}
1866
1867struct pvr2_std_hack {
1868        v4l2_std_id pat;  /* Pattern to match */
1869        v4l2_std_id msk;  /* Which bits we care about */
1870        v4l2_std_id std;  /* What additional standards or default to set */
1871};
1872
1873/* This data structure labels specific combinations of standards from
1874   tveeprom that we'll try to recognize.  If we recognize one, then assume
1875   a specified default standard to use.  This is here because tveeprom only
1876   tells us about available standards not the intended default standard (if
1877   any) for the device in question.  We guess the default based on what has
1878   been reported as available.  Note that this is only for guessing a
1879   default - which can always be overridden explicitly - and if the user
1880   has otherwise named a default then that default will always be used in
1881   place of this table. */
1882static const struct pvr2_std_hack std_eeprom_maps[] = {
1883        {       /* PAL(B/G) */
1884                .pat = V4L2_STD_B|V4L2_STD_GH,
1885                .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1886        },
1887        {       /* NTSC(M) */
1888                .pat = V4L2_STD_MN,
1889                .std = V4L2_STD_NTSC_M,
1890        },
1891        {       /* PAL(I) */
1892                .pat = V4L2_STD_PAL_I,
1893                .std = V4L2_STD_PAL_I,
1894        },
1895        {       /* SECAM(L/L') */
1896                .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1897                .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1898        },
1899        {       /* PAL(D/D1/K) */
1900                .pat = V4L2_STD_DK,
1901                .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1902        },
1903};
1904
1905static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1906{
1907        char buf[40];
1908        unsigned int bcnt;
1909        v4l2_std_id std1,std2,std3;
1910
1911        std1 = get_default_standard(hdw);
1912        std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1913
1914        bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1915        pvr2_trace(PVR2_TRACE_STD,
1916                   "Supported video standard(s) reported available"
1917                   " in hardware: %.*s",
1918                   bcnt,buf);
1919
1920        hdw->std_mask_avail = hdw->std_mask_eeprom;
1921
1922        std2 = (std1|std3) & ~hdw->std_mask_avail;
1923        if (std2) {
1924                bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1925                pvr2_trace(PVR2_TRACE_STD,
1926                           "Expanding supported video standards"
1927                           " to include: %.*s",
1928                           bcnt,buf);
1929                hdw->std_mask_avail |= std2;
1930        }
1931
1932        pvr2_hdw_internal_set_std_avail(hdw);
1933
1934        if (std1) {
1935                bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1936                pvr2_trace(PVR2_TRACE_STD,
1937                           "Initial video standard forced to %.*s",
1938                           bcnt,buf);
1939                hdw->std_mask_cur = std1;
1940                hdw->std_dirty = !0;
1941                pvr2_hdw_internal_find_stdenum(hdw);
1942                return;
1943        }
1944        if (std3) {
1945                bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1946                pvr2_trace(PVR2_TRACE_STD,
1947                           "Initial video standard"
1948                           " (determined by device type): %.*s",bcnt,buf);
1949                hdw->std_mask_cur = std3;
1950                hdw->std_dirty = !0;
1951                pvr2_hdw_internal_find_stdenum(hdw);
1952                return;
1953        }
1954
1955        {
1956                unsigned int idx;
1957                for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1958                        if (std_eeprom_maps[idx].msk ?
1959                            ((std_eeprom_maps[idx].pat ^
1960                             hdw->std_mask_eeprom) &
1961                             std_eeprom_maps[idx].msk) :
1962                            (std_eeprom_maps[idx].pat !=
1963                             hdw->std_mask_eeprom)) continue;
1964                        bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1965                                                  std_eeprom_maps[idx].std);
1966                        pvr2_trace(PVR2_TRACE_STD,
1967                                   "Initial video standard guessed as %.*s",
1968                                   bcnt,buf);
1969                        hdw->std_mask_cur = std_eeprom_maps[idx].std;
1970                        hdw->std_dirty = !0;
1971                        pvr2_hdw_internal_find_stdenum(hdw);
1972                        return;
1973                }
1974        }
1975
1976        if (hdw->std_enum_cnt > 1) {
1977                // Autoselect the first listed standard
1978                hdw->std_enum_cur = 1;
1979                hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1980                hdw->std_dirty = !0;
1981                pvr2_trace(PVR2_TRACE_STD,
1982                           "Initial video standard auto-selected to %s",
1983                           hdw->std_defs[hdw->std_enum_cur-1].name);
1984                return;
1985        }
1986
1987        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1988                   "Unable to select a viable initial video standard");
1989}
1990
1991
1992static unsigned int pvr2_copy_i2c_addr_list(
1993        unsigned short *dst, const unsigned char *src,
1994        unsigned int dst_max)
1995{
1996        unsigned int cnt = 0;
1997        if (!src) return 0;
1998        while (src[cnt] && (cnt + 1) < dst_max) {
1999                dst[cnt] = src[cnt];
2000                cnt++;
2001        }
2002        dst[cnt] = I2C_CLIENT_END;
2003        return cnt;
2004}
2005
2006
2007static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
2008{
2009        /*
2010          Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
2011          for cx25840 causes that module to correctly set up its video
2012          scaling.  This is really a problem in the cx25840 module itself,
2013          but we work around it here.  The problem has not been seen in
2014          ivtv because there VBI is supported and set up.  We don't do VBI
2015          here (at least not yet) and thus we never attempted to even set
2016          it up.
2017        */
2018        struct v4l2_format fmt;
2019        if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
2020                /* We're not using a cx25840 so don't enable the hack */
2021                return;
2022        }
2023
2024        pvr2_trace(PVR2_TRACE_INIT,
2025                   "Module ID %u:"
2026                   " Executing cx25840 VBI hack",
2027                   hdw->decoder_client_id);
2028        memset(&fmt, 0, sizeof(fmt));
2029        fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2030        v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
2031                             vbi, s_sliced_fmt, &fmt.fmt.sliced);
2032}
2033
2034
2035static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
2036                                const struct pvr2_device_client_desc *cd)
2037{
2038        const char *fname;
2039        unsigned char mid;
2040        struct v4l2_subdev *sd;
2041        unsigned int i2ccnt;
2042        const unsigned char *p;
2043        /* Arbitrary count - max # i2c addresses we will probe */
2044        unsigned short i2caddr[25];
2045
2046        mid = cd->module_id;
2047        fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2048        if (!fname) {
2049                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2050                           "Module ID %u for device %s has no name?"
2051                           "  The driver might have a configuration problem.",
2052                           mid,
2053                           hdw->hdw_desc->description);
2054                return -EINVAL;
2055        }
2056        pvr2_trace(PVR2_TRACE_INIT,
2057                   "Module ID %u (%s) for device %s being loaded...",
2058                   mid, fname,
2059                   hdw->hdw_desc->description);
2060
2061        i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2062                                         ARRAY_SIZE(i2caddr));
2063        if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2064                         module_i2c_addresses[mid] : NULL) != NULL)) {
2065                /* Second chance: Try default i2c address list */
2066                i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2067                                                 ARRAY_SIZE(i2caddr));
2068                if (i2ccnt) {
2069                        pvr2_trace(PVR2_TRACE_INIT,
2070                                   "Module ID %u:"
2071                                   " Using default i2c address list",
2072                                   mid);
2073                }
2074        }
2075
2076        if (!i2ccnt) {
2077                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2078                           "Module ID %u (%s) for device %s:"
2079                           " No i2c addresses."
2080                           "  The driver might have a configuration problem.",
2081                           mid, fname, hdw->hdw_desc->description);
2082                return -EINVAL;
2083        }
2084
2085        if (i2ccnt == 1) {
2086                pvr2_trace(PVR2_TRACE_INIT,
2087                           "Module ID %u:"
2088                           " Setting up with specified i2c address 0x%x",
2089                           mid, i2caddr[0]);
2090                sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2091                                         fname, i2caddr[0], NULL);
2092        } else {
2093                pvr2_trace(PVR2_TRACE_INIT,
2094                           "Module ID %u:"
2095                           " Setting up with address probe list",
2096                           mid);
2097                sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2098                                         fname, 0, i2caddr);
2099        }
2100
2101        if (!sd) {
2102                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2103                           "Module ID %u (%s) for device %s failed to load."
2104                           "  Possible missing sub-device kernel module or"
2105                           " initialization failure within module.",
2106                           mid, fname, hdw->hdw_desc->description);
2107                return -EIO;
2108        }
2109
2110        /* Tag this sub-device instance with the module ID we know about.
2111           In other places we'll use that tag to determine if the instance
2112           requires special handling. */
2113        sd->grp_id = mid;
2114
2115        pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
2116
2117
2118        /* client-specific setup... */
2119        switch (mid) {
2120        case PVR2_CLIENT_ID_CX25840:
2121        case PVR2_CLIENT_ID_SAA7115:
2122                hdw->decoder_client_id = mid;
2123                break;
2124        default: break;
2125        }
2126
2127        return 0;
2128}
2129
2130
2131static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2132{
2133        unsigned int idx;
2134        const struct pvr2_string_table *cm;
2135        const struct pvr2_device_client_table *ct;
2136        int okFl = !0;
2137
2138        cm = &hdw->hdw_desc->client_modules;
2139        for (idx = 0; idx < cm->cnt; idx++) {
2140                request_module(cm->lst[idx]);
2141        }
2142
2143        ct = &hdw->hdw_desc->client_table;
2144        for (idx = 0; idx < ct->cnt; idx++) {
2145                if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
2146        }
2147        if (!okFl) {
2148                hdw->flag_modulefail = !0;
2149                pvr2_hdw_render_useless(hdw);
2150        }
2151}
2152
2153
2154static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2155{
2156        int ret;
2157        unsigned int idx;
2158        struct pvr2_ctrl *cptr;
2159        int reloadFl = 0;
2160        if (hdw->hdw_desc->fx2_firmware.cnt) {
2161                if (!reloadFl) {
2162                        reloadFl =
2163                                (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2164                                 == 0);
2165                        if (reloadFl) {
2166                                pvr2_trace(PVR2_TRACE_INIT,
2167                                           "USB endpoint config looks strange"
2168                                           "; possibly firmware needs to be"
2169                                           " loaded");
2170                        }
2171                }
2172                if (!reloadFl) {
2173                        reloadFl = !pvr2_hdw_check_firmware(hdw);
2174                        if (reloadFl) {
2175                                pvr2_trace(PVR2_TRACE_INIT,
2176                                           "Check for FX2 firmware failed"
2177                                           "; possibly firmware needs to be"
2178                                           " loaded");
2179                        }
2180                }
2181                if (reloadFl) {
2182                        if (pvr2_upload_firmware1(hdw) != 0) {
2183                                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2184                                           "Failure uploading firmware1");
2185                        }
2186                        return;
2187                }
2188        }
2189        hdw->fw1_state = FW1_STATE_OK;
2190
2191        if (!pvr2_hdw_dev_ok(hdw)) return;
2192
2193        hdw->force_dirty = !0;
2194
2195        if (!hdw->hdw_desc->flag_no_powerup) {
2196                pvr2_hdw_cmd_powerup(hdw);
2197                if (!pvr2_hdw_dev_ok(hdw)) return;
2198        }
2199
2200        /* Take the IR chip out of reset, if appropriate */
2201        if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
2202                pvr2_issue_simple_cmd(hdw,
2203                                      FX2CMD_HCW_ZILOG_RESET |
2204                                      (1 << 8) |
2205                                      ((0) << 16));
2206        }
2207
2208        // This step MUST happen after the earlier powerup step.
2209        pvr2_i2c_core_init(hdw);
2210        if (!pvr2_hdw_dev_ok(hdw)) return;
2211
2212        pvr2_hdw_load_modules(hdw);
2213        if (!pvr2_hdw_dev_ok(hdw)) return;
2214
2215        v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
2216
2217        for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2218                cptr = hdw->controls + idx;
2219                if (cptr->info->skip_init) continue;
2220                if (!cptr->info->set_value) continue;
2221                cptr->info->set_value(cptr,~0,cptr->info->default_value);
2222        }
2223
2224        pvr2_hdw_cx25840_vbi_hack(hdw);
2225
2226        /* Set up special default values for the television and radio
2227           frequencies here.  It's not really important what these defaults
2228           are, but I set them to something usable in the Chicago area just
2229           to make driver testing a little easier. */
2230
2231        hdw->freqValTelevision = default_tv_freq;
2232        hdw->freqValRadio = default_radio_freq;
2233
2234        // Do not use pvr2_reset_ctl_endpoints() here.  It is not
2235        // thread-safe against the normal pvr2_send_request() mechanism.
2236        // (We should make it thread safe).
2237
2238        if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2239                ret = pvr2_hdw_get_eeprom_addr(hdw);
2240                if (!pvr2_hdw_dev_ok(hdw)) return;
2241                if (ret < 0) {
2242                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2243                                   "Unable to determine location of eeprom,"
2244                                   " skipping");
2245                } else {
2246                        hdw->eeprom_addr = ret;
2247                        pvr2_eeprom_analyze(hdw);
2248                        if (!pvr2_hdw_dev_ok(hdw)) return;
2249                }
2250        } else {
2251                hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2252                hdw->tuner_updated = !0;
2253                hdw->std_mask_eeprom = V4L2_STD_ALL;
2254        }
2255
2256        if (hdw->serial_number) {
2257                idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2258                                "sn-%lu", hdw->serial_number);
2259        } else if (hdw->unit_number >= 0) {
2260                idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2261                                "unit-%c",
2262                                hdw->unit_number + 'a');
2263        } else {
2264                idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2265                                "unit-??");
2266        }
2267        hdw->identifier[idx] = 0;
2268
2269        pvr2_hdw_setup_std(hdw);
2270
2271        if (!get_default_tuner_type(hdw)) {
2272                pvr2_trace(PVR2_TRACE_INIT,
2273                           "pvr2_hdw_setup: Tuner type overridden to %d",
2274                           hdw->tuner_type);
2275        }
2276
2277
2278        if (!pvr2_hdw_dev_ok(hdw)) return;
2279
2280        if (hdw->hdw_desc->signal_routing_scheme ==
2281            PVR2_ROUTING_SCHEME_GOTVIEW) {
2282                /* Ensure that GPIO 11 is set to output for GOTVIEW
2283                   hardware. */
2284                pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2285        }
2286
2287        pvr2_hdw_commit_setup(hdw);
2288
2289        hdw->vid_stream = pvr2_stream_create();
2290        if (!pvr2_hdw_dev_ok(hdw)) return;
2291        pvr2_trace(PVR2_TRACE_INIT,
2292                   "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2293        if (hdw->vid_stream) {
2294                idx = get_default_error_tolerance(hdw);
2295                if (idx) {
2296                        pvr2_trace(PVR2_TRACE_INIT,
2297                                   "pvr2_hdw_setup: video stream %p"
2298                                   " setting tolerance %u",
2299                                   hdw->vid_stream,idx);
2300                }
2301                pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2302                                  PVR2_VID_ENDPOINT,idx);
2303        }
2304
2305        if (!pvr2_hdw_dev_ok(hdw)) return;
2306
2307        hdw->flag_init_ok = !0;
2308
2309        pvr2_hdw_state_sched(hdw);
2310}
2311
2312
2313/* Set up the structure and attempt to put the device into a usable state.
2314   This can be a time-consuming operation, which is why it is not done
2315   internally as part of the create() step. */
2316static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2317{
2318        pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2319        do {
2320                pvr2_hdw_setup_low(hdw);
2321                pvr2_trace(PVR2_TRACE_INIT,
2322                           "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2323                           hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2324                if (pvr2_hdw_dev_ok(hdw)) {
2325                        if (hdw->flag_init_ok) {
2326                                pvr2_trace(
2327                                        PVR2_TRACE_INFO,
2328                                        "Device initialization"
2329                                        " completed successfully.");
2330                                break;
2331                        }
2332                        if (hdw->fw1_state == FW1_STATE_RELOAD) {
2333                                pvr2_trace(
2334                                        PVR2_TRACE_INFO,
2335                                        "Device microcontroller firmware"
2336                                        " (re)loaded; it should now reset"
2337                                        " and reconnect.");
2338                                break;
2339                        }
2340                        pvr2_trace(
2341                                PVR2_TRACE_ERROR_LEGS,
2342                                "Device initialization was not successful.");
2343                        if (hdw->fw1_state == FW1_STATE_MISSING) {
2344                                pvr2_trace(
2345                                        PVR2_TRACE_ERROR_LEGS,
2346                                        "Giving up since device"
2347                                        " microcontroller firmware"
2348                                        " appears to be missing.");
2349                                break;
2350                        }
2351                }
2352                if (hdw->flag_modulefail) {
2353                        pvr2_trace(
2354                                PVR2_TRACE_ERROR_LEGS,
2355                                "***WARNING*** pvrusb2 driver initialization"
2356                                " failed due to the failure of one or more"
2357                                " sub-device kernel modules.");
2358                        pvr2_trace(
2359                                PVR2_TRACE_ERROR_LEGS,
2360                                "You need to resolve the failing condition"
2361                                " before this driver can function.  There"
2362                                " should be some earlier messages giving more"
2363                                " information about the problem.");
2364                        break;
2365                }
2366                if (procreload) {
2367                        pvr2_trace(
2368                                PVR2_TRACE_ERROR_LEGS,
2369                                "Attempting pvrusb2 recovery by reloading"
2370                                " primary firmware.");
2371                        pvr2_trace(
2372                                PVR2_TRACE_ERROR_LEGS,
2373                                "If this works, device should disconnect"
2374                                " and reconnect in a sane state.");
2375                        hdw->fw1_state = FW1_STATE_UNKNOWN;
2376                        pvr2_upload_firmware1(hdw);
2377                } else {
2378                        pvr2_trace(
2379                                PVR2_TRACE_ERROR_LEGS,
2380                                "***WARNING*** pvrusb2 device hardware"
2381                                " appears to be jammed"
2382                                " and I can't clear it.");
2383                        pvr2_trace(
2384                                PVR2_TRACE_ERROR_LEGS,
2385                                "You might need to power cycle"
2386                                " the pvrusb2 device"
2387                                " in order to recover.");
2388                }
2389        } while (0);
2390        pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2391}
2392
2393
2394/* Perform second stage initialization.  Set callback pointer first so that
2395   we can avoid a possible initialization race (if the kernel thread runs
2396   before the callback has been set). */
2397int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2398                        void (*callback_func)(void *),
2399                        void *callback_data)
2400{
2401        LOCK_TAKE(hdw->big_lock); do {
2402                if (hdw->flag_disconnected) {
2403                        /* Handle a race here: If we're already
2404                           disconnected by this point, then give up.  If we
2405                           get past this then we'll remain connected for
2406                           the duration of initialization since the entire
2407                           initialization sequence is now protected by the
2408                           big_lock. */
2409                        break;
2410                }
2411                hdw->state_data = callback_data;
2412                hdw->state_func = callback_func;
2413                pvr2_hdw_setup(hdw);
2414        } while (0); LOCK_GIVE(hdw->big_lock);
2415        return hdw->flag_init_ok;
2416}
2417
2418
2419/* Create, set up, and return a structure for interacting with the
2420   underlying hardware.  */
2421struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2422                                 const struct usb_device_id *devid)
2423{
2424        unsigned int idx,cnt1,cnt2,m;
2425        struct pvr2_hdw *hdw = NULL;
2426        int valid_std_mask;
2427        struct pvr2_ctrl *cptr;
2428        struct usb_device *usb_dev;
2429        const struct pvr2_device_desc *hdw_desc;
2430        __u8 ifnum;
2431        struct v4l2_queryctrl qctrl;
2432        struct pvr2_ctl_info *ciptr;
2433
2434        usb_dev = interface_to_usbdev(intf);
2435
2436        hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2437
2438        if (hdw_desc == NULL) {
2439                pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2440                           " No device description pointer,"
2441                           " unable to continue.");
2442                pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2443                           " please contact Mike Isely <isely@pobox.com>"
2444                           " to get it included in the driver\n");
2445                goto fail;
2446        }
2447
2448        hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2449        pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2450                   hdw,hdw_desc->description);
2451        pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
2452                hdw_desc->description);
2453        if (hdw_desc->flag_is_experimental) {
2454                pvr2_trace(PVR2_TRACE_INFO, "**********");
2455                pvr2_trace(PVR2_TRACE_INFO,
2456                           "WARNING: Support for this device (%s) is"
2457                           " experimental.", hdw_desc->description);
2458                pvr2_trace(PVR2_TRACE_INFO,
2459                           "Important functionality might not be"
2460                           " entirely working.");
2461                pvr2_trace(PVR2_TRACE_INFO,
2462                           "Please consider contacting the driver author to"
2463                           " help with further stabilization of the driver.");
2464                pvr2_trace(PVR2_TRACE_INFO, "**********");
2465        }
2466        if (!hdw) goto fail;
2467
2468        init_timer(&hdw->quiescent_timer);
2469        hdw->quiescent_timer.data = (unsigned long)hdw;
2470        hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2471
2472        init_timer(&hdw->decoder_stabilization_timer);
2473        hdw->decoder_stabilization_timer.data = (unsigned long)hdw;
2474        hdw->decoder_stabilization_timer.function =
2475                pvr2_hdw_decoder_stabilization_timeout;
2476
2477        init_timer(&hdw->encoder_wait_timer);
2478        hdw->encoder_wait_timer.data = (unsigned long)hdw;
2479        hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2480
2481        init_timer(&hdw->encoder_run_timer);
2482        hdw->encoder_run_timer.data = (unsigned long)hdw;
2483        hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2484
2485        hdw->master_state = PVR2_STATE_DEAD;
2486
2487        init_waitqueue_head(&hdw->state_wait_data);
2488
2489        hdw->tuner_signal_stale = !0;
2490        cx2341x_fill_defaults(&hdw->enc_ctl_state);
2491
2492        /* Calculate which inputs are OK */
2493        m = 0;
2494        if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2495        if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2496                m |= 1 << PVR2_CVAL_INPUT_DTV;
2497        }
2498        if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2499        if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2500        if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2501        hdw->input_avail_mask = m;
2502        hdw->input_allowed_mask = hdw->input_avail_mask;
2503
2504        /* If not a hybrid device, pathway_state never changes.  So
2505           initialize it here to what it should forever be. */
2506        if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2507                hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2508        } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2509                hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2510        }
2511
2512        hdw->control_cnt = CTRLDEF_COUNT;
2513        hdw->control_cnt += MPEGDEF_COUNT;
2514        hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2515                                GFP_KERNEL);
2516        if (!hdw->controls) goto fail;
2517        hdw->hdw_desc = hdw_desc;
2518        hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
2519        for (idx = 0; idx < hdw->control_cnt; idx++) {
2520                cptr = hdw->controls + idx;
2521                cptr->hdw = hdw;
2522        }
2523        for (idx = 0; idx < 32; idx++) {
2524                hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2525        }
2526        for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2527                cptr = hdw->controls + idx;
2528                cptr->info = control_defs+idx;
2529        }
2530
2531        /* Ensure that default input choice is a valid one. */
2532        m = hdw->input_avail_mask;
2533        if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2534                if (!((1 << idx) & m)) continue;
2535                hdw->input_val = idx;
2536                break;
2537        }
2538
2539        /* Define and configure additional controls from cx2341x module. */
2540        hdw->mpeg_ctrl_info = kzalloc(
2541                sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2542        if (!hdw->mpeg_ctrl_info) goto fail;
2543        for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2544                cptr = hdw->controls + idx + CTRLDEF_COUNT;
2545                ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2546                ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2547                ciptr->name = mpeg_ids[idx].strid;
2548                ciptr->v4l_id = mpeg_ids[idx].id;
2549                ciptr->skip_init = !0;
2550                ciptr->get_value = ctrl_cx2341x_get;
2551                ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2552                ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2553                if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2554                qctrl.id = ciptr->v4l_id;
2555                cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2556                if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2557                        ciptr->set_value = ctrl_cx2341x_set;
2558                }
2559                strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2560                        PVR2_CTLD_INFO_DESC_SIZE);
2561                hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2562                ciptr->default_value = qctrl.default_value;
2563                switch (qctrl.type) {
2564                default:
2565                case V4L2_CTRL_TYPE_INTEGER:
2566                        ciptr->type = pvr2_ctl_int;
2567                        ciptr->def.type_int.min_value = qctrl.minimum;
2568                        ciptr->def.type_int.max_value = qctrl.maximum;
2569                        break;
2570                case V4L2_CTRL_TYPE_BOOLEAN:
2571                        ciptr->type = pvr2_ctl_bool;
2572                        break;
2573                case V4L2_CTRL_TYPE_MENU:
2574                        ciptr->type = pvr2_ctl_enum;
2575                        ciptr->def.type_enum.value_names =
2576                                cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2577                                                                ciptr->v4l_id);
2578                        for (cnt1 = 0;
2579                             ciptr->def.type_enum.value_names[cnt1] != NULL;
2580                             cnt1++) { }
2581                        ciptr->def.type_enum.count = cnt1;
2582                        break;
2583                }
2584                cptr->info = ciptr;
2585        }
2586
2587        // Initialize video standard enum dynamic control
2588        cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2589        if (cptr) {
2590                memcpy(&hdw->std_info_enum,cptr->info,
2591                       sizeof(hdw->std_info_enum));
2592                cptr->info = &hdw->std_info_enum;
2593
2594        }
2595        // Initialize control data regarding video standard masks
2596        valid_std_mask = pvr2_std_get_usable();
2597        for (idx = 0; idx < 32; idx++) {
2598                if (!(valid_std_mask & (1 << idx))) continue;
2599                cnt1 = pvr2_std_id_to_str(
2600                        hdw->std_mask_names[idx],
2601                        sizeof(hdw->std_mask_names[idx])-1,
2602                        1 << idx);
2603                hdw->std_mask_names[idx][cnt1] = 0;
2604        }
2605        cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2606        if (cptr) {
2607                memcpy(&hdw->std_info_avail,cptr->info,
2608                       sizeof(hdw->std_info_avail));
2609                cptr->info = &hdw->std_info_avail;
2610                hdw->std_info_avail.def.type_bitmask.bit_names =
2611                        hdw->std_mask_ptrs;
2612                hdw->std_info_avail.def.type_bitmask.valid_bits =
2613                        valid_std_mask;
2614        }
2615        cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2616        if (cptr) {
2617                memcpy(&hdw->std_info_cur,cptr->info,
2618                       sizeof(hdw->std_info_cur));
2619                cptr->info = &hdw->std_info_cur;
2620                hdw->std_info_cur.def.type_bitmask.bit_names =
2621                        hdw->std_mask_ptrs;
2622                hdw->std_info_avail.def.type_bitmask.valid_bits =
2623                        valid_std_mask;
2624        }
2625
2626        hdw->cropcap_stale = !0;
2627        hdw->eeprom_addr = -1;
2628        hdw->unit_number = -1;
2629        hdw->v4l_minor_number_video = -1;
2630        hdw->v4l_minor_number_vbi = -1;
2631        hdw->v4l_minor_number_radio = -1;
2632        hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2633        if (!hdw->ctl_write_buffer) goto fail;
2634        hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2635        if (!hdw->ctl_read_buffer) goto fail;
2636        hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2637        if (!hdw->ctl_write_urb) goto fail;
2638        hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2639        if (!hdw->ctl_read_urb) goto fail;
2640
2641        if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
2642                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2643                           "Error registering with v4l core, giving up");
2644                goto fail;
2645        }
2646        mutex_lock(&pvr2_unit_mtx); do {
2647                for (idx = 0; idx < PVR_NUM; idx++) {
2648                        if (unit_pointers[idx]) continue;
2649                        hdw->unit_number = idx;
2650                        unit_pointers[idx] = hdw;
2651                        break;
2652                }
2653        } while (0); mutex_unlock(&pvr2_unit_mtx);
2654
2655        cnt1 = 0;
2656        cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2657        cnt1 += cnt2;
2658        if (hdw->unit_number >= 0) {
2659                cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2660                                 ('a' + hdw->unit_number));
2661                cnt1 += cnt2;
2662        }
2663        if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2664        hdw->name[cnt1] = 0;
2665
2666        hdw->workqueue = create_singlethread_workqueue(hdw->name);
2667        INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2668
2669        pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2670                   hdw->unit_number,hdw->name);
2671
2672        hdw->tuner_type = -1;
2673        hdw->flag_ok = !0;
2674
2675        hdw->usb_intf = intf;
2676        hdw->usb_dev = usb_dev;
2677
2678        usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2679
2680        ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2681        usb_set_interface(hdw->usb_dev,ifnum,0);
2682
2683        mutex_init(&hdw->ctl_lock_mutex);
2684        mutex_init(&hdw->big_lock_mutex);
2685
2686        return hdw;
2687 fail:
2688        if (hdw) {
2689                del_timer_sync(&hdw->quiescent_timer);
2690                del_timer_sync(&hdw->decoder_stabilization_timer);
2691                del_timer_sync(&hdw->encoder_run_timer);
2692                del_timer_sync(&hdw->encoder_wait_timer);
2693                if (hdw->workqueue) {
2694                        flush_workqueue(hdw->workqueue);
2695                        destroy_workqueue(hdw->workqueue);
2696                        hdw->workqueue = NULL;
2697                }
2698                usb_free_urb(hdw->ctl_read_urb);
2699                usb_free_urb(hdw->ctl_write_urb);
2700                kfree(hdw->ctl_read_buffer);
2701                kfree(hdw->ctl_write_buffer);
2702                kfree(hdw->controls);
2703                kfree(hdw->mpeg_ctrl_info);
2704                kfree(hdw->std_defs);
2705                kfree(hdw->std_enum_names);
2706                kfree(hdw);
2707        }
2708        return NULL;
2709}
2710
2711
2712/* Remove _all_ associations between this driver and the underlying USB
2713   layer. */
2714static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2715{
2716        if (hdw->flag_disconnected) return;
2717        pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2718        if (hdw->ctl_read_urb) {
2719                usb_kill_urb(hdw->ctl_read_urb);
2720                usb_free_urb(hdw->ctl_read_urb);
2721                hdw->ctl_read_urb = NULL;
2722        }
2723        if (hdw->ctl_write_urb) {
2724                usb_kill_urb(hdw->ctl_write_urb);
2725                usb_free_urb(hdw->ctl_write_urb);
2726                hdw->ctl_write_urb = NULL;
2727        }
2728        if (hdw->ctl_read_buffer) {
2729                kfree(hdw->ctl_read_buffer);
2730                hdw->ctl_read_buffer = NULL;
2731        }
2732        if (hdw->ctl_write_buffer) {
2733                kfree(hdw->ctl_write_buffer);
2734                hdw->ctl_write_buffer = NULL;
2735        }
2736        hdw->flag_disconnected = !0;
2737        /* If we don't do this, then there will be a dangling struct device
2738           reference to our disappearing device persisting inside the V4L
2739           core... */
2740        v4l2_device_disconnect(&hdw->v4l2_dev);
2741        hdw->usb_dev = NULL;
2742        hdw->usb_intf = NULL;
2743        pvr2_hdw_render_useless(hdw);
2744}
2745
2746
2747/* Destroy hardware interaction structure */
2748void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2749{
2750        if (!hdw) return;
2751        pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2752        if (hdw->workqueue) {
2753                flush_workqueue(hdw->workqueue);
2754                destroy_workqueue(hdw->workqueue);
2755                hdw->workqueue = NULL;
2756        }
2757        del_timer_sync(&hdw->quiescent_timer);
2758        del_timer_sync(&hdw->decoder_stabilization_timer);
2759        del_timer_sync(&hdw->encoder_run_timer);
2760        del_timer_sync(&hdw->encoder_wait_timer);
2761        if (hdw->fw_buffer) {
2762                kfree(hdw->fw_buffer);
2763                hdw->fw_buffer = NULL;
2764        }
2765        if (hdw->vid_stream) {
2766                pvr2_stream_destroy(hdw->vid_stream);
2767                hdw->vid_stream = NULL;
2768        }
2769        pvr2_i2c_core_done(hdw);
2770        v4l2_device_unregister(&hdw->v4l2_dev);
2771        pvr2_hdw_remove_usb_stuff(hdw);
2772        mutex_lock(&pvr2_unit_mtx); do {
2773                if ((hdw->unit_number >= 0) &&
2774                    (hdw->unit_number < PVR_NUM) &&
2775                    (unit_pointers[hdw->unit_number] == hdw)) {
2776                        unit_pointers[hdw->unit_number] = NULL;
2777                }
2778        } while (0); mutex_unlock(&pvr2_unit_mtx);
2779        kfree(hdw->controls);
2780        kfree(hdw->mpeg_ctrl_info);
2781        kfree(hdw->std_defs);
2782        kfree(hdw->std_enum_names);
2783        kfree(hdw);
2784}
2785
2786
2787int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2788{
2789        return (hdw && hdw->flag_ok);
2790}
2791
2792
2793/* Called when hardware has been unplugged */
2794void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2795{
2796        pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2797        LOCK_TAKE(hdw->big_lock);
2798        LOCK_TAKE(hdw->ctl_lock);
2799        pvr2_hdw_remove_usb_stuff(hdw);
2800        LOCK_GIVE(hdw->ctl_lock);
2801        LOCK_GIVE(hdw->big_lock);
2802}
2803
2804
2805// Attempt to autoselect an appropriate value for std_enum_cur given
2806// whatever is currently in std_mask_cur
2807static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2808{
2809        unsigned int idx;
2810        for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2811                if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2812                        hdw->std_enum_cur = idx;
2813                        return;
2814                }
2815        }
2816        hdw->std_enum_cur = 0;
2817}
2818
2819
2820// Calculate correct set of enumerated standards based on currently known
2821// set of available standards bits.
2822static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2823{
2824        struct v4l2_standard *newstd;
2825        unsigned int std_cnt;
2826        unsigned int idx;
2827
2828        newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2829
2830        if (hdw->std_defs) {
2831                kfree(hdw->std_defs);
2832                hdw->std_defs = NULL;
2833        }
2834        hdw->std_enum_cnt = 0;
2835        if (hdw->std_enum_names) {
2836                kfree(hdw->std_enum_names);
2837                hdw->std_enum_names = NULL;
2838        }
2839
2840        if (!std_cnt) {
2841                pvr2_trace(
2842                        PVR2_TRACE_ERROR_LEGS,
2843                        "WARNING: Failed to identify any viable standards");
2844        }
2845        hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2846        hdw->std_enum_names[0] = "none";
2847        for (idx = 0; idx < std_cnt; idx++) {
2848                hdw->std_enum_names[idx+1] =
2849                        newstd[idx].name;
2850        }
2851        // Set up the dynamic control for this standard
2852        hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2853        hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2854        hdw->std_defs = newstd;
2855        hdw->std_enum_cnt = std_cnt+1;
2856        hdw->std_enum_cur = 0;
2857        hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2858}
2859
2860
2861int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2862                               struct v4l2_standard *std,
2863                               unsigned int idx)
2864{
2865        int ret = -EINVAL;
2866        if (!idx) return ret;
2867        LOCK_TAKE(hdw->big_lock); do {
2868                if (idx >= hdw->std_enum_cnt) break;
2869                idx--;
2870                memcpy(std,hdw->std_defs+idx,sizeof(*std));
2871                ret = 0;
2872        } while (0); LOCK_GIVE(hdw->big_lock);
2873        return ret;
2874}
2875
2876
2877/* Get the number of defined controls */
2878unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2879{
2880        return hdw->control_cnt;
2881}
2882
2883
2884/* Retrieve a control handle given its index (0..count-1) */
2885struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2886                                             unsigned int idx)
2887{
2888        if (idx >= hdw->control_cnt) return NULL;
2889        return hdw->controls + idx;
2890}
2891
2892
2893/* Retrieve a control handle given its index (0..count-1) */
2894struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2895                                          unsigned int ctl_id)
2896{
2897        struct pvr2_ctrl *cptr;
2898        unsigned int idx;
2899        int i;
2900
2901        /* This could be made a lot more efficient, but for now... */
2902        for (idx = 0; idx < hdw->control_cnt; idx++) {
2903                cptr = hdw->controls + idx;
2904                i = cptr->info->internal_id;
2905                if (i && (i == ctl_id)) return cptr;
2906        }
2907        return NULL;
2908}
2909
2910
2911/* Given a V4L ID, retrieve the control structure associated with it. */
2912struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2913{
2914        struct pvr2_ctrl *cptr;
2915        unsigned int idx;
2916        int i;
2917
2918        /* This could be made a lot more efficient, but for now... */
2919        for (idx = 0; idx < hdw->control_cnt; idx++) {
2920                cptr = hdw->controls + idx;
2921                i = cptr->info->v4l_id;
2922                if (i && (i == ctl_id)) return cptr;
2923        }
2924        return NULL;
2925}
2926
2927
2928/* Given a V4L ID for its immediate predecessor, retrieve the control
2929   structure associated with it. */
2930struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2931                                            unsigned int ctl_id)
2932{
2933        struct pvr2_ctrl *cptr,*cp2;
2934        unsigned int idx;
2935        int i;
2936
2937        /* This could be made a lot more efficient, but for now... */
2938        cp2 = NULL;
2939        for (idx = 0; idx < hdw->control_cnt; idx++) {
2940                cptr = hdw->controls + idx;
2941                i = cptr->info->v4l_id;
2942                if (!i) continue;
2943                if (i <= ctl_id) continue;
2944                if (cp2 && (cp2->info->v4l_id < i)) continue;
2945                cp2 = cptr;
2946        }
2947        return cp2;
2948        return NULL;
2949}
2950
2951
2952static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2953{
2954        switch (tp) {
2955        case pvr2_ctl_int: return "integer";
2956        case pvr2_ctl_enum: return "enum";
2957        case pvr2_ctl_bool: return "boolean";
2958        case pvr2_ctl_bitmask: return "bitmask";
2959        }
2960        return "";
2961}
2962
2963
2964static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2965                                    const char *name, int val)
2966{
2967        struct v4l2_control ctrl;
2968        pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2969        memset(&ctrl, 0, sizeof(ctrl));
2970        ctrl.id = id;
2971        ctrl.value = val;
2972        v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2973}
2974
2975#define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2976        if ((hdw)->lab##_dirty || (hdw)->force_dirty) {         \
2977                pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2978        }
2979
2980/* Execute whatever commands are required to update the state of all the
2981   sub-devices so that they match our current control values. */
2982static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2983{
2984        struct v4l2_subdev *sd;
2985        unsigned int id;
2986        pvr2_subdev_update_func fp;
2987
2988        pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2989
2990        if (hdw->tuner_updated || hdw->force_dirty) {
2991                struct tuner_setup setup;
2992                pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2993                           hdw->tuner_type);
2994                if (((int)(hdw->tuner_type)) >= 0) {
2995                        memset(&setup, 0, sizeof(setup));
2996                        setup.addr = ADDR_UNSET;
2997                        setup.type = hdw->tuner_type;
2998                        setup.mode_mask = T_RADIO | T_ANALOG_TV;
2999                        v4l2_device_call_all(&hdw->v4l2_dev, 0,
3000                                             tuner, s_type_addr, &setup);
3001                }
3002        }
3003
3004        if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
3005                pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
3006                if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3007                        v4l2_device_call_all(&hdw->v4l2_dev, 0,
3008                                             tuner, s_radio);
3009                } else {
3010                        v4l2_std_id vs;
3011                        vs = hdw->std_mask_cur;
3012                        v4l2_device_call_all(&hdw->v4l2_dev, 0,
3013                                             core, s_std, vs);
3014                        pvr2_hdw_cx25840_vbi_hack(hdw);
3015                }
3016                hdw->tuner_signal_stale = !0;
3017                hdw->cropcap_stale = !0;
3018        }
3019
3020        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
3021        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
3022        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
3023        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
3024        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
3025        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
3026        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
3027        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
3028        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
3029
3030        if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
3031                struct v4l2_tuner vt;
3032                memset(&vt, 0, sizeof(vt));
3033                vt.audmode = hdw->audiomode_val;
3034                v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
3035        }
3036
3037        if (hdw->freqDirty || hdw->force_dirty) {
3038                unsigned long fv;
3039                struct v4l2_frequency freq;
3040                fv = pvr2_hdw_get_cur_freq(hdw);
3041                pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
3042                if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
3043                memset(&freq, 0, sizeof(freq));
3044                if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
3045                        /* ((fv * 1000) / 62500) */
3046                        freq.frequency = (fv * 2) / 125;
3047                } else {
3048                        freq.frequency = fv / 62500;
3049                }
3050                /* tuner-core currently doesn't seem to care about this, but
3051                   let's set it anyway for completeness. */
3052                if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3053                        freq.type = V4L2_TUNER_RADIO;
3054                } else {
3055                        freq.type = V4L2_TUNER_ANALOG_TV;
3056                }
3057                freq.tuner = 0;
3058                v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
3059                                     s_frequency, &freq);
3060        }
3061
3062        if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
3063                struct v4l2_mbus_framefmt fmt;
3064                memset(&fmt, 0, sizeof(fmt));
3065                fmt.width = hdw->res_hor_val;
3066                fmt.height = hdw->res_ver_val;
3067                fmt.code = V4L2_MBUS_FMT_FIXED;
3068                pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
3069                           fmt.width, fmt.height);
3070                v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_mbus_fmt, &fmt);
3071        }
3072
3073        if (hdw->srate_dirty || hdw->force_dirty) {
3074                u32 val;
3075                pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
3076                           hdw->srate_val);
3077                switch (hdw->srate_val) {
3078                default:
3079                case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
3080                        val = 48000;
3081                        break;
3082                case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
3083                        val = 44100;
3084                        break;
3085                case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3086                        val = 32000;
3087                        break;
3088                }
3089                v4l2_device_call_all(&hdw->v4l2_dev, 0,
3090                                     audio, s_clock_freq, val);
3091        }
3092
3093        /* Unable to set crop parameters; there is apparently no equivalent
3094           for VIDIOC_S_CROP */
3095
3096        v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3097                id = sd->grp_id;
3098                if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3099                fp = pvr2_module_update_functions[id];
3100                if (!fp) continue;
3101                (*fp)(hdw, sd);
3102        }
3103
3104        if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
3105                pvr2_hdw_status_poll(hdw);
3106        }
3107}
3108
3109
3110/* Figure out if we need to commit control changes.  If so, mark internal
3111   state flags to indicate this fact and return true.  Otherwise do nothing
3112   else and return false. */
3113static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
3114{
3115        unsigned int idx;
3116        struct pvr2_ctrl *cptr;
3117        int value;
3118        int commit_flag = hdw->force_dirty;
3119        char buf[100];
3120        unsigned int bcnt,ccnt;
3121
3122        for (idx = 0; idx < hdw->control_cnt; idx++) {
3123                cptr = hdw->controls + idx;
3124                if (!cptr->info->is_dirty) continue;
3125                if (!cptr->info->is_dirty(cptr)) continue;
3126                commit_flag = !0;
3127
3128                if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
3129                bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3130                                 cptr->info->name);
3131                value = 0;
3132                cptr->info->get_value(cptr,&value);
3133                pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3134                                                buf+bcnt,
3135                                                sizeof(buf)-bcnt,&ccnt);
3136                bcnt += ccnt;
3137                bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3138                                  get_ctrl_typename(cptr->info->type));
3139                pvr2_trace(PVR2_TRACE_CTL,
3140                           "/*--TRACE_COMMIT--*/ %.*s",
3141                           bcnt,buf);
3142        }
3143
3144        if (!commit_flag) {
3145                /* Nothing has changed */
3146                return 0;
3147        }
3148
3149        hdw->state_pipeline_config = 0;
3150        trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3151        pvr2_hdw_state_sched(hdw);
3152
3153        return !0;
3154}
3155
3156
3157/* Perform all operations needed to commit all control changes.  This must
3158   be performed in synchronization with the pipeline state and is thus
3159   expected to be called as part of the driver's worker thread.  Return
3160   true if commit successful, otherwise return false to indicate that
3161   commit isn't possible at this time. */
3162static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3163{
3164        unsigned int idx;
3165        struct pvr2_ctrl *cptr;
3166        int disruptive_change;
3167
3168        /* Handle some required side effects when the video standard is
3169           changed.... */
3170        if (hdw->std_dirty) {
3171                int nvres;
3172                int gop_size;
3173                if (hdw->std_mask_cur & V4L2_STD_525_60) {
3174                        nvres = 480;
3175                        gop_size = 15;
3176                } else {
3177                        nvres = 576;
3178                        gop_size = 12;
3179                }
3180                /* Rewrite the vertical resolution to be appropriate to the
3181                   video standard that has been selected. */
3182                if (nvres != hdw->res_ver_val) {
3183                        hdw->res_ver_val = nvres;
3184                        hdw->res_ver_dirty = !0;
3185                }
3186                /* Rewrite the GOP size to be appropriate to the video
3187                   standard that has been selected. */
3188                if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3189                        struct v4l2_ext_controls cs;
3190                        struct v4l2_ext_control c1;
3191                        memset(&cs, 0, sizeof(cs));
3192                        memset(&c1, 0, sizeof(c1));
3193                        cs.controls = &c1;
3194                        cs.count = 1;
3195                        c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3196                        c1.value = gop_size;
3197                        cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3198                                          VIDIOC_S_EXT_CTRLS);
3199                }
3200        }
3201
3202        if (hdw->input_dirty && hdw->state_pathway_ok &&
3203            (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3204              PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3205             hdw->pathway_state)) {
3206                /* Change of mode being asked for... */
3207                hdw->state_pathway_ok = 0;
3208                trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
3209        }
3210        if (!hdw->state_pathway_ok) {
3211                /* Can't commit anything until pathway is ok. */
3212                return 0;
3213        }
3214        /* The broadcast decoder can only scale down, so if
3215         * res_*_dirty && crop window < output format ==> enlarge crop.
3216         *
3217         * The mpeg encoder receives fields of res_hor_val dots and
3218         * res_ver_val halflines.  Limits: hor<=720, ver<=576.
3219         */
3220        if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3221                hdw->cropw_val = hdw->res_hor_val;
3222                hdw->cropw_dirty = !0;
3223        } else if (hdw->cropw_dirty) {
3224                hdw->res_hor_dirty = !0;           /* must rescale */
3225                hdw->res_hor_val = min(720, hdw->cropw_val);
3226        }
3227        if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3228                hdw->croph_val = hdw->res_ver_val;
3229                hdw->croph_dirty = !0;
3230        } else if (hdw->croph_dirty) {
3231                int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3232                hdw->res_ver_dirty = !0;
3233                hdw->res_ver_val = min(nvres, hdw->croph_val);
3234        }
3235
3236        /* If any of the below has changed, then we can't do the update
3237           while the pipeline is running.  Pipeline must be paused first
3238           and decoder -> encoder connection be made quiescent before we
3239           can proceed. */
3240        disruptive_change =
3241                (hdw->std_dirty ||
3242                 hdw->enc_unsafe_stale ||
3243                 hdw->srate_dirty ||
3244                 hdw->res_ver_dirty ||
3245                 hdw->res_hor_dirty ||
3246                 hdw->cropw_dirty ||
3247                 hdw->croph_dirty ||
3248                 hdw->input_dirty ||
3249                 (hdw->active_stream_type != hdw->desired_stream_type));
3250        if (disruptive_change && !hdw->state_pipeline_idle) {
3251                /* Pipeline is not idle; we can't proceed.  Arrange to
3252                   cause pipeline to stop so that we can try this again
3253                   later.... */
3254                hdw->state_pipeline_pause = !0;
3255                return 0;
3256        }
3257
3258        if (hdw->srate_dirty) {
3259                /* Write new sample rate into control structure since
3260                 * the master copy is stale.  We must track srate
3261                 * separate from the mpeg control structure because
3262                 * other logic also uses this value. */
3263                struct v4l2_ext_controls cs;
3264                struct v4l2_ext_control c1;
3265                memset(&cs,0,sizeof(cs));
3266                memset(&c1,0,sizeof(c1));
3267                cs.controls = &c1;
3268                cs.count = 1;
3269                c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3270                c1.value = hdw->srate_val;
3271                cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3272        }
3273
3274        if (hdw->active_stream_type != hdw->desired_stream_type) {
3275                /* Handle any side effects of stream config here */
3276                hdw->active_stream_type = hdw->desired_stream_type;
3277        }
3278
3279        if (hdw->hdw_desc->signal_routing_scheme ==
3280            PVR2_ROUTING_SCHEME_GOTVIEW) {
3281                u32 b;
3282                /* Handle GOTVIEW audio switching */
3283                pvr2_hdw_gpio_get_out(hdw,&b);
3284                if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3285                        /* Set GPIO 11 */
3286                        pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3287                } else {
3288                        /* Clear GPIO 11 */
3289                        pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3290                }
3291        }
3292
3293        /* Check and update state for all sub-devices. */
3294        pvr2_subdev_update(hdw);
3295
3296        hdw->tuner_updated = 0;
3297        hdw->force_dirty = 0;
3298        for (idx = 0; idx < hdw->control_cnt; idx++) {
3299                cptr = hdw->controls + idx;
3300                if (!cptr->info->clear_dirty) continue;
3301                cptr->info->clear_dirty(cptr);
3302        }
3303
3304        if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3305            hdw->state_encoder_run) {
3306                /* If encoder isn't running or it can't be touched, then
3307                   this will get worked out later when we start the
3308                   encoder. */
3309                if (pvr2_encoder_adjust(hdw) < 0) return !0;
3310        }
3311
3312        hdw->state_pipeline_config = !0;
3313        /* Hardware state may have changed in a way to cause the cropping
3314           capabilities to have changed.  So mark it stale, which will
3315           cause a later re-fetch. */
3316        trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3317        return !0;
3318}
3319
3320
3321int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3322{
3323        int fl;
3324        LOCK_TAKE(hdw->big_lock);
3325        fl = pvr2_hdw_commit_setup(hdw);
3326        LOCK_GIVE(hdw->big_lock);
3327        if (!fl) return 0;
3328        return pvr2_hdw_wait(hdw,0);
3329}
3330
3331
3332static void pvr2_hdw_worker_poll(struct work_struct *work)
3333{
3334        int fl = 0;
3335        struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3336        LOCK_TAKE(hdw->big_lock); do {
3337                fl = pvr2_hdw_state_eval(hdw);
3338        } while (0); LOCK_GIVE(hdw->big_lock);
3339        if (fl && hdw->state_func) {
3340                hdw->state_func(hdw->state_data);
3341        }
3342}
3343
3344
3345static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3346{
3347        return wait_event_interruptible(
3348                hdw->state_wait_data,
3349                (hdw->state_stale == 0) &&
3350                (!state || (hdw->master_state != state)));
3351}
3352
3353
3354/* Return name for this driver instance */
3355const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3356{
3357        return hdw->name;
3358}
3359
3360
3361const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3362{
3363        return hdw->hdw_desc->description;
3364}
3365
3366
3367const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3368{
3369        return hdw->hdw_desc->shortname;
3370}
3371
3372
3373int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3374{
3375        int result;
3376        LOCK_TAKE(hdw->ctl_lock); do {
3377                hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3378                result = pvr2_send_request(hdw,
3379                                           hdw->cmd_buffer,1,
3380                                           hdw->cmd_buffer,1);
3381                if (result < 0) break;
3382                result = (hdw->cmd_buffer[0] != 0);
3383        } while(0); LOCK_GIVE(hdw->ctl_lock);
3384        return result;
3385}
3386
3387
3388/* Execute poll of tuner status */
3389void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3390{
3391        LOCK_TAKE(hdw->big_lock); do {
3392                pvr2_hdw_status_poll(hdw);
3393        } while (0); LOCK_GIVE(hdw->big_lock);
3394}
3395
3396
3397static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3398{
3399        if (!hdw->cropcap_stale) {
3400                return 0;
3401        }
3402        pvr2_hdw_status_poll(hdw);
3403        if (hdw->cropcap_stale) {
3404                return -EIO;
3405        }
3406        return 0;
3407}
3408
3409
3410/* Return information about cropping capabilities */
3411int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3412{
3413        int stat = 0;
3414        LOCK_TAKE(hdw->big_lock);
3415        stat = pvr2_hdw_check_cropcap(hdw);
3416        if (!stat) {
3417                memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3418        }
3419        LOCK_GIVE(hdw->big_lock);
3420        return stat;
3421}
3422
3423
3424/* Return information about the tuner */
3425int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3426{
3427        LOCK_TAKE(hdw->big_lock); do {
3428                if (hdw->tuner_signal_stale) {
3429                        pvr2_hdw_status_poll(hdw);
3430                }
3431                memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3432        } while (0); LOCK_GIVE(hdw->big_lock);
3433        return 0;
3434}
3435
3436
3437/* Get handle to video output stream */
3438struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3439{
3440        return hp->vid_stream;
3441}
3442
3443
3444void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3445{
3446        int nr = pvr2_hdw_get_unit_number(hdw);
3447        LOCK_TAKE(hdw->big_lock); do {
3448                printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3449                v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3450                pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3451                cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3452                pvr2_hdw_state_log_state(hdw);
3453                printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3454        } while (0); LOCK_GIVE(hdw->big_lock);
3455}
3456
3457
3458/* Grab EEPROM contents, needed for direct method. */
3459#define EEPROM_SIZE 8192
3460#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3461static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3462{
3463        struct i2c_msg msg[2];
3464        u8 *eeprom;
3465        u8 iadd[2];
3466        u8 addr;
3467        u16 eepromSize;
3468        unsigned int offs;
3469        int ret;
3470        int mode16 = 0;
3471        unsigned pcnt,tcnt;
3472        eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3473        if (!eeprom) {
3474                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3475                           "Failed to allocate memory"
3476                           " required to read eeprom");
3477                return NULL;
3478        }
3479
3480        trace_eeprom("Value for eeprom addr from controller was 0x%x",
3481                     hdw->eeprom_addr);
3482        addr = hdw->eeprom_addr;
3483        /* Seems that if the high bit is set, then the *real* eeprom
3484           address is shifted right now bit position (noticed this in
3485           newer PVR USB2 hardware) */
3486        if (addr & 0x80) addr >>= 1;
3487
3488        /* FX2 documentation states that a 16bit-addressed eeprom is
3489           expected if the I2C address is an odd number (yeah, this is
3490           strange but it's what they do) */
3491        mode16 = (addr & 1);
3492        eepromSize = (mode16 ? EEPROM_SIZE : 256);
3493        trace_eeprom("Examining %d byte eeprom at location 0x%x"
3494                     " using %d bit addressing",eepromSize,addr,
3495                     mode16 ? 16 : 8);
3496
3497        msg[0].addr = addr;
3498        msg[0].flags = 0;
3499        msg[0].len = mode16 ? 2 : 1;
3500        msg[0].buf = iadd;
3501        msg[1].addr = addr;
3502        msg[1].flags = I2C_M_RD;
3503
3504        /* We have to do the actual eeprom data fetch ourselves, because
3505           (1) we're only fetching part of the eeprom, and (2) if we were
3506           getting the whole thing our I2C driver can't grab it in one
3507           pass - which is what tveeprom is otherwise going to attempt */
3508        memset(eeprom,0,EEPROM_SIZE);
3509        for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3510                pcnt = 16;
3511                if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3512                offs = tcnt + (eepromSize - EEPROM_SIZE);
3513                if (mode16) {
3514                        iadd[0] = offs >> 8;
3515                        iadd[1] = offs;
3516                } else {
3517                        iadd[0] = offs;
3518                }
3519                msg[1].len = pcnt;
3520                msg[1].buf = eeprom+tcnt;
3521                if ((ret = i2c_transfer(&hdw->i2c_adap,
3522                                        msg,ARRAY_SIZE(msg))) != 2) {
3523                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3524                                   "eeprom fetch set offs err=%d",ret);
3525                        kfree(eeprom);
3526                        return NULL;
3527                }
3528        }
3529        return eeprom;
3530}
3531
3532
3533void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3534                                int mode,
3535                                int enable_flag)
3536{
3537        int ret;
3538        u16 address;
3539        unsigned int pipe;
3540        LOCK_TAKE(hdw->big_lock); do {
3541                if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3542
3543                if (!enable_flag) {
3544                        pvr2_trace(PVR2_TRACE_FIRMWARE,
3545                                   "Cleaning up after CPU firmware fetch");
3546                        kfree(hdw->fw_buffer);
3547                        hdw->fw_buffer = NULL;
3548                        hdw->fw_size = 0;
3549                        if (hdw->fw_cpu_flag) {
3550                                /* Now release the CPU.  It will disconnect
3551                                   and reconnect later. */
3552                                pvr2_hdw_cpureset_assert(hdw,0);
3553                        }
3554                        break;
3555                }
3556
3557                hdw->fw_cpu_flag = (mode != 2);
3558                if (hdw->fw_cpu_flag) {
3559                        hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
3560                        pvr2_trace(PVR2_TRACE_FIRMWARE,
3561                                   "Preparing to suck out CPU firmware"
3562                                   " (size=%u)", hdw->fw_size);
3563                        hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3564                        if (!hdw->fw_buffer) {
3565                                hdw->fw_size = 0;
3566                                break;
3567                        }
3568
3569                        /* We have to hold the CPU during firmware upload. */
3570                        pvr2_hdw_cpureset_assert(hdw,1);
3571
3572                        /* download the firmware from address 0000-1fff in 2048
3573                           (=0x800) bytes chunk. */
3574
3575                        pvr2_trace(PVR2_TRACE_FIRMWARE,
3576                                   "Grabbing CPU firmware");
3577                        pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3578                        for(address = 0; address < hdw->fw_size;
3579                            address += 0x800) {
3580                                ret = usb_control_msg(hdw->usb_dev,pipe,
3581                                                      0xa0,0xc0,
3582                                                      address,0,
3583                                                      hdw->fw_buffer+address,
3584                                                      0x800,HZ);
3585                                if (ret < 0) break;
3586                        }
3587
3588                        pvr2_trace(PVR2_TRACE_FIRMWARE,
3589                                   "Done grabbing CPU firmware");
3590                } else {
3591                        pvr2_trace(PVR2_TRACE_FIRMWARE,
3592                                   "Sucking down EEPROM contents");
3593                        hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3594                        if (!hdw->fw_buffer) {
3595                                pvr2_trace(PVR2_TRACE_FIRMWARE,
3596                                           "EEPROM content suck failed.");
3597                                break;
3598                        }
3599                        hdw->fw_size = EEPROM_SIZE;
3600                        pvr2_trace(PVR2_TRACE_FIRMWARE,
3601                                   "Done sucking down EEPROM contents");
3602                }
3603
3604        } while (0); LOCK_GIVE(hdw->big_lock);
3605}
3606
3607
3608/* Return true if we're in a mode for retrieval CPU firmware */
3609int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3610{
3611        return hdw->fw_buffer != NULL;
3612}
3613
3614
3615int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3616                       char *buf,unsigned int cnt)
3617{
3618        int ret = -EINVAL;
3619        LOCK_TAKE(hdw->big_lock); do {
3620                if (!buf) break;
3621                if (!cnt) break;
3622
3623                if (!hdw->fw_buffer) {
3624                        ret = -EIO;
3625                        break;
3626                }
3627
3628                if (offs >= hdw->fw_size) {
3629                        pvr2_trace(PVR2_TRACE_FIRMWARE,
3630                                   "Read firmware data offs=%d EOF",
3631                                   offs);
3632                        ret = 0;
3633                        break;
3634                }
3635
3636                if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3637
3638                memcpy(buf,hdw->fw_buffer+offs,cnt);
3639
3640                pvr2_trace(PVR2_TRACE_FIRMWARE,
3641                           "Read firmware data offs=%d cnt=%d",
3642                           offs,cnt);
3643                ret = cnt;
3644        } while (0); LOCK_GIVE(hdw->big_lock);
3645
3646        return ret;
3647}
3648
3649
3650int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3651                                  enum pvr2_v4l_type index)
3652{
3653        switch (index) {
3654        case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3655        case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3656        case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3657        default: return -1;
3658        }
3659}
3660
3661
3662/* Store a v4l minor device number */
3663void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3664                                     enum pvr2_v4l_type index,int v)
3665{
3666        switch (index) {
3667        case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3668        case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3669        case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
3670        default: break;
3671        }
3672}
3673
3674
3675static void pvr2_ctl_write_complete(struct urb *urb)
3676{
3677        struct pvr2_hdw *hdw = urb->context;
3678        hdw->ctl_write_pend_flag = 0;
3679        if (hdw->ctl_read_pend_flag) return;
3680        complete(&hdw->ctl_done);
3681}
3682
3683
3684static void pvr2_ctl_read_complete(struct urb *urb)
3685{
3686        struct pvr2_hdw *hdw = urb->context;
3687        hdw->ctl_read_pend_flag = 0;
3688        if (hdw->ctl_write_pend_flag) return;
3689        complete(&hdw->ctl_done);
3690}
3691
3692
3693static void pvr2_ctl_timeout(unsigned long data)
3694{
3695        struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3696        if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3697                hdw->ctl_timeout_flag = !0;
3698                if (hdw->ctl_write_pend_flag)
3699                        usb_unlink_urb(hdw->ctl_write_urb);
3700                if (hdw->ctl_read_pend_flag)
3701                        usb_unlink_urb(hdw->ctl_read_urb);
3702        }
3703}
3704
3705
3706/* Issue a command and get a response from the device.  This extended
3707   version includes a probe flag (which if set means that device errors
3708   should not be logged or treated as fatal) and a timeout in jiffies.
3709   This can be used to non-lethally probe the health of endpoint 1. */
3710static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3711                                unsigned int timeout,int probe_fl,
3712                                void *write_data,unsigned int write_len,
3713                                void *read_data,unsigned int read_len)
3714{
3715        unsigned int idx;
3716        int status = 0;
3717        struct timer_list timer;
3718        if (!hdw->ctl_lock_held) {
3719                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3720                           "Attempted to execute control transfer"
3721                           " without lock!!");
3722                return -EDEADLK;
3723        }
3724        if (!hdw->flag_ok && !probe_fl) {
3725                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3726                           "Attempted to execute control transfer"
3727                           " when device not ok");
3728                return -EIO;
3729        }
3730        if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3731                if (!probe_fl) {
3732                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3733                                   "Attempted to execute control transfer"
3734                                   " when USB is disconnected");
3735                }
3736                return -ENOTTY;
3737        }
3738
3739        /* Ensure that we have sane parameters */
3740        if (!write_data) write_len = 0;
3741        if (!read_data) read_len = 0;
3742        if (write_len > PVR2_CTL_BUFFSIZE) {
3743                pvr2_trace(
3744                        PVR2_TRACE_ERROR_LEGS,
3745                        "Attempted to execute %d byte"
3746                        " control-write transfer (limit=%d)",
3747                        write_len,PVR2_CTL_BUFFSIZE);
3748                return -EINVAL;
3749        }
3750        if (read_len > PVR2_CTL_BUFFSIZE) {
3751                pvr2_trace(
3752                        PVR2_TRACE_ERROR_LEGS,
3753                        "Attempted to execute %d byte"
3754                        " control-read transfer (limit=%d)",
3755                        write_len,PVR2_CTL_BUFFSIZE);
3756                return -EINVAL;
3757        }
3758        if ((!write_len) && (!read_len)) {
3759                pvr2_trace(
3760                        PVR2_TRACE_ERROR_LEGS,
3761                        "Attempted to execute null control transfer?");
3762                return -EINVAL;
3763        }
3764
3765
3766        hdw->cmd_debug_state = 1;
3767        if (write_len) {
3768                hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3769        } else {
3770                hdw->cmd_debug_code = 0;
3771        }
3772        hdw->cmd_debug_write_len = write_len;
3773        hdw->cmd_debug_read_len = read_len;
3774
3775        /* Initialize common stuff */
3776        init_completion(&hdw->ctl_done);
3777        hdw->ctl_timeout_flag = 0;
3778        hdw->ctl_write_pend_flag = 0;
3779        hdw->ctl_read_pend_flag = 0;
3780        init_timer(&timer);
3781        timer.expires = jiffies + timeout;
3782        timer.data = (unsigned long)hdw;
3783        timer.function = pvr2_ctl_timeout;
3784
3785        if (write_len) {
3786                hdw->cmd_debug_state = 2;
3787                /* Transfer write data to internal buffer */
3788                for (idx = 0; idx < write_len; idx++) {
3789                        hdw->ctl_write_buffer[idx] =
3790                                ((unsigned char *)write_data)[idx];
3791                }
3792                /* Initiate a write request */
3793                usb_fill_bulk_urb(hdw->ctl_write_urb,
3794                                  hdw->usb_dev,
3795                                  usb_sndbulkpipe(hdw->usb_dev,
3796                                                  PVR2_CTL_WRITE_ENDPOINT),
3797                                  hdw->ctl_write_buffer,
3798                                  write_len,
3799                                  pvr2_ctl_write_complete,
3800                                  hdw);
3801                hdw->ctl_write_urb->actual_length = 0;
3802                hdw->ctl_write_pend_flag = !0;
3803                status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3804                if (status < 0) {
3805                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3806                                   "Failed to submit write-control"
3807                                   " URB status=%d",status);
3808                        hdw->ctl_write_pend_flag = 0;
3809                        goto done;
3810                }
3811        }
3812
3813        if (read_len) {
3814                hdw->cmd_debug_state = 3;
3815                memset(hdw->ctl_read_buffer,0x43,read_len);
3816                /* Initiate a read request */
3817                usb_fill_bulk_urb(hdw->ctl_read_urb,
3818                                  hdw->usb_dev,
3819                                  usb_rcvbulkpipe(hdw->usb_dev,
3820                                                  PVR2_CTL_READ_ENDPOINT),
3821                                  hdw->ctl_read_buffer,
3822                                  read_len,
3823                                  pvr2_ctl_read_complete,
3824                                  hdw);
3825                hdw->ctl_read_urb->actual_length = 0;
3826                hdw->ctl_read_pend_flag = !0;
3827                status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3828                if (status < 0) {
3829                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3830                                   "Failed to submit read-control"
3831                                   " URB status=%d",status);
3832                        hdw->ctl_read_pend_flag = 0;
3833                        goto done;
3834                }
3835        }
3836
3837        /* Start timer */
3838        add_timer(&timer);
3839
3840        /* Now wait for all I/O to complete */
3841        hdw->cmd_debug_state = 4;
3842        while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3843                wait_for_completion(&hdw->ctl_done);
3844        }
3845        hdw->cmd_debug_state = 5;
3846
3847        /* Stop timer */
3848        del_timer_sync(&timer);
3849
3850        hdw->cmd_debug_state = 6;
3851        status = 0;
3852
3853        if (hdw->ctl_timeout_flag) {
3854                status = -ETIMEDOUT;
3855                if (!probe_fl) {
3856                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3857                                   "Timed out control-write");
3858                }
3859                goto done;
3860        }
3861
3862        if (write_len) {
3863                /* Validate results of write request */
3864                if ((hdw->ctl_write_urb->status != 0) &&
3865                    (hdw->ctl_write_urb->status != -ENOENT) &&
3866                    (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3867                    (hdw->ctl_write_urb->status != -ECONNRESET)) {
3868                        /* USB subsystem is reporting some kind of failure
3869                           on the write */
3870                        status = hdw->ctl_write_urb->status;
3871                        if (!probe_fl) {
3872                                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3873                                           "control-write URB failure,"
3874                                           " status=%d",
3875                                           status);
3876                        }
3877                        goto done;
3878                }
3879                if (hdw->ctl_write_urb->actual_length < write_len) {
3880                        /* Failed to write enough data */
3881                        status = -EIO;
3882                        if (!probe_fl) {
3883                                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3884                                           "control-write URB short,"
3885                                           " expected=%d got=%d",
3886                                           write_len,
3887                                           hdw->ctl_write_urb->actual_length);
3888                        }
3889                        goto done;
3890                }
3891        }
3892        if (read_len) {
3893                /* Validate results of read request */
3894                if ((hdw->ctl_read_urb->status != 0) &&
3895                    (hdw->ctl_read_urb->status != -ENOENT) &&
3896                    (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3897                    (hdw->ctl_read_urb->status != -ECONNRESET)) {
3898                        /* USB subsystem is reporting some kind of failure
3899                           on the read */
3900                        status = hdw->ctl_read_urb->status;
3901                        if (!probe_fl) {
3902                                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3903                                           "control-read URB failure,"
3904                                           " status=%d",
3905                                           status);
3906                        }
3907                        goto done;
3908                }
3909                if (hdw->ctl_read_urb->actual_length < read_len) {
3910                        /* Failed to read enough data */
3911                        status = -EIO;
3912                        if (!probe_fl) {
3913                                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3914                                           "control-read URB short,"
3915                                           " expected=%d got=%d",
3916                                           read_len,
3917                                           hdw->ctl_read_urb->actual_length);
3918                        }
3919                        goto done;
3920                }
3921                /* Transfer retrieved data out from internal buffer */
3922                for (idx = 0; idx < read_len; idx++) {
3923                        ((unsigned char *)read_data)[idx] =
3924                                hdw->ctl_read_buffer[idx];
3925                }
3926        }
3927
3928 done:
3929
3930        hdw->cmd_debug_state = 0;
3931        if ((status < 0) && (!probe_fl)) {
3932                pvr2_hdw_render_useless(hdw);
3933        }
3934        return status;
3935}
3936
3937
3938int pvr2_send_request(struct pvr2_hdw *hdw,
3939                      void *write_data,unsigned int write_len,
3940                      void *read_data,unsigned int read_len)
3941{
3942        return pvr2_send_request_ex(hdw,HZ*4,0,
3943                                    write_data,write_len,
3944                                    read_data,read_len);
3945}
3946
3947
3948static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3949{
3950        int ret;
3951        unsigned int cnt = 1;
3952        unsigned int args = 0;
3953        LOCK_TAKE(hdw->ctl_lock);
3954        hdw->cmd_buffer[0] = cmdcode & 0xffu;
3955        args = (cmdcode >> 8) & 0xffu;
3956        args = (args > 2) ? 2 : args;
3957        if (args) {
3958                cnt += args;
3959                hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3960                if (args > 1) {
3961                        hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3962                }
3963        }
3964        if (pvrusb2_debug & PVR2_TRACE_INIT) {
3965                unsigned int idx;
3966                unsigned int ccnt,bcnt;
3967                char tbuf[50];
3968                cmdcode &= 0xffu;
3969                bcnt = 0;
3970                ccnt = scnprintf(tbuf+bcnt,
3971                                 sizeof(tbuf)-bcnt,
3972                                 "Sending FX2 command 0x%x",cmdcode);
3973                bcnt += ccnt;
3974                for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3975                        if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3976                                ccnt = scnprintf(tbuf+bcnt,
3977                                                 sizeof(tbuf)-bcnt,
3978                                                 " \"%s\"",
3979                                                 pvr2_fx2cmd_desc[idx].desc);
3980                                bcnt += ccnt;
3981                                break;
3982                        }
3983                }
3984                if (args) {
3985                        ccnt = scnprintf(tbuf+bcnt,
3986                                         sizeof(tbuf)-bcnt,
3987                                         " (%u",hdw->cmd_buffer[1]);
3988                        bcnt += ccnt;
3989                        if (args > 1) {
3990                                ccnt = scnprintf(tbuf+bcnt,
3991                                                 sizeof(tbuf)-bcnt,
3992                                                 ",%u",hdw->cmd_buffer[2]);
3993                                bcnt += ccnt;
3994                        }
3995                        ccnt = scnprintf(tbuf+bcnt,
3996                                         sizeof(tbuf)-bcnt,
3997                                         ")");
3998                        bcnt += ccnt;
3999                }
4000                pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
4001        }
4002        ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
4003        LOCK_GIVE(hdw->ctl_lock);
4004        return ret;
4005}
4006
4007
4008int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
4009{
4010        int ret;
4011
4012        LOCK_TAKE(hdw->ctl_lock);
4013
4014        hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
4015        PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
4016        hdw->cmd_buffer[5] = 0;
4017        hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4018        hdw->cmd_buffer[7] = reg & 0xff;
4019
4020
4021        ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
4022
4023        LOCK_GIVE(hdw->ctl_lock);
4024
4025        return ret;
4026}
4027
4028
4029static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
4030{
4031        int ret = 0;
4032
4033        LOCK_TAKE(hdw->ctl_lock);
4034
4035        hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
4036        hdw->cmd_buffer[1] = 0;
4037        hdw->cmd_buffer[2] = 0;
4038        hdw->cmd_buffer[3] = 0;
4039        hdw->cmd_buffer[4] = 0;
4040        hdw->cmd_buffer[5] = 0;
4041        hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4042        hdw->cmd_buffer[7] = reg & 0xff;
4043
4044        ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
4045        *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
4046
4047        LOCK_GIVE(hdw->ctl_lock);
4048
4049        return ret;
4050}
4051
4052
4053void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
4054{
4055        if (!hdw->flag_ok) return;
4056        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4057                   "Device being rendered inoperable");
4058        if (hdw->vid_stream) {
4059                pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
4060        }
4061        hdw->flag_ok = 0;
4062        trace_stbit("flag_ok",hdw->flag_ok);
4063        pvr2_hdw_state_sched(hdw);
4064}
4065
4066
4067void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
4068{
4069        int ret;
4070        pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
4071        ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
4072        if (ret == 0) {
4073                ret = usb_reset_device(hdw->usb_dev);
4074                usb_unlock_device(hdw->usb_dev);
4075        } else {
4076                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4077                           "Failed to lock USB device ret=%d",ret);
4078        }
4079        if (init_pause_msec) {
4080                pvr2_trace(PVR2_TRACE_INFO,
4081                           "Waiting %u msec for hardware to settle",
4082                           init_pause_msec);
4083                msleep(init_pause_msec);
4084        }
4085
4086}
4087
4088
4089void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4090{
4091        char *da;
4092        unsigned int pipe;
4093        int ret;
4094
4095        if (!hdw->usb_dev) return;
4096
4097        da = kmalloc(16, GFP_KERNEL);
4098
4099        if (da == NULL) {
4100                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4101                           "Unable to allocate memory to control CPU reset");
4102                return;
4103        }
4104
4105        pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4106
4107        da[0] = val ? 0x01 : 0x00;
4108
4109        /* Write the CPUCS register on the 8051.  The lsb of the register
4110           is the reset bit; a 1 asserts reset while a 0 clears it. */
4111        pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4112        ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4113        if (ret < 0) {
4114                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4115                           "cpureset_assert(%d) error=%d",val,ret);
4116                pvr2_hdw_render_useless(hdw);
4117        }
4118
4119        kfree(da);
4120}
4121
4122
4123int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4124{
4125        return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
4126}
4127
4128
4129int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4130{
4131        return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
4132}
4133
4134
4135int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4136{
4137        return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
4138}
4139
4140
4141int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4142{
4143        pvr2_trace(PVR2_TRACE_INIT,
4144                   "Requesting decoder reset");
4145        if (hdw->decoder_client_id) {
4146                v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4147                                     core, reset, 0);
4148                pvr2_hdw_cx25840_vbi_hack(hdw);
4149                return 0;
4150        }
4151        pvr2_trace(PVR2_TRACE_INIT,
4152                   "Unable to reset decoder: nothing attached");
4153        return -ENOTTY;
4154}
4155
4156
4157static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4158{
4159        hdw->flag_ok = !0;
4160        return pvr2_issue_simple_cmd(hdw,
4161                                     FX2CMD_HCW_DEMOD_RESETIN |
4162                                     (1 << 8) |
4163                                     ((onoff ? 1 : 0) << 16));
4164}
4165
4166
4167static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4168{
4169        hdw->flag_ok = !0;
4170        return pvr2_issue_simple_cmd(hdw,(onoff ?
4171                                          FX2CMD_ONAIR_DTV_POWER_ON :
4172                                          FX2CMD_ONAIR_DTV_POWER_OFF));
4173}
4174
4175
4176static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4177                                                int onoff)
4178{
4179        return pvr2_issue_simple_cmd(hdw,(onoff ?
4180                                          FX2CMD_ONAIR_DTV_STREAMING_ON :
4181                                          FX2CMD_ONAIR_DTV_STREAMING_OFF));
4182}
4183
4184
4185static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4186{
4187        int cmode;
4188        /* Compare digital/analog desired setting with current setting.  If
4189           they don't match, fix it... */
4190        cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4191        if (cmode == hdw->pathway_state) {
4192                /* They match; nothing to do */
4193                return;
4194        }
4195
4196        switch (hdw->hdw_desc->digital_control_scheme) {
4197        case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4198                pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4199                if (cmode == PVR2_PATHWAY_ANALOG) {
4200                        /* If moving to analog mode, also force the decoder
4201                           to reset.  If no decoder is attached, then it's
4202                           ok to ignore this because if/when the decoder
4203                           attaches, it will reset itself at that time. */
4204                        pvr2_hdw_cmd_decoder_reset(hdw);
4205                }
4206                break;
4207        case PVR2_DIGITAL_SCHEME_ONAIR:
4208                /* Supposedly we should always have the power on whether in
4209                   digital or analog mode.  But for now do what appears to
4210                   work... */
4211                pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4212                break;
4213        default: break;
4214        }
4215
4216        pvr2_hdw_untrip_unlocked(hdw);
4217        hdw->pathway_state = cmode;
4218}
4219
4220
4221static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4222{
4223        /* change some GPIO data
4224         *
4225         * note: bit d7 of dir appears to control the LED,
4226         * so we shut it off here.
4227         *
4228         */
4229        if (onoff) {
4230                pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4231        } else {
4232                pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4233        }
4234        pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4235}
4236
4237
4238typedef void (*led_method_func)(struct pvr2_hdw *,int);
4239
4240static led_method_func led_methods[] = {
4241        [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4242};
4243
4244
4245/* Toggle LED */
4246static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4247{
4248        unsigned int scheme_id;
4249        led_method_func fp;
4250
4251        if ((!onoff) == (!hdw->led_on)) return;
4252
4253        hdw->led_on = onoff != 0;
4254
4255        scheme_id = hdw->hdw_desc->led_scheme;
4256        if (scheme_id < ARRAY_SIZE(led_methods)) {
4257                fp = led_methods[scheme_id];
4258        } else {
4259                fp = NULL;
4260        }
4261
4262        if (fp) (*fp)(hdw,onoff);
4263}
4264
4265
4266/* Stop / start video stream transport */
4267static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4268{
4269        int ret;
4270
4271        /* If we're in analog mode, then just issue the usual analog
4272           command. */
4273        if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4274                return pvr2_issue_simple_cmd(hdw,
4275                                             (runFl ?
4276                                              FX2CMD_STREAMING_ON :
4277                                              FX2CMD_STREAMING_OFF));
4278                /*Note: Not reached */
4279        }
4280
4281        if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4282                /* Whoops, we don't know what mode we're in... */
4283                return -EINVAL;
4284        }
4285
4286        /* To get here we have to be in digital mode.  The mechanism here
4287           is unfortunately different for different vendors.  So we switch
4288           on the device's digital scheme attribute in order to figure out
4289           what to do. */
4290        switch (hdw->hdw_desc->digital_control_scheme) {
4291        case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4292                return pvr2_issue_simple_cmd(hdw,
4293                                             (runFl ?
4294                                              FX2CMD_HCW_DTV_STREAMING_ON :
4295                                              FX2CMD_HCW_DTV_STREAMING_OFF));
4296        case PVR2_DIGITAL_SCHEME_ONAIR:
4297                ret = pvr2_issue_simple_cmd(hdw,
4298                                            (runFl ?
4299                                             FX2CMD_STREAMING_ON :
4300                                             FX2CMD_STREAMING_OFF));
4301                if (ret) return ret;
4302                return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4303        default:
4304                return -EINVAL;
4305        }
4306}
4307
4308
4309/* Evaluate whether or not state_pathway_ok can change */
4310static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4311{
4312        if (hdw->state_pathway_ok) {
4313                /* Nothing to do if pathway is already ok */
4314                return 0;
4315        }
4316        if (!hdw->state_pipeline_idle) {
4317                /* Not allowed to change anything if pipeline is not idle */
4318                return 0;
4319        }
4320        pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4321        hdw->state_pathway_ok = !0;
4322        trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4323        return !0;
4324}
4325
4326
4327/* Evaluate whether or not state_encoder_ok can change */
4328static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4329{
4330        if (hdw->state_encoder_ok) return 0;
4331        if (hdw->flag_tripped) return 0;
4332        if (hdw->state_encoder_run) return 0;
4333        if (hdw->state_encoder_config) return 0;
4334        if (hdw->state_decoder_run) return 0;
4335        if (hdw->state_usbstream_run) return 0;
4336        if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4337                if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4338        } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4339                return 0;
4340        }
4341
4342        if (pvr2_upload_firmware2(hdw) < 0) {
4343                hdw->flag_tripped = !0;
4344                trace_stbit("flag_tripped",hdw->flag_tripped);
4345                return !0;
4346        }
4347        hdw->state_encoder_ok = !0;
4348        trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4349        return !0;
4350}
4351
4352
4353/* Evaluate whether or not state_encoder_config can change */
4354static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4355{
4356        if (hdw->state_encoder_config) {
4357                if (hdw->state_encoder_ok) {
4358                        if (hdw->state_pipeline_req &&
4359                            !hdw->state_pipeline_pause) return 0;
4360                }
4361                hdw->state_encoder_config = 0;
4362                hdw->state_encoder_waitok = 0;
4363                trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4364                /* paranoia - solve race if timer just completed */
4365                del_timer_sync(&hdw->encoder_wait_timer);
4366        } else {
4367                if (!hdw->state_pathway_ok ||
4368                    (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4369                    !hdw->state_encoder_ok ||
4370                    !hdw->state_pipeline_idle ||
4371                    hdw->state_pipeline_pause ||
4372                    !hdw->state_pipeline_req ||
4373                    !hdw->state_pipeline_config) {
4374                        /* We must reset the enforced wait interval if
4375                           anything has happened that might have disturbed
4376                           the encoder.  This should be a rare case. */
4377                        if (timer_pending(&hdw->encoder_wait_timer)) {
4378                                del_timer_sync(&hdw->encoder_wait_timer);
4379                        }
4380                        if (hdw->state_encoder_waitok) {
4381                                /* Must clear the state - therefore we did
4382                                   something to a state bit and must also
4383                                   return true. */
4384                                hdw->state_encoder_waitok = 0;
4385                                trace_stbit("state_encoder_waitok",
4386                                            hdw->state_encoder_waitok);
4387                                return !0;
4388                        }
4389                        return 0;
4390                }
4391                if (!hdw->state_encoder_waitok) {
4392                        if (!timer_pending(&hdw->encoder_wait_timer)) {
4393                                /* waitok flag wasn't set and timer isn't
4394                                   running.  Check flag once more to avoid
4395                                   a race then start the timer.  This is
4396                                   the point when we measure out a minimal
4397                                   quiet interval before doing something to
4398                                   the encoder. */
4399                                if (!hdw->state_encoder_waitok) {
4400                                        hdw->encoder_wait_timer.expires =
4401                                                jiffies +
4402                                                (HZ * TIME_MSEC_ENCODER_WAIT
4403                                                 / 1000);
4404                                        add_timer(&hdw->encoder_wait_timer);
4405                                }
4406                        }
4407                        /* We can't continue until we know we have been
4408                           quiet for the interval measured by this
4409                           timer. */
4410                        return 0;
4411                }
4412                pvr2_encoder_configure(hdw);
4413                if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4414        }
4415        trace_stbit("state_encoder_config",hdw->state_encoder_config);
4416        return !0;
4417}
4418
4419
4420/* Return true if the encoder should not be running. */
4421static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4422{
4423        if (!hdw->state_encoder_ok) {
4424                /* Encoder isn't healthy at the moment, so stop it. */
4425                return !0;
4426        }
4427        if (!hdw->state_pathway_ok) {
4428                /* Mode is not understood at the moment (i.e. it wants to
4429                   change), so encoder must be stopped. */
4430                return !0;
4431        }
4432
4433        switch (hdw->pathway_state) {
4434        case PVR2_PATHWAY_ANALOG:
4435                if (!hdw->state_decoder_run) {
4436                        /* We're in analog mode and the decoder is not
4437                           running; thus the encoder should be stopped as
4438                           well. */
4439                        return !0;
4440                }
4441                break;
4442        case PVR2_PATHWAY_DIGITAL:
4443                if (hdw->state_encoder_runok) {
4444                        /* This is a funny case.  We're in digital mode so
4445                           really the encoder should be stopped.  However
4446                           if it really is running, only kill it after
4447                           runok has been set.  This gives a chance for the
4448                           onair quirk to function (encoder must run
4449                           briefly first, at least once, before onair
4450                           digital streaming can work). */
4451                        return !0;
4452                }
4453                break;
4454        default:
4455                /* Unknown mode; so encoder should be stopped. */
4456                return !0;
4457        }
4458
4459        /* If we get here, we haven't found a reason to stop the
4460           encoder. */
4461        return 0;
4462}
4463
4464
4465/* Return true if the encoder should be running. */
4466static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4467{
4468        if (!hdw->state_encoder_ok) {
4469                /* Don't run the encoder if it isn't healthy... */
4470                return 0;
4471        }
4472        if (!hdw->state_pathway_ok) {
4473                /* Don't run the encoder if we don't (yet) know what mode
4474                   we need to be in... */
4475                return 0;
4476        }
4477
4478        switch (hdw->pathway_state) {
4479        case PVR2_PATHWAY_ANALOG:
4480                if (hdw->state_decoder_run && hdw->state_decoder_ready) {
4481                        /* In analog mode, if the decoder is running, then
4482                           run the encoder. */
4483                        return !0;
4484                }
4485                break;
4486        case PVR2_PATHWAY_DIGITAL:
4487                if ((hdw->hdw_desc->digital_control_scheme ==
4488                     PVR2_DIGITAL_SCHEME_ONAIR) &&
4489                    !hdw->state_encoder_runok) {
4490                        /* This is a quirk.  OnAir hardware won't stream
4491                           digital until the encoder has been run at least
4492                           once, for a minimal period of time (empiricially
4493                           measured to be 1/4 second).  So if we're on
4494                           OnAir hardware and the encoder has never been
4495                           run at all, then start the encoder.  Normal
4496                           state machine logic in the driver will
4497                           automatically handle the remaining bits. */
4498                        return !0;
4499                }
4500                break;
4501        default:
4502                /* For completeness (unknown mode; encoder won't run ever) */
4503                break;
4504        }
4505        /* If we get here, then we haven't found any reason to run the
4506           encoder, so don't run it. */
4507        return 0;
4508}
4509
4510
4511/* Evaluate whether or not state_encoder_run can change */
4512static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4513{
4514        if (hdw->state_encoder_run) {
4515                if (!state_check_disable_encoder_run(hdw)) return 0;
4516                if (hdw->state_encoder_ok) {
4517                        del_timer_sync(&hdw->encoder_run_timer);
4518                        if (pvr2_encoder_stop(hdw) < 0) return !0;
4519                }
4520                hdw->state_encoder_run = 0;
4521        } else {
4522                if (!state_check_enable_encoder_run(hdw)) return 0;
4523                if (pvr2_encoder_start(hdw) < 0) return !0;
4524                hdw->state_encoder_run = !0;
4525                if (!hdw->state_encoder_runok) {
4526                        hdw->encoder_run_timer.expires =
4527                                jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
4528                        add_timer(&hdw->encoder_run_timer);
4529                }
4530        }
4531        trace_stbit("state_encoder_run",hdw->state_encoder_run);
4532        return !0;
4533}
4534
4535
4536/* Timeout function for quiescent timer. */
4537static void pvr2_hdw_quiescent_timeout(unsigned long data)
4538{
4539        struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4540        hdw->state_decoder_quiescent = !0;
4541        trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4542        hdw->state_stale = !0;
4543        queue_work(hdw->workqueue,&hdw->workpoll);
4544}
4545
4546
4547/* Timeout function for decoder stabilization timer. */
4548static void pvr2_hdw_decoder_stabilization_timeout(unsigned long data)
4549{
4550        struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4551        hdw->state_decoder_ready = !0;
4552        trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4553        hdw->state_stale = !0;
4554        queue_work(hdw->workqueue, &hdw->workpoll);
4555}
4556
4557
4558/* Timeout function for encoder wait timer. */
4559static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4560{
4561        struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4562        hdw->state_encoder_waitok = !0;
4563        trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4564        hdw->state_stale = !0;
4565        queue_work(hdw->workqueue,&hdw->workpoll);
4566}
4567
4568
4569/* Timeout function for encoder run timer. */
4570static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4571{
4572        struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4573        if (!hdw->state_encoder_runok) {
4574                hdw->state_encoder_runok = !0;
4575                trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4576                hdw->state_stale = !0;
4577                queue_work(hdw->workqueue,&hdw->workpoll);
4578        }
4579}
4580
4581
4582/* Evaluate whether or not state_decoder_run can change */
4583static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4584{
4585        if (hdw->state_decoder_run) {
4586                if (hdw->state_encoder_ok) {
4587                        if (hdw->state_pipeline_req &&
4588                            !hdw->state_pipeline_pause &&
4589                            hdw->state_pathway_ok) return 0;
4590                }
4591                if (!hdw->flag_decoder_missed) {
4592                        pvr2_decoder_enable(hdw,0);
4593                }
4594                hdw->state_decoder_quiescent = 0;
4595                hdw->state_decoder_run = 0;
4596                /* paranoia - solve race if timer(s) just completed */
4597                del_timer_sync(&hdw->quiescent_timer);
4598                /* Kill the stabilization timer, in case we're killing the
4599                   encoder before the previous stabilization interval has
4600                   been properly timed. */
4601                del_timer_sync(&hdw->decoder_stabilization_timer);
4602                hdw->state_decoder_ready = 0;
4603        } else {
4604                if (!hdw->state_decoder_quiescent) {
4605                        if (!timer_pending(&hdw->quiescent_timer)) {
4606                                /* We don't do something about the
4607                                   quiescent timer until right here because
4608                                   we also want to catch cases where the
4609                                   decoder was already not running (like
4610                                   after initialization) as opposed to
4611                                   knowing that we had just stopped it.
4612                                   The second flag check is here to cover a
4613                                   race - the timer could have run and set
4614                                   this flag just after the previous check
4615                                   but before we did the pending check. */
4616                                if (!hdw->state_decoder_quiescent) {
4617                                        hdw->quiescent_timer.expires =
4618                                                jiffies +
4619                                                (HZ * TIME_MSEC_DECODER_WAIT
4620                                                 / 1000);
4621                                        add_timer(&hdw->quiescent_timer);
4622                                }
4623                        }
4624                        /* Don't allow decoder to start again until it has
4625                           been quiesced first.  This little detail should
4626                           hopefully further stabilize the encoder. */
4627                        return 0;
4628                }
4629                if (!hdw->state_pathway_ok ||
4630                    (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4631                    !hdw->state_pipeline_req ||
4632                    hdw->state_pipeline_pause ||
4633                    !hdw->state_pipeline_config ||
4634                    !hdw->state_encoder_config ||
4635                    !hdw->state_encoder_ok) return 0;
4636                del_timer_sync(&hdw->quiescent_timer);
4637                if (hdw->flag_decoder_missed) return 0;
4638                if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4639                hdw->state_decoder_quiescent = 0;
4640                hdw->state_decoder_ready = 0;
4641                hdw->state_decoder_run = !0;
4642                if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) {
4643                        hdw->decoder_stabilization_timer.expires =
4644                                jiffies +
4645                                (HZ * TIME_MSEC_DECODER_STABILIZATION_WAIT /
4646                                 1000);
4647                        add_timer(&hdw->decoder_stabilization_timer);
4648                } else {
4649                        hdw->state_decoder_ready = !0;
4650                }
4651        }
4652        trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4653        trace_stbit("state_decoder_run",hdw->state_decoder_run);
4654        trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4655        return !0;
4656}
4657
4658
4659/* Evaluate whether or not state_usbstream_run can change */
4660static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4661{
4662        if (hdw->state_usbstream_run) {
4663                int fl = !0;
4664                if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4665                        fl = (hdw->state_encoder_ok &&
4666                              hdw->state_encoder_run);
4667                } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4668                           (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4669                        fl = hdw->state_encoder_ok;
4670                }
4671                if (fl &&
4672                    hdw->state_pipeline_req &&
4673                    !hdw->state_pipeline_pause &&
4674                    hdw->state_pathway_ok) {
4675                        return 0;
4676                }
4677                pvr2_hdw_cmd_usbstream(hdw,0);
4678                hdw->state_usbstream_run = 0;
4679        } else {
4680                if (!hdw->state_pipeline_req ||
4681                    hdw->state_pipeline_pause ||
4682                    !hdw->state_pathway_ok) return 0;
4683                if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4684                        if (!hdw->state_encoder_ok ||
4685                            !hdw->state_encoder_run) return 0;
4686                } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4687                           (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4688                        if (!hdw->state_encoder_ok) return 0;
4689                        if (hdw->state_encoder_run) return 0;
4690                        if (hdw->hdw_desc->digital_control_scheme ==
4691                            PVR2_DIGITAL_SCHEME_ONAIR) {
4692                                /* OnAir digital receivers won't stream
4693                                   unless the analog encoder has run first.
4694                                   Why?  I have no idea.  But don't even
4695                                   try until we know the analog side is
4696                                   known to have run. */
4697                                if (!hdw->state_encoder_runok) return 0;
4698                        }
4699                }
4700                if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4701                hdw->state_usbstream_run = !0;
4702        }
4703        trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4704        return !0;
4705}
4706
4707
4708/* Attempt to configure pipeline, if needed */
4709static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4710{
4711        if (hdw->state_pipeline_config ||
4712            hdw->state_pipeline_pause) return 0;
4713        pvr2_hdw_commit_execute(hdw);
4714        return !0;
4715}
4716
4717
4718/* Update pipeline idle and pipeline pause tracking states based on other
4719   inputs.  This must be called whenever the other relevant inputs have
4720   changed. */
4721static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4722{
4723        unsigned int st;
4724        int updatedFl = 0;
4725        /* Update pipeline state */
4726        st = !(hdw->state_encoder_run ||
4727               hdw->state_decoder_run ||
4728               hdw->state_usbstream_run ||
4729               (!hdw->state_decoder_quiescent));
4730        if (!st != !hdw->state_pipeline_idle) {
4731                hdw->state_pipeline_idle = st;
4732                updatedFl = !0;
4733        }
4734        if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4735                hdw->state_pipeline_pause = 0;
4736                updatedFl = !0;
4737        }
4738        return updatedFl;
4739}
4740
4741
4742typedef int (*state_eval_func)(struct pvr2_hdw *);
4743
4744/* Set of functions to be run to evaluate various states in the driver. */
4745static const state_eval_func eval_funcs[] = {
4746        state_eval_pathway_ok,
4747        state_eval_pipeline_config,
4748        state_eval_encoder_ok,
4749        state_eval_encoder_config,
4750        state_eval_decoder_run,
4751        state_eval_encoder_run,
4752        state_eval_usbstream_run,
4753};
4754
4755
4756/* Process various states and return true if we did anything interesting. */
4757static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4758{
4759        unsigned int i;
4760        int state_updated = 0;
4761        int check_flag;
4762
4763        if (!hdw->state_stale) return 0;
4764        if ((hdw->fw1_state != FW1_STATE_OK) ||
4765            !hdw->flag_ok) {
4766                hdw->state_stale = 0;
4767                return !0;
4768        }
4769        /* This loop is the heart of the entire driver.  It keeps trying to
4770           evaluate various bits of driver state until nothing changes for
4771           one full iteration.  Each "bit of state" tracks some global
4772           aspect of the driver, e.g. whether decoder should run, if
4773           pipeline is configured, usb streaming is on, etc.  We separately
4774           evaluate each of those questions based on other driver state to
4775           arrive at the correct running configuration. */
4776        do {
4777                check_flag = 0;
4778                state_update_pipeline_state(hdw);
4779                /* Iterate over each bit of state */
4780                for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4781                        if ((*eval_funcs[i])(hdw)) {
4782                                check_flag = !0;
4783                                state_updated = !0;
4784                                state_update_pipeline_state(hdw);
4785                        }
4786                }
4787        } while (check_flag && hdw->flag_ok);
4788        hdw->state_stale = 0;
4789        trace_stbit("state_stale",hdw->state_stale);
4790        return state_updated;
4791}
4792
4793
4794static unsigned int print_input_mask(unsigned int msk,
4795                                     char *buf,unsigned int acnt)
4796{
4797        unsigned int idx,ccnt;
4798        unsigned int tcnt = 0;
4799        for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4800                if (!((1 << idx) & msk)) continue;
4801                ccnt = scnprintf(buf+tcnt,
4802                                 acnt-tcnt,
4803                                 "%s%s",
4804                                 (tcnt ? ", " : ""),
4805                                 control_values_input[idx]);
4806                tcnt += ccnt;
4807        }
4808        return tcnt;
4809}
4810
4811
4812static const char *pvr2_pathway_state_name(int id)
4813{
4814        switch (id) {
4815        case PVR2_PATHWAY_ANALOG: return "analog";
4816        case PVR2_PATHWAY_DIGITAL: return "digital";
4817        default: return "unknown";
4818        }
4819}
4820
4821
4822static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4823                                             char *buf,unsigned int acnt)
4824{
4825        switch (which) {
4826        case 0:
4827                return scnprintf(
4828                        buf,acnt,
4829                        "driver:%s%s%s%s%s <mode=%s>",
4830                        (hdw->flag_ok ? " <ok>" : " <fail>"),
4831                        (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4832                        (hdw->flag_disconnected ? " <disconnected>" :
4833                         " <connected>"),
4834                        (hdw->flag_tripped ? " <tripped>" : ""),
4835                        (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4836                        pvr2_pathway_state_name(hdw->pathway_state));
4837
4838        case 1:
4839                return scnprintf(
4840                        buf,acnt,
4841                        "pipeline:%s%s%s%s",
4842                        (hdw->state_pipeline_idle ? " <idle>" : ""),
4843                        (hdw->state_pipeline_config ?
4844                         " <configok>" : " <stale>"),
4845                        (hdw->state_pipeline_req ? " <req>" : ""),
4846                        (hdw->state_pipeline_pause ? " <pause>" : ""));
4847        case 2:
4848                return scnprintf(
4849                        buf,acnt,
4850                        "worker:%s%s%s%s%s%s%s",
4851                        (hdw->state_decoder_run ?
4852                         (hdw->state_decoder_ready ?
4853                          "<decode:run>" : " <decode:start>") :
4854                         (hdw->state_decoder_quiescent ?
4855                          "" : " <decode:stop>")),
4856                        (hdw->state_decoder_quiescent ?
4857                         " <decode:quiescent>" : ""),
4858                        (hdw->state_encoder_ok ?
4859                         "" : " <encode:init>"),
4860                        (hdw->state_encoder_run ?
4861                         (hdw->state_encoder_runok ?
4862                          " <encode:run>" :
4863                          " <encode:firstrun>") :
4864                         (hdw->state_encoder_runok ?
4865                          " <encode:stop>" :
4866                          " <encode:virgin>")),
4867                        (hdw->state_encoder_config ?
4868                         " <encode:configok>" :
4869                         (hdw->state_encoder_waitok ?
4870                          "" : " <encode:waitok>")),
4871                        (hdw->state_usbstream_run ?
4872                         " <usb:run>" : " <usb:stop>"),
4873                        (hdw->state_pathway_ok ?
4874                         " <pathway:ok>" : ""));
4875        case 3:
4876                return scnprintf(
4877                        buf,acnt,
4878                        "state: %s",
4879                        pvr2_get_state_name(hdw->master_state));
4880        case 4: {
4881                unsigned int tcnt = 0;
4882                unsigned int ccnt;
4883
4884                ccnt = scnprintf(buf,
4885                                 acnt,
4886                                 "Hardware supported inputs: ");
4887                tcnt += ccnt;
4888                tcnt += print_input_mask(hdw->input_avail_mask,
4889                                         buf+tcnt,
4890                                         acnt-tcnt);
4891                if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4892                        ccnt = scnprintf(buf+tcnt,
4893                                         acnt-tcnt,
4894                                         "; allowed inputs: ");
4895                        tcnt += ccnt;
4896                        tcnt += print_input_mask(hdw->input_allowed_mask,
4897                                                 buf+tcnt,
4898                                                 acnt-tcnt);
4899                }
4900                return tcnt;
4901        }
4902        case 5: {
4903                struct pvr2_stream_stats stats;
4904                if (!hdw->vid_stream) break;
4905                pvr2_stream_get_stats(hdw->vid_stream,
4906                                      &stats,
4907                                      0);
4908                return scnprintf(
4909                        buf,acnt,
4910                        "Bytes streamed=%u"
4911                        " URBs: queued=%u idle=%u ready=%u"
4912                        " processed=%u failed=%u",
4913                        stats.bytes_processed,
4914                        stats.buffers_in_queue,
4915                        stats.buffers_in_idle,
4916                        stats.buffers_in_ready,
4917                        stats.buffers_processed,
4918                        stats.buffers_failed);
4919        }
4920        case 6: {
4921                unsigned int id = hdw->ir_scheme_active;
4922                return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4923                                 (id >= ARRAY_SIZE(ir_scheme_names) ?
4924                                  "?" : ir_scheme_names[id]));
4925        }
4926        default: break;
4927        }
4928        return 0;
4929}
4930
4931
4932/* Generate report containing info about attached sub-devices and attached
4933   i2c clients, including an indication of which attached i2c clients are
4934   actually sub-devices. */
4935static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4936                                            char *buf, unsigned int acnt)
4937{
4938        struct v4l2_subdev *sd;
4939        unsigned int tcnt = 0;
4940        unsigned int ccnt;
4941        struct i2c_client *client;
4942        const char *p;
4943        unsigned int id;
4944
4945        ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
4946        tcnt += ccnt;
4947        v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4948                id = sd->grp_id;
4949                p = NULL;
4950                if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4951                if (p) {
4952                        ccnt = scnprintf(buf + tcnt, acnt - tcnt, "  %s:", p);
4953                        tcnt += ccnt;
4954                } else {
4955                        ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4956                                         "  (unknown id=%u):", id);
4957                        tcnt += ccnt;
4958                }
4959                client = v4l2_get_subdevdata(sd);
4960                if (client) {
4961                        ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4962                                         " %s @ %02x\n", client->name,
4963                                         client->addr);
4964                        tcnt += ccnt;
4965                } else {
4966                        ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4967                                         " no i2c client\n");
4968                        tcnt += ccnt;
4969                }
4970        }
4971        return tcnt;
4972}
4973
4974
4975unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4976                                   char *buf,unsigned int acnt)
4977{
4978        unsigned int bcnt,ccnt,idx;
4979        bcnt = 0;
4980        LOCK_TAKE(hdw->big_lock);
4981        for (idx = 0; ; idx++) {
4982                ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4983                if (!ccnt) break;
4984                bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4985                if (!acnt) break;
4986                buf[0] = '\n'; ccnt = 1;
4987                bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4988        }
4989        ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4990        bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4991        LOCK_GIVE(hdw->big_lock);
4992        return bcnt;
4993}
4994
4995
4996static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4997{
4998        char buf[256];
4999        unsigned int idx, ccnt;
5000        unsigned int lcnt, ucnt;
5001
5002        for (idx = 0; ; idx++) {
5003                ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
5004                if (!ccnt) break;
5005                printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
5006        }
5007        ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
5008        ucnt = 0;
5009        while (ucnt < ccnt) {
5010                lcnt = 0;
5011                while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
5012                        lcnt++;
5013                }
5014                printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
5015                ucnt += lcnt + 1;
5016        }
5017}
5018
5019
5020/* Evaluate and update the driver's current state, taking various actions
5021   as appropriate for the update. */
5022static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
5023{
5024        unsigned int st;
5025        int state_updated = 0;
5026        int callback_flag = 0;
5027        int analog_mode;
5028
5029        pvr2_trace(PVR2_TRACE_STBITS,
5030                   "Drive state check START");
5031        if (pvrusb2_debug & PVR2_TRACE_STBITS) {
5032                pvr2_hdw_state_log_state(hdw);
5033        }
5034
5035        /* Process all state and get back over disposition */
5036        state_updated = pvr2_hdw_state_update(hdw);
5037
5038        analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
5039
5040        /* Update master state based upon all other states. */
5041        if (!hdw->flag_ok) {
5042                st = PVR2_STATE_DEAD;
5043        } else if (hdw->fw1_state != FW1_STATE_OK) {
5044                st = PVR2_STATE_COLD;
5045        } else if ((analog_mode ||
5046                    hdw->hdw_desc->flag_digital_requires_cx23416) &&
5047                   !hdw->state_encoder_ok) {
5048                st = PVR2_STATE_WARM;
5049        } else if (hdw->flag_tripped ||
5050                   (analog_mode && hdw->flag_decoder_missed)) {
5051                st = PVR2_STATE_ERROR;
5052        } else if (hdw->state_usbstream_run &&
5053                   (!analog_mode ||
5054                    (hdw->state_encoder_run && hdw->state_decoder_run))) {
5055                st = PVR2_STATE_RUN;
5056        } else {
5057                st = PVR2_STATE_READY;
5058        }
5059        if (hdw->master_state != st) {
5060                pvr2_trace(PVR2_TRACE_STATE,
5061                           "Device state change from %s to %s",
5062                           pvr2_get_state_name(hdw->master_state),
5063                           pvr2_get_state_name(st));
5064                pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
5065                hdw->master_state = st;
5066                state_updated = !0;
5067                callback_flag = !0;
5068        }
5069        if (state_updated) {
5070                /* Trigger anyone waiting on any state changes here. */
5071                wake_up(&hdw->state_wait_data);
5072        }
5073
5074        if (pvrusb2_debug & PVR2_TRACE_STBITS) {
5075                pvr2_hdw_state_log_state(hdw);
5076        }
5077        pvr2_trace(PVR2_TRACE_STBITS,
5078                   "Drive state check DONE callback=%d",callback_flag);
5079
5080        return callback_flag;
5081}
5082
5083
5084/* Cause kernel thread to check / update driver state */
5085static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
5086{
5087        if (hdw->state_stale) return;
5088        hdw->state_stale = !0;
5089        trace_stbit("state_stale",hdw->state_stale);
5090        queue_work(hdw->workqueue,&hdw->workpoll);
5091}
5092
5093
5094int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
5095{
5096        return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
5097}
5098
5099
5100int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5101{
5102        return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5103}
5104
5105
5106int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5107{
5108        return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5109}
5110
5111
5112int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5113{
5114        u32 cval,nval;
5115        int ret;
5116        if (~msk) {
5117                ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5118                if (ret) return ret;
5119                nval = (cval & ~msk) | (val & msk);
5120                pvr2_trace(PVR2_TRACE_GPIO,
5121                           "GPIO direction changing 0x%x:0x%x"
5122                           " from 0x%x to 0x%x",
5123                           msk,val,cval,nval);
5124        } else {
5125                nval = val;
5126                pvr2_trace(PVR2_TRACE_GPIO,
5127                           "GPIO direction changing to 0x%x",nval);
5128        }
5129        return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5130}
5131
5132
5133int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5134{
5135        u32 cval,nval;
5136        int ret;
5137        if (~msk) {
5138                ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5139                if (ret) return ret;
5140                nval = (cval & ~msk) | (val & msk);
5141                pvr2_trace(PVR2_TRACE_GPIO,
5142                           "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5143                           msk,val,cval,nval);
5144        } else {
5145                nval = val;
5146                pvr2_trace(PVR2_TRACE_GPIO,
5147                           "GPIO output changing to 0x%x",nval);
5148        }
5149        return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5150}
5151
5152
5153void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5154{
5155        struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5156        memset(vtp, 0, sizeof(*vtp));
5157        hdw->tuner_signal_stale = 0;
5158        /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5159           using v4l2-subdev - therefore we can't support that AT ALL right
5160           now.  (Of course, no sub-drivers seem to implement it either.
5161           But now it's a a chicken and egg problem...) */
5162        v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
5163                             &hdw->tuner_signal_info);
5164        pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
5165                   " type=%u strength=%u audio=0x%x cap=0x%x"
5166                   " low=%u hi=%u",
5167                   vtp->type,
5168                   vtp->signal, vtp->rxsubchans, vtp->capability,
5169                   vtp->rangelow, vtp->rangehigh);
5170
5171        /* We have to do this to avoid getting into constant polling if
5172           there's nobody to answer a poll of cropcap info. */
5173        hdw->cropcap_stale = 0;
5174}
5175
5176
5177unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5178{
5179        return hdw->input_avail_mask;
5180}
5181
5182
5183unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5184{
5185        return hdw->input_allowed_mask;
5186}
5187
5188
5189static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5190{
5191        if (hdw->input_val != v) {
5192                hdw->input_val = v;
5193                hdw->input_dirty = !0;
5194        }
5195
5196        /* Handle side effects - if we switch to a mode that needs the RF
5197           tuner, then select the right frequency choice as well and mark
5198           it dirty. */
5199        if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5200                hdw->freqSelector = 0;
5201                hdw->freqDirty = !0;
5202        } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5203                   (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5204                hdw->freqSelector = 1;
5205                hdw->freqDirty = !0;
5206        }
5207        return 0;
5208}
5209
5210
5211int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5212                               unsigned int change_mask,
5213                               unsigned int change_val)
5214{
5215        int ret = 0;
5216        unsigned int nv,m,idx;
5217        LOCK_TAKE(hdw->big_lock);
5218        do {
5219                nv = hdw->input_allowed_mask & ~change_mask;
5220                nv |= (change_val & change_mask);
5221                nv &= hdw->input_avail_mask;
5222                if (!nv) {
5223                        /* No legal modes left; return error instead. */
5224                        ret = -EPERM;
5225                        break;
5226                }
5227                hdw->input_allowed_mask = nv;
5228                if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5229                        /* Current mode is still in the allowed mask, so
5230                           we're done. */
5231                        break;
5232                }
5233                /* Select and switch to a mode that is still in the allowed
5234                   mask */
5235                if (!hdw->input_allowed_mask) {
5236                        /* Nothing legal; give up */
5237                        break;
5238                }
5239                m = hdw->input_allowed_mask;
5240                for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5241                        if (!((1 << idx) & m)) continue;
5242                        pvr2_hdw_set_input(hdw,idx);
5243                        break;
5244                }
5245        } while (0);
5246        LOCK_GIVE(hdw->big_lock);
5247        return ret;
5248}
5249
5250
5251/* Find I2C address of eeprom */
5252static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5253{
5254        int result;
5255        LOCK_TAKE(hdw->ctl_lock); do {
5256                hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5257                result = pvr2_send_request(hdw,
5258                                           hdw->cmd_buffer,1,
5259                                           hdw->cmd_buffer,1);
5260                if (result < 0) break;
5261                result = hdw->cmd_buffer[0];
5262        } while(0); LOCK_GIVE(hdw->ctl_lock);
5263        return result;
5264}
5265
5266
5267int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
5268                             struct v4l2_dbg_match *match, u64 reg_id,
5269                             int setFl, u64 *val_ptr)
5270{
5271#ifdef CONFIG_VIDEO_ADV_DEBUG
5272        struct v4l2_dbg_register req;
5273        int stat = 0;
5274        int okFl = 0;
5275
5276        if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5277
5278        req.match = *match;
5279        req.reg = reg_id;
5280        if (setFl) req.val = *val_ptr;
5281        /* It would be nice to know if a sub-device answered the request */
5282        v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5283        if (!setFl) *val_ptr = req.val;
5284        if (okFl) {
5285                return stat;
5286        }
5287        return -EINVAL;
5288#else
5289        return -ENOSYS;
5290#endif
5291}
5292
5293
5294/*
5295  Stuff for Emacs to see, in order to encourage consistent editing style:
5296  *** Local Variables: ***
5297  *** mode: c ***
5298  *** fill-column: 75 ***
5299  *** tab-width: 8 ***
5300  *** c-basic-offset: 8 ***
5301  *** End: ***
5302  */
5303