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31#include <linux/i2c.h>
32#include <linux/slab.h>
33#include <linux/delay.h>
34#include <linux/videodev2.h>
35
36#include <media/v4l2-device.h>
37#include <media/v4l2-common.h>
38#include <media/v4l2-mediabus.h>
39#include <media/v4l2-chip-ident.h>
40#include <media/tvp514x.h>
41
42#include "tvp514x_regs.h"
43
44
45#define TVP514X_MODULE_NAME "tvp514x"
46
47
48#define I2C_RETRY_COUNT (5)
49#define LOCK_RETRY_COUNT (5)
50#define LOCK_RETRY_DELAY (200)
51
52
53static int debug;
54module_param(debug, bool, 0644);
55MODULE_PARM_DESC(debug, "Debug level (0-1)");
56
57MODULE_AUTHOR("Texas Instruments");
58MODULE_DESCRIPTION("TVP514X linux decoder driver");
59MODULE_LICENSE("GPL");
60
61
62enum tvp514x_std {
63 STD_NTSC_MJ = 0,
64 STD_PAL_BDGHIN,
65 STD_INVALID
66};
67
68
69
70
71
72
73
74
75struct tvp514x_std_info {
76 unsigned long width;
77 unsigned long height;
78 u8 video_std;
79 struct v4l2_standard standard;
80};
81
82static struct tvp514x_reg tvp514x_reg_list_default[0x40];
83
84static int tvp514x_s_stream(struct v4l2_subdev *sd, int enable);
85
86
87
88
89
90
91
92
93
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95
96
97
98struct tvp514x_decoder {
99 struct v4l2_subdev sd;
100 struct tvp514x_reg tvp514x_regs[ARRAY_SIZE(tvp514x_reg_list_default)];
101 const struct tvp514x_platform_data *pdata;
102
103 int ver;
104 int streaming;
105
106 enum tvp514x_std current_std;
107 int num_stds;
108 const struct tvp514x_std_info *std_list;
109
110 u32 input;
111 u32 output;
112};
113
114
115static struct tvp514x_reg tvp514x_reg_list_default[] = {
116
117 {TOK_WRITE, REG_INPUT_SEL, 0x05},
118 {TOK_WRITE, REG_AFE_GAIN_CTRL, 0x0F},
119
120 {TOK_WRITE, REG_VIDEO_STD, 0x00},
121 {TOK_WRITE, REG_OPERATION_MODE, 0x00},
122 {TOK_SKIP, REG_AUTOSWITCH_MASK, 0x3F},
123 {TOK_WRITE, REG_COLOR_KILLER, 0x10},
124 {TOK_WRITE, REG_LUMA_CONTROL1, 0x00},
125 {TOK_WRITE, REG_LUMA_CONTROL2, 0x00},
126 {TOK_WRITE, REG_LUMA_CONTROL3, 0x02},
127 {TOK_WRITE, REG_BRIGHTNESS, 0x80},
128 {TOK_WRITE, REG_CONTRAST, 0x80},
129 {TOK_WRITE, REG_SATURATION, 0x80},
130 {TOK_WRITE, REG_HUE, 0x00},
131 {TOK_WRITE, REG_CHROMA_CONTROL1, 0x00},
132 {TOK_WRITE, REG_CHROMA_CONTROL2, 0x0E},
133
134 {TOK_SKIP, 0x0F, 0x00},
135 {TOK_WRITE, REG_COMP_PR_SATURATION, 0x80},
136 {TOK_WRITE, REG_COMP_Y_CONTRAST, 0x80},
137 {TOK_WRITE, REG_COMP_PB_SATURATION, 0x80},
138
139 {TOK_SKIP, 0x13, 0x00},
140 {TOK_WRITE, REG_COMP_Y_BRIGHTNESS, 0x80},
141
142 {TOK_SKIP, 0x15, 0x00},
143
144 {TOK_SKIP, REG_AVID_START_PIXEL_LSB, 0x55},
145 {TOK_SKIP, REG_AVID_START_PIXEL_MSB, 0x00},
146 {TOK_SKIP, REG_AVID_STOP_PIXEL_LSB, 0x25},
147 {TOK_SKIP, REG_AVID_STOP_PIXEL_MSB, 0x03},
148
149 {TOK_SKIP, REG_HSYNC_START_PIXEL_LSB, 0x00},
150 {TOK_SKIP, REG_HSYNC_START_PIXEL_MSB, 0x00},
151 {TOK_SKIP, REG_HSYNC_STOP_PIXEL_LSB, 0x40},
152 {TOK_SKIP, REG_HSYNC_STOP_PIXEL_MSB, 0x00},
153
154 {TOK_SKIP, REG_VSYNC_START_LINE_LSB, 0x04},
155 {TOK_SKIP, REG_VSYNC_START_LINE_MSB, 0x00},
156 {TOK_SKIP, REG_VSYNC_STOP_LINE_LSB, 0x07},
157 {TOK_SKIP, REG_VSYNC_STOP_LINE_MSB, 0x00},
158
159 {TOK_SKIP, REG_VBLK_START_LINE_LSB, 0x01},
160 {TOK_SKIP, REG_VBLK_START_LINE_MSB, 0x00},
161 {TOK_SKIP, REG_VBLK_STOP_LINE_LSB, 0x15},
162 {TOK_SKIP, REG_VBLK_STOP_LINE_MSB, 0x00},
163
164 {TOK_SKIP, 0x26, 0x00},
165
166 {TOK_SKIP, 0x27, 0x00},
167 {TOK_SKIP, REG_FAST_SWTICH_CONTROL, 0xCC},
168
169 {TOK_SKIP, 0x29, 0x00},
170 {TOK_SKIP, REG_FAST_SWTICH_SCART_DELAY, 0x00},
171
172 {TOK_SKIP, 0x2B, 0x00},
173 {TOK_SKIP, REG_SCART_DELAY, 0x00},
174 {TOK_SKIP, REG_CTI_DELAY, 0x00},
175 {TOK_SKIP, REG_CTI_CONTROL, 0x00},
176
177 {TOK_SKIP, 0x2F, 0x00},
178
179 {TOK_SKIP, 0x30, 0x00},
180
181 {TOK_SKIP, 0x31, 0x00},
182
183 {TOK_WRITE, REG_SYNC_CONTROL, 0x00},
184
185 {TOK_WRITE, REG_OUTPUT_FORMATTER1, 0x00},
186
187 {TOK_WRITE, REG_OUTPUT_FORMATTER2, 0x11},
188
189 {TOK_WRITE, REG_OUTPUT_FORMATTER3, 0xEE},
190
191 {TOK_WRITE, REG_OUTPUT_FORMATTER4, 0xAF},
192 {TOK_WRITE, REG_OUTPUT_FORMATTER5, 0xFF},
193 {TOK_WRITE, REG_OUTPUT_FORMATTER6, 0xFF},
194
195 {TOK_WRITE, REG_CLEAR_LOST_LOCK, 0x01},
196 {TOK_TERM, 0, 0},
197};
198
199
200
201
202
203
204
205static const struct tvp514x_std_info tvp514x_std_list[] = {
206
207 [STD_NTSC_MJ] = {
208 .width = NTSC_NUM_ACTIVE_PIXELS,
209 .height = NTSC_NUM_ACTIVE_LINES,
210 .video_std = VIDEO_STD_NTSC_MJ_BIT,
211 .standard = {
212 .index = 0,
213 .id = V4L2_STD_NTSC,
214 .name = "NTSC",
215 .frameperiod = {1001, 30000},
216 .framelines = 525
217 },
218
219 },
220 [STD_PAL_BDGHIN] = {
221 .width = PAL_NUM_ACTIVE_PIXELS,
222 .height = PAL_NUM_ACTIVE_LINES,
223 .video_std = VIDEO_STD_PAL_BDGHIN_BIT,
224 .standard = {
225 .index = 1,
226 .id = V4L2_STD_PAL,
227 .name = "PAL",
228 .frameperiod = {1, 25},
229 .framelines = 625
230 },
231 },
232
233};
234
235
236static inline struct tvp514x_decoder *to_decoder(struct v4l2_subdev *sd)
237{
238 return container_of(sd, struct tvp514x_decoder, sd);
239}
240
241
242
243
244
245
246
247
248
249static int tvp514x_read_reg(struct v4l2_subdev *sd, u8 reg)
250{
251 int err, retry = 0;
252 struct i2c_client *client = v4l2_get_subdevdata(sd);
253
254read_again:
255
256 err = i2c_smbus_read_byte_data(client, reg);
257 if (err < 0) {
258 if (retry <= I2C_RETRY_COUNT) {
259 v4l2_warn(sd, "Read: retry ... %d\n", retry);
260 retry++;
261 msleep_interruptible(10);
262 goto read_again;
263 }
264 }
265
266 return err;
267}
268
269
270
271
272
273
274static void dump_reg(struct v4l2_subdev *sd, u8 reg)
275{
276 u32 val;
277
278 val = tvp514x_read_reg(sd, reg);
279 v4l2_info(sd, "Reg(0x%.2X): 0x%.2X\n", reg, val);
280}
281
282
283
284
285
286
287
288
289
290
291static int tvp514x_write_reg(struct v4l2_subdev *sd, u8 reg, u8 val)
292{
293 int err, retry = 0;
294 struct i2c_client *client = v4l2_get_subdevdata(sd);
295
296write_again:
297
298 err = i2c_smbus_write_byte_data(client, reg, val);
299 if (err) {
300 if (retry <= I2C_RETRY_COUNT) {
301 v4l2_warn(sd, "Write: retry ... %d\n", retry);
302 retry++;
303 msleep_interruptible(10);
304 goto write_again;
305 }
306 }
307
308 return err;
309}
310
311
312
313
314
315
316
317
318
319
320
321
322
323static int tvp514x_write_regs(struct v4l2_subdev *sd,
324 const struct tvp514x_reg reglist[])
325{
326 int err;
327 const struct tvp514x_reg *next = reglist;
328
329 for (; next->token != TOK_TERM; next++) {
330 if (next->token == TOK_DELAY) {
331 msleep(next->val);
332 continue;
333 }
334
335 if (next->token == TOK_SKIP)
336 continue;
337
338 err = tvp514x_write_reg(sd, next->reg, (u8) next->val);
339 if (err) {
340 v4l2_err(sd, "Write failed. Err[%d]\n", err);
341 return err;
342 }
343 }
344 return 0;
345}
346
347
348
349
350
351
352
353
354static enum tvp514x_std tvp514x_query_current_std(struct v4l2_subdev *sd)
355{
356 u8 std, std_status;
357
358 std = tvp514x_read_reg(sd, REG_VIDEO_STD);
359 if ((std & VIDEO_STD_MASK) == VIDEO_STD_AUTO_SWITCH_BIT)
360
361 std_status = tvp514x_read_reg(sd, REG_VIDEO_STD_STATUS);
362 else
363
364 std_status = std;
365
366 switch (std_status & VIDEO_STD_MASK) {
367 case VIDEO_STD_NTSC_MJ_BIT:
368 return STD_NTSC_MJ;
369
370 case VIDEO_STD_PAL_BDGHIN_BIT:
371 return STD_PAL_BDGHIN;
372
373 default:
374 return STD_INVALID;
375 }
376
377 return STD_INVALID;
378}
379
380
381static void tvp514x_reg_dump(struct v4l2_subdev *sd)
382{
383 dump_reg(sd, REG_INPUT_SEL);
384 dump_reg(sd, REG_AFE_GAIN_CTRL);
385 dump_reg(sd, REG_VIDEO_STD);
386 dump_reg(sd, REG_OPERATION_MODE);
387 dump_reg(sd, REG_COLOR_KILLER);
388 dump_reg(sd, REG_LUMA_CONTROL1);
389 dump_reg(sd, REG_LUMA_CONTROL2);
390 dump_reg(sd, REG_LUMA_CONTROL3);
391 dump_reg(sd, REG_BRIGHTNESS);
392 dump_reg(sd, REG_CONTRAST);
393 dump_reg(sd, REG_SATURATION);
394 dump_reg(sd, REG_HUE);
395 dump_reg(sd, REG_CHROMA_CONTROL1);
396 dump_reg(sd, REG_CHROMA_CONTROL2);
397 dump_reg(sd, REG_COMP_PR_SATURATION);
398 dump_reg(sd, REG_COMP_Y_CONTRAST);
399 dump_reg(sd, REG_COMP_PB_SATURATION);
400 dump_reg(sd, REG_COMP_Y_BRIGHTNESS);
401 dump_reg(sd, REG_AVID_START_PIXEL_LSB);
402 dump_reg(sd, REG_AVID_START_PIXEL_MSB);
403 dump_reg(sd, REG_AVID_STOP_PIXEL_LSB);
404 dump_reg(sd, REG_AVID_STOP_PIXEL_MSB);
405 dump_reg(sd, REG_HSYNC_START_PIXEL_LSB);
406 dump_reg(sd, REG_HSYNC_START_PIXEL_MSB);
407 dump_reg(sd, REG_HSYNC_STOP_PIXEL_LSB);
408 dump_reg(sd, REG_HSYNC_STOP_PIXEL_MSB);
409 dump_reg(sd, REG_VSYNC_START_LINE_LSB);
410 dump_reg(sd, REG_VSYNC_START_LINE_MSB);
411 dump_reg(sd, REG_VSYNC_STOP_LINE_LSB);
412 dump_reg(sd, REG_VSYNC_STOP_LINE_MSB);
413 dump_reg(sd, REG_VBLK_START_LINE_LSB);
414 dump_reg(sd, REG_VBLK_START_LINE_MSB);
415 dump_reg(sd, REG_VBLK_STOP_LINE_LSB);
416 dump_reg(sd, REG_VBLK_STOP_LINE_MSB);
417 dump_reg(sd, REG_SYNC_CONTROL);
418 dump_reg(sd, REG_OUTPUT_FORMATTER1);
419 dump_reg(sd, REG_OUTPUT_FORMATTER2);
420 dump_reg(sd, REG_OUTPUT_FORMATTER3);
421 dump_reg(sd, REG_OUTPUT_FORMATTER4);
422 dump_reg(sd, REG_OUTPUT_FORMATTER5);
423 dump_reg(sd, REG_OUTPUT_FORMATTER6);
424 dump_reg(sd, REG_CLEAR_LOST_LOCK);
425}
426
427
428
429
430
431
432
433
434static int tvp514x_configure(struct v4l2_subdev *sd,
435 struct tvp514x_decoder *decoder)
436{
437 int err;
438
439
440 err =
441 tvp514x_write_regs(sd, decoder->tvp514x_regs);
442 if (err)
443 return err;
444
445 if (debug)
446 tvp514x_reg_dump(sd);
447
448 return 0;
449}
450
451
452
453
454
455
456
457
458
459
460
461
462static int tvp514x_detect(struct v4l2_subdev *sd,
463 struct tvp514x_decoder *decoder)
464{
465 u8 chip_id_msb, chip_id_lsb, rom_ver;
466 struct i2c_client *client = v4l2_get_subdevdata(sd);
467
468 chip_id_msb = tvp514x_read_reg(sd, REG_CHIP_ID_MSB);
469 chip_id_lsb = tvp514x_read_reg(sd, REG_CHIP_ID_LSB);
470 rom_ver = tvp514x_read_reg(sd, REG_ROM_VERSION);
471
472 v4l2_dbg(1, debug, sd,
473 "chip id detected msb:0x%x lsb:0x%x rom version:0x%x\n",
474 chip_id_msb, chip_id_lsb, rom_ver);
475 if ((chip_id_msb != TVP514X_CHIP_ID_MSB)
476 || ((chip_id_lsb != TVP5146_CHIP_ID_LSB)
477 && (chip_id_lsb != TVP5147_CHIP_ID_LSB))) {
478
479
480
481 v4l2_err(sd, "chip id mismatch msb:0x%x lsb:0x%x\n",
482 chip_id_msb, chip_id_lsb);
483 return -ENODEV;
484 }
485
486 decoder->ver = rom_ver;
487
488 v4l2_info(sd, "%s (Version - 0x%.2x) found at 0x%x (%s)\n",
489 client->name, decoder->ver,
490 client->addr << 1, client->adapter->name);
491 return 0;
492}
493
494
495
496
497
498
499
500
501
502static int tvp514x_querystd(struct v4l2_subdev *sd, v4l2_std_id *std_id)
503{
504 struct tvp514x_decoder *decoder = to_decoder(sd);
505 enum tvp514x_std current_std;
506 enum tvp514x_input input_sel;
507 u8 sync_lock_status, lock_mask;
508
509 if (std_id == NULL)
510 return -EINVAL;
511
512 *std_id = V4L2_STD_UNKNOWN;
513
514
515 current_std = tvp514x_query_current_std(sd);
516 if (current_std == STD_INVALID)
517 return 0;
518
519 input_sel = decoder->input;
520
521 switch (input_sel) {
522 case INPUT_CVBS_VI1A:
523 case INPUT_CVBS_VI1B:
524 case INPUT_CVBS_VI1C:
525 case INPUT_CVBS_VI2A:
526 case INPUT_CVBS_VI2B:
527 case INPUT_CVBS_VI2C:
528 case INPUT_CVBS_VI3A:
529 case INPUT_CVBS_VI3B:
530 case INPUT_CVBS_VI3C:
531 case INPUT_CVBS_VI4A:
532 lock_mask = STATUS_CLR_SUBCAR_LOCK_BIT |
533 STATUS_HORZ_SYNC_LOCK_BIT |
534 STATUS_VIRT_SYNC_LOCK_BIT;
535 break;
536
537 case INPUT_SVIDEO_VI2A_VI1A:
538 case INPUT_SVIDEO_VI2B_VI1B:
539 case INPUT_SVIDEO_VI2C_VI1C:
540 case INPUT_SVIDEO_VI2A_VI3A:
541 case INPUT_SVIDEO_VI2B_VI3B:
542 case INPUT_SVIDEO_VI2C_VI3C:
543 case INPUT_SVIDEO_VI4A_VI1A:
544 case INPUT_SVIDEO_VI4A_VI1B:
545 case INPUT_SVIDEO_VI4A_VI1C:
546 case INPUT_SVIDEO_VI4A_VI3A:
547 case INPUT_SVIDEO_VI4A_VI3B:
548 case INPUT_SVIDEO_VI4A_VI3C:
549 lock_mask = STATUS_HORZ_SYNC_LOCK_BIT |
550 STATUS_VIRT_SYNC_LOCK_BIT;
551 break;
552
553 default:
554 return -EINVAL;
555 }
556
557 sync_lock_status = tvp514x_read_reg(sd, REG_STATUS1);
558 if (lock_mask != (sync_lock_status & lock_mask))
559 return 0;
560
561 *std_id = decoder->std_list[current_std].standard.id;
562
563 v4l2_dbg(1, debug, sd, "Current STD: %s\n",
564 decoder->std_list[current_std].standard.name);
565 return 0;
566}
567
568
569
570
571
572
573
574
575
576static int tvp514x_s_std(struct v4l2_subdev *sd, v4l2_std_id std_id)
577{
578 struct tvp514x_decoder *decoder = to_decoder(sd);
579 int err, i;
580
581 for (i = 0; i < decoder->num_stds; i++)
582 if (std_id & decoder->std_list[i].standard.id)
583 break;
584
585 if ((i == decoder->num_stds) || (i == STD_INVALID))
586 return -EINVAL;
587
588 err = tvp514x_write_reg(sd, REG_VIDEO_STD,
589 decoder->std_list[i].video_std);
590 if (err)
591 return err;
592
593 decoder->current_std = i;
594 decoder->tvp514x_regs[REG_VIDEO_STD].val =
595 decoder->std_list[i].video_std;
596
597 v4l2_dbg(1, debug, sd, "Standard set to: %s\n",
598 decoder->std_list[i].standard.name);
599 return 0;
600}
601
602
603
604
605
606
607
608
609
610
611
612
613static int tvp514x_s_routing(struct v4l2_subdev *sd,
614 u32 input, u32 output, u32 config)
615{
616 struct tvp514x_decoder *decoder = to_decoder(sd);
617 int err;
618 enum tvp514x_input input_sel;
619 enum tvp514x_output output_sel;
620 u8 sync_lock_status, lock_mask;
621 int try_count = LOCK_RETRY_COUNT;
622
623 if ((input >= INPUT_INVALID) ||
624 (output >= OUTPUT_INVALID))
625
626 return -EINVAL;
627
628
629
630
631
632
633
634
635
636 if (!decoder->streaming)
637 tvp514x_s_stream(sd, 1);
638
639 input_sel = input;
640 output_sel = output;
641
642 err = tvp514x_write_reg(sd, REG_INPUT_SEL, input_sel);
643 if (err)
644 return err;
645
646 output_sel |= tvp514x_read_reg(sd,
647 REG_OUTPUT_FORMATTER1) & 0x7;
648 err = tvp514x_write_reg(sd, REG_OUTPUT_FORMATTER1,
649 output_sel);
650 if (err)
651 return err;
652
653 decoder->tvp514x_regs[REG_INPUT_SEL].val = input_sel;
654 decoder->tvp514x_regs[REG_OUTPUT_FORMATTER1].val = output_sel;
655
656
657 msleep(LOCK_RETRY_DELAY);
658 err =
659 tvp514x_write_reg(sd, REG_CLEAR_LOST_LOCK, 0x01);
660 if (err)
661 return err;
662
663 switch (input_sel) {
664 case INPUT_CVBS_VI1A:
665 case INPUT_CVBS_VI1B:
666 case INPUT_CVBS_VI1C:
667 case INPUT_CVBS_VI2A:
668 case INPUT_CVBS_VI2B:
669 case INPUT_CVBS_VI2C:
670 case INPUT_CVBS_VI3A:
671 case INPUT_CVBS_VI3B:
672 case INPUT_CVBS_VI3C:
673 case INPUT_CVBS_VI4A:
674 lock_mask = STATUS_CLR_SUBCAR_LOCK_BIT |
675 STATUS_HORZ_SYNC_LOCK_BIT |
676 STATUS_VIRT_SYNC_LOCK_BIT;
677 break;
678
679 case INPUT_SVIDEO_VI2A_VI1A:
680 case INPUT_SVIDEO_VI2B_VI1B:
681 case INPUT_SVIDEO_VI2C_VI1C:
682 case INPUT_SVIDEO_VI2A_VI3A:
683 case INPUT_SVIDEO_VI2B_VI3B:
684 case INPUT_SVIDEO_VI2C_VI3C:
685 case INPUT_SVIDEO_VI4A_VI1A:
686 case INPUT_SVIDEO_VI4A_VI1B:
687 case INPUT_SVIDEO_VI4A_VI1C:
688 case INPUT_SVIDEO_VI4A_VI3A:
689 case INPUT_SVIDEO_VI4A_VI3B:
690 case INPUT_SVIDEO_VI4A_VI3C:
691 lock_mask = STATUS_HORZ_SYNC_LOCK_BIT |
692 STATUS_VIRT_SYNC_LOCK_BIT;
693 break;
694
695 default:
696 return -EINVAL;
697 }
698
699 while (try_count-- > 0) {
700
701 msleep(LOCK_RETRY_DELAY);
702
703 sync_lock_status = tvp514x_read_reg(sd,
704 REG_STATUS1);
705 if (lock_mask == (sync_lock_status & lock_mask))
706
707 break;
708 }
709
710 if (try_count < 0)
711 return -EINVAL;
712
713 decoder->input = input;
714 decoder->output = output;
715
716 v4l2_dbg(1, debug, sd, "Input set to: %d\n", input_sel);
717
718 return 0;
719}
720
721
722
723
724
725
726
727
728
729static int
730tvp514x_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qctrl)
731{
732 int err = -EINVAL;
733
734 if (qctrl == NULL)
735 return err;
736
737 switch (qctrl->id) {
738 case V4L2_CID_BRIGHTNESS:
739
740 err = v4l2_ctrl_query_fill(qctrl, 0, 255, 1, 128);
741 break;
742 case V4L2_CID_CONTRAST:
743 case V4L2_CID_SATURATION:
744
745
746
747
748
749 err = v4l2_ctrl_query_fill(qctrl, 0, 255, 1, 128);
750 break;
751 case V4L2_CID_HUE:
752
753
754
755 err = v4l2_ctrl_query_fill(qctrl, -180, 180, 180, 0);
756 break;
757 case V4L2_CID_AUTOGAIN:
758
759
760
761
762 err = v4l2_ctrl_query_fill(qctrl, 0, 1, 1, 1);
763 break;
764 default:
765 v4l2_err(sd, "invalid control id %d\n", qctrl->id);
766 return err;
767 }
768
769 v4l2_dbg(1, debug, sd, "Query Control:%s: Min - %d, Max - %d, Def - %d\n",
770 qctrl->name, qctrl->minimum, qctrl->maximum,
771 qctrl->default_value);
772
773 return err;
774}
775
776
777
778
779
780
781
782
783
784
785static int
786tvp514x_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
787{
788 struct tvp514x_decoder *decoder = to_decoder(sd);
789
790 if (ctrl == NULL)
791 return -EINVAL;
792
793 switch (ctrl->id) {
794 case V4L2_CID_BRIGHTNESS:
795 ctrl->value = decoder->tvp514x_regs[REG_BRIGHTNESS].val;
796 break;
797 case V4L2_CID_CONTRAST:
798 ctrl->value = decoder->tvp514x_regs[REG_CONTRAST].val;
799 break;
800 case V4L2_CID_SATURATION:
801 ctrl->value = decoder->tvp514x_regs[REG_SATURATION].val;
802 break;
803 case V4L2_CID_HUE:
804 ctrl->value = decoder->tvp514x_regs[REG_HUE].val;
805 if (ctrl->value == 0x7F)
806 ctrl->value = 180;
807 else if (ctrl->value == 0x80)
808 ctrl->value = -180;
809 else
810 ctrl->value = 0;
811
812 break;
813 case V4L2_CID_AUTOGAIN:
814 ctrl->value = decoder->tvp514x_regs[REG_AFE_GAIN_CTRL].val;
815 if ((ctrl->value & 0x3) == 3)
816 ctrl->value = 1;
817 else
818 ctrl->value = 0;
819
820 break;
821 default:
822 v4l2_err(sd, "invalid control id %d\n", ctrl->id);
823 return -EINVAL;
824 }
825
826 v4l2_dbg(1, debug, sd, "Get Control: ID - %d - %d\n",
827 ctrl->id, ctrl->value);
828 return 0;
829}
830
831
832
833
834
835
836
837
838
839static int
840tvp514x_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
841{
842 struct tvp514x_decoder *decoder = to_decoder(sd);
843 int err = -EINVAL, value;
844
845 if (ctrl == NULL)
846 return err;
847
848 value = ctrl->value;
849
850 switch (ctrl->id) {
851 case V4L2_CID_BRIGHTNESS:
852 if (ctrl->value < 0 || ctrl->value > 255) {
853 v4l2_err(sd, "invalid brightness setting %d\n",
854 ctrl->value);
855 return -ERANGE;
856 }
857 err = tvp514x_write_reg(sd, REG_BRIGHTNESS,
858 value);
859 if (err)
860 return err;
861
862 decoder->tvp514x_regs[REG_BRIGHTNESS].val = value;
863 break;
864 case V4L2_CID_CONTRAST:
865 if (ctrl->value < 0 || ctrl->value > 255) {
866 v4l2_err(sd, "invalid contrast setting %d\n",
867 ctrl->value);
868 return -ERANGE;
869 }
870 err = tvp514x_write_reg(sd, REG_CONTRAST, value);
871 if (err)
872 return err;
873
874 decoder->tvp514x_regs[REG_CONTRAST].val = value;
875 break;
876 case V4L2_CID_SATURATION:
877 if (ctrl->value < 0 || ctrl->value > 255) {
878 v4l2_err(sd, "invalid saturation setting %d\n",
879 ctrl->value);
880 return -ERANGE;
881 }
882 err = tvp514x_write_reg(sd, REG_SATURATION, value);
883 if (err)
884 return err;
885
886 decoder->tvp514x_regs[REG_SATURATION].val = value;
887 break;
888 case V4L2_CID_HUE:
889 if (value == 180)
890 value = 0x7F;
891 else if (value == -180)
892 value = 0x80;
893 else if (value == 0)
894 value = 0;
895 else {
896 v4l2_err(sd, "invalid hue setting %d\n", ctrl->value);
897 return -ERANGE;
898 }
899 err = tvp514x_write_reg(sd, REG_HUE, value);
900 if (err)
901 return err;
902
903 decoder->tvp514x_regs[REG_HUE].val = value;
904 break;
905 case V4L2_CID_AUTOGAIN:
906 if (value == 1)
907 value = 0x0F;
908 else if (value == 0)
909 value = 0x0C;
910 else {
911 v4l2_err(sd, "invalid auto gain setting %d\n",
912 ctrl->value);
913 return -ERANGE;
914 }
915 err = tvp514x_write_reg(sd, REG_AFE_GAIN_CTRL, value);
916 if (err)
917 return err;
918
919 decoder->tvp514x_regs[REG_AFE_GAIN_CTRL].val = value;
920 break;
921 default:
922 v4l2_err(sd, "invalid control id %d\n", ctrl->id);
923 return err;
924 }
925
926 v4l2_dbg(1, debug, sd, "Set Control: ID - %d - %d\n",
927 ctrl->id, ctrl->value);
928
929 return err;
930}
931
932
933
934
935
936
937
938
939
940static int
941tvp514x_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index,
942 enum v4l2_mbus_pixelcode *code)
943{
944 if (index)
945 return -EINVAL;
946
947 *code = V4L2_MBUS_FMT_YUYV10_2X10;
948 return 0;
949}
950
951
952
953
954
955
956
957
958static int
959tvp514x_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *f)
960{
961 struct tvp514x_decoder *decoder = to_decoder(sd);
962 enum tvp514x_std current_std;
963
964 if (f == NULL)
965 return -EINVAL;
966
967
968 current_std = decoder->current_std;
969
970 f->code = V4L2_MBUS_FMT_YUYV10_2X10;
971 f->width = decoder->std_list[current_std].width;
972 f->height = decoder->std_list[current_std].height;
973 f->field = V4L2_FIELD_INTERLACED;
974 f->colorspace = V4L2_COLORSPACE_SMPTE170M;
975
976 v4l2_dbg(1, debug, sd, "MBUS_FMT: Width - %d, Height - %d\n",
977 f->width, f->height);
978 return 0;
979}
980
981
982
983
984
985
986
987
988static int
989tvp514x_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a)
990{
991 struct tvp514x_decoder *decoder = to_decoder(sd);
992 struct v4l2_captureparm *cparm;
993 enum tvp514x_std current_std;
994
995 if (a == NULL)
996 return -EINVAL;
997
998 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
999
1000 return -EINVAL;
1001
1002
1003 current_std = decoder->current_std;
1004
1005 cparm = &a->parm.capture;
1006 cparm->capability = V4L2_CAP_TIMEPERFRAME;
1007 cparm->timeperframe =
1008 decoder->std_list[current_std].standard.frameperiod;
1009
1010 return 0;
1011}
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021static int
1022tvp514x_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a)
1023{
1024 struct tvp514x_decoder *decoder = to_decoder(sd);
1025 struct v4l2_fract *timeperframe;
1026 enum tvp514x_std current_std;
1027
1028 if (a == NULL)
1029 return -EINVAL;
1030
1031 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1032
1033 return -EINVAL;
1034
1035 timeperframe = &a->parm.capture.timeperframe;
1036
1037
1038 current_std = decoder->current_std;
1039
1040 *timeperframe =
1041 decoder->std_list[current_std].standard.frameperiod;
1042
1043 return 0;
1044}
1045
1046
1047
1048
1049
1050
1051
1052
1053static int tvp514x_s_stream(struct v4l2_subdev *sd, int enable)
1054{
1055 int err = 0;
1056 struct i2c_client *client = v4l2_get_subdevdata(sd);
1057 struct tvp514x_decoder *decoder = to_decoder(sd);
1058
1059 if (decoder->streaming == enable)
1060 return 0;
1061
1062 switch (enable) {
1063 case 0:
1064 {
1065
1066 err = tvp514x_write_reg(sd, REG_OPERATION_MODE, 0x01);
1067 if (err) {
1068 v4l2_err(sd, "Unable to turn off decoder\n");
1069 return err;
1070 }
1071 decoder->streaming = enable;
1072 break;
1073 }
1074 case 1:
1075 {
1076 struct tvp514x_reg *int_seq = (struct tvp514x_reg *)
1077 client->driver->id_table->driver_data;
1078
1079
1080 err = tvp514x_write_regs(sd, int_seq);
1081 if (err) {
1082 v4l2_err(sd, "Unable to turn on decoder\n");
1083 return err;
1084 }
1085
1086 err = tvp514x_detect(sd, decoder);
1087 if (err) {
1088 v4l2_err(sd, "Unable to detect decoder\n");
1089 return err;
1090 }
1091 err = tvp514x_configure(sd, decoder);
1092 if (err) {
1093 v4l2_err(sd, "Unable to configure decoder\n");
1094 return err;
1095 }
1096 decoder->streaming = enable;
1097 break;
1098 }
1099 default:
1100 err = -ENODEV;
1101 break;
1102 }
1103
1104 return err;
1105}
1106
1107static const struct v4l2_subdev_core_ops tvp514x_core_ops = {
1108 .queryctrl = tvp514x_queryctrl,
1109 .g_ctrl = tvp514x_g_ctrl,
1110 .s_ctrl = tvp514x_s_ctrl,
1111 .s_std = tvp514x_s_std,
1112};
1113
1114static const struct v4l2_subdev_video_ops tvp514x_video_ops = {
1115 .s_routing = tvp514x_s_routing,
1116 .querystd = tvp514x_querystd,
1117 .enum_mbus_fmt = tvp514x_enum_mbus_fmt,
1118 .g_mbus_fmt = tvp514x_mbus_fmt,
1119 .try_mbus_fmt = tvp514x_mbus_fmt,
1120 .s_mbus_fmt = tvp514x_mbus_fmt,
1121 .g_parm = tvp514x_g_parm,
1122 .s_parm = tvp514x_s_parm,
1123 .s_stream = tvp514x_s_stream,
1124};
1125
1126static const struct v4l2_subdev_ops tvp514x_ops = {
1127 .core = &tvp514x_core_ops,
1128 .video = &tvp514x_video_ops,
1129};
1130
1131static struct tvp514x_decoder tvp514x_dev = {
1132 .streaming = 0,
1133 .current_std = STD_NTSC_MJ,
1134 .std_list = tvp514x_std_list,
1135 .num_stds = ARRAY_SIZE(tvp514x_std_list),
1136
1137};
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147static int
1148tvp514x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1149{
1150 struct tvp514x_decoder *decoder;
1151 struct v4l2_subdev *sd;
1152
1153
1154 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1155 return -EIO;
1156
1157 if (!client->dev.platform_data) {
1158 v4l2_err(client, "No platform data!!\n");
1159 return -ENODEV;
1160 }
1161
1162 decoder = kzalloc(sizeof(*decoder), GFP_KERNEL);
1163 if (!decoder)
1164 return -ENOMEM;
1165
1166
1167 *decoder = tvp514x_dev;
1168
1169 memcpy(decoder->tvp514x_regs, tvp514x_reg_list_default,
1170 sizeof(tvp514x_reg_list_default));
1171
1172
1173 decoder->pdata = client->dev.platform_data;
1174
1175
1176
1177
1178
1179
1180 decoder->tvp514x_regs[REG_OUTPUT_FORMATTER2].val |=
1181 (decoder->pdata->clk_polarity << 1);
1182 decoder->tvp514x_regs[REG_SYNC_CONTROL].val |=
1183 ((decoder->pdata->hs_polarity << 2) |
1184 (decoder->pdata->vs_polarity << 3));
1185
1186 decoder->tvp514x_regs[REG_VIDEO_STD].val =
1187 VIDEO_STD_AUTO_SWITCH_BIT;
1188
1189
1190 sd = &decoder->sd;
1191 v4l2_i2c_subdev_init(sd, client, &tvp514x_ops);
1192
1193 v4l2_info(sd, "%s decoder driver registered !!\n", sd->name);
1194
1195 return 0;
1196
1197}
1198
1199
1200
1201
1202
1203
1204
1205
1206static int tvp514x_remove(struct i2c_client *client)
1207{
1208 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1209 struct tvp514x_decoder *decoder = to_decoder(sd);
1210
1211 v4l2_device_unregister_subdev(sd);
1212 kfree(decoder);
1213 return 0;
1214}
1215
1216static const struct tvp514x_reg tvp5146_init_reg_seq[] = {
1217 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x02},
1218 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1219 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0x80},
1220 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x01},
1221 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x60},
1222 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1223 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0xB0},
1224 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x01},
1225 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x00},
1226 {TOK_WRITE, REG_OPERATION_MODE, 0x01},
1227 {TOK_WRITE, REG_OPERATION_MODE, 0x00},
1228 {TOK_TERM, 0, 0},
1229};
1230
1231
1232static const struct tvp514x_reg tvp5147_init_reg_seq[] = {
1233 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x02},
1234 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1235 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0x80},
1236 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x01},
1237 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x60},
1238 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1239 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0xB0},
1240 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x01},
1241 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x16},
1242 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1243 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0xA0},
1244 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x16},
1245 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x60},
1246 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1247 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0xB0},
1248 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x00},
1249 {TOK_WRITE, REG_OPERATION_MODE, 0x01},
1250 {TOK_WRITE, REG_OPERATION_MODE, 0x00},
1251 {TOK_TERM, 0, 0},
1252};
1253
1254
1255static const struct tvp514x_reg tvp514xm_init_reg_seq[] = {
1256 {TOK_WRITE, REG_OPERATION_MODE, 0x01},
1257 {TOK_WRITE, REG_OPERATION_MODE, 0x00},
1258 {TOK_TERM, 0, 0},
1259};
1260
1261
1262
1263
1264
1265
1266
1267static const struct i2c_device_id tvp514x_id[] = {
1268 {"tvp5146", (unsigned long)tvp5146_init_reg_seq},
1269 {"tvp5146m2", (unsigned long)tvp514xm_init_reg_seq},
1270 {"tvp5147", (unsigned long)tvp5147_init_reg_seq},
1271 {"tvp5147m1", (unsigned long)tvp514xm_init_reg_seq},
1272 {},
1273};
1274
1275MODULE_DEVICE_TABLE(i2c, tvp514x_id);
1276
1277static struct i2c_driver tvp514x_driver = {
1278 .driver = {
1279 .owner = THIS_MODULE,
1280 .name = TVP514X_MODULE_NAME,
1281 },
1282 .probe = tvp514x_probe,
1283 .remove = tvp514x_remove,
1284 .id_table = tvp514x_id,
1285};
1286
1287static int __init tvp514x_init(void)
1288{
1289 return i2c_add_driver(&tvp514x_driver);
1290}
1291
1292static void __exit tvp514x_exit(void)
1293{
1294 i2c_del_driver(&tvp514x_driver);
1295}
1296
1297module_init(tvp514x_init);
1298module_exit(tvp514x_exit);
1299