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18#include <linux/err.h>
19#include <linux/irq.h>
20#include <linux/interrupt.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/platform_device.h>
24#include <linux/slab.h>
25#include <linux/spinlock.h>
26
27#include <linux/clk.h>
28#include <linux/mfd/core.h>
29
30#include <linux/jz4740-adc.h>
31
32
33#define JZ_REG_ADC_ENABLE 0x00
34#define JZ_REG_ADC_CFG 0x04
35#define JZ_REG_ADC_CTRL 0x08
36#define JZ_REG_ADC_STATUS 0x0c
37
38#define JZ_REG_ADC_TOUCHSCREEN_BASE 0x10
39#define JZ_REG_ADC_BATTERY_BASE 0x1c
40#define JZ_REG_ADC_HWMON_BASE 0x20
41
42#define JZ_ADC_ENABLE_TOUCH BIT(2)
43#define JZ_ADC_ENABLE_BATTERY BIT(1)
44#define JZ_ADC_ENABLE_ADCIN BIT(0)
45
46enum {
47 JZ_ADC_IRQ_ADCIN = 0,
48 JZ_ADC_IRQ_BATTERY,
49 JZ_ADC_IRQ_TOUCH,
50 JZ_ADC_IRQ_PENUP,
51 JZ_ADC_IRQ_PENDOWN,
52};
53
54struct jz4740_adc {
55 struct resource *mem;
56 void __iomem *base;
57
58 int irq;
59 int irq_base;
60
61 struct clk *clk;
62 atomic_t clk_ref;
63
64 spinlock_t lock;
65};
66
67static inline void jz4740_adc_irq_set_masked(struct jz4740_adc *adc, int irq,
68 bool masked)
69{
70 unsigned long flags;
71 uint8_t val;
72
73 irq -= adc->irq_base;
74
75 spin_lock_irqsave(&adc->lock, flags);
76
77 val = readb(adc->base + JZ_REG_ADC_CTRL);
78 if (masked)
79 val |= BIT(irq);
80 else
81 val &= ~BIT(irq);
82 writeb(val, adc->base + JZ_REG_ADC_CTRL);
83
84 spin_unlock_irqrestore(&adc->lock, flags);
85}
86
87static void jz4740_adc_irq_mask(struct irq_data *data)
88{
89 struct jz4740_adc *adc = irq_data_get_irq_chip_data(data);
90 jz4740_adc_irq_set_masked(adc, data->irq, true);
91}
92
93static void jz4740_adc_irq_unmask(struct irq_data *data)
94{
95 struct jz4740_adc *adc = irq_data_get_irq_chip_data(data);
96 jz4740_adc_irq_set_masked(adc, data->irq, false);
97}
98
99static void jz4740_adc_irq_ack(struct irq_data *data)
100{
101 struct jz4740_adc *adc = irq_data_get_irq_chip_data(data);
102 unsigned int irq = data->irq - adc->irq_base;
103 writeb(BIT(irq), adc->base + JZ_REG_ADC_STATUS);
104}
105
106static struct irq_chip jz4740_adc_irq_chip = {
107 .name = "jz4740-adc",
108 .irq_mask = jz4740_adc_irq_mask,
109 .irq_unmask = jz4740_adc_irq_unmask,
110 .irq_ack = jz4740_adc_irq_ack,
111};
112
113static void jz4740_adc_irq_demux(unsigned int irq, struct irq_desc *desc)
114{
115 struct jz4740_adc *adc = get_irq_desc_data(desc);
116 uint8_t status;
117 unsigned int i;
118
119 status = readb(adc->base + JZ_REG_ADC_STATUS);
120
121 for (i = 0; i < 5; ++i) {
122 if (status & BIT(i))
123 generic_handle_irq(adc->irq_base + i);
124 }
125}
126
127
128
129
130
131static inline void jz4740_adc_clk_enable(struct jz4740_adc *adc)
132{
133 if (atomic_inc_return(&adc->clk_ref) == 1)
134 clk_enable(adc->clk);
135}
136
137static inline void jz4740_adc_clk_disable(struct jz4740_adc *adc)
138{
139 if (atomic_dec_return(&adc->clk_ref) == 0)
140 clk_disable(adc->clk);
141}
142
143static inline void jz4740_adc_set_enabled(struct jz4740_adc *adc, int engine,
144 bool enabled)
145{
146 unsigned long flags;
147 uint8_t val;
148
149 spin_lock_irqsave(&adc->lock, flags);
150
151 val = readb(adc->base + JZ_REG_ADC_ENABLE);
152 if (enabled)
153 val |= BIT(engine);
154 else
155 val &= ~BIT(engine);
156 writeb(val, adc->base + JZ_REG_ADC_ENABLE);
157
158 spin_unlock_irqrestore(&adc->lock, flags);
159}
160
161static int jz4740_adc_cell_enable(struct platform_device *pdev)
162{
163 struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent);
164
165 jz4740_adc_clk_enable(adc);
166 jz4740_adc_set_enabled(adc, pdev->id, true);
167
168 return 0;
169}
170
171static int jz4740_adc_cell_disable(struct platform_device *pdev)
172{
173 struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent);
174
175 jz4740_adc_set_enabled(adc, pdev->id, false);
176 jz4740_adc_clk_disable(adc);
177
178 return 0;
179}
180
181int jz4740_adc_set_config(struct device *dev, uint32_t mask, uint32_t val)
182{
183 struct jz4740_adc *adc = dev_get_drvdata(dev);
184 unsigned long flags;
185 uint32_t cfg;
186
187 if (!adc)
188 return -ENODEV;
189
190 spin_lock_irqsave(&adc->lock, flags);
191
192 cfg = readl(adc->base + JZ_REG_ADC_CFG);
193
194 cfg &= ~mask;
195 cfg |= val;
196
197 writel(cfg, adc->base + JZ_REG_ADC_CFG);
198
199 spin_unlock_irqrestore(&adc->lock, flags);
200
201 return 0;
202}
203EXPORT_SYMBOL_GPL(jz4740_adc_set_config);
204
205static struct resource jz4740_hwmon_resources[] = {
206 {
207 .start = JZ_ADC_IRQ_ADCIN,
208 .flags = IORESOURCE_IRQ,
209 },
210 {
211 .start = JZ_REG_ADC_HWMON_BASE,
212 .end = JZ_REG_ADC_HWMON_BASE + 3,
213 .flags = IORESOURCE_MEM,
214 },
215};
216
217static struct resource jz4740_battery_resources[] = {
218 {
219 .start = JZ_ADC_IRQ_BATTERY,
220 .flags = IORESOURCE_IRQ,
221 },
222 {
223 .start = JZ_REG_ADC_BATTERY_BASE,
224 .end = JZ_REG_ADC_BATTERY_BASE + 3,
225 .flags = IORESOURCE_MEM,
226 },
227};
228
229const struct mfd_cell jz4740_adc_cells[] = {
230 {
231 .id = 0,
232 .name = "jz4740-hwmon",
233 .num_resources = ARRAY_SIZE(jz4740_hwmon_resources),
234 .resources = jz4740_hwmon_resources,
235 .platform_data = (void *)&jz4740_adc_cells[0],
236 .data_size = sizeof(struct mfd_cell),
237
238 .enable = jz4740_adc_cell_enable,
239 .disable = jz4740_adc_cell_disable,
240 },
241 {
242 .id = 1,
243 .name = "jz4740-battery",
244 .num_resources = ARRAY_SIZE(jz4740_battery_resources),
245 .resources = jz4740_battery_resources,
246 .platform_data = (void *)&jz4740_adc_cells[1],
247 .data_size = sizeof(struct mfd_cell),
248
249 .enable = jz4740_adc_cell_enable,
250 .disable = jz4740_adc_cell_disable,
251 },
252};
253
254static int __devinit jz4740_adc_probe(struct platform_device *pdev)
255{
256 int ret;
257 struct jz4740_adc *adc;
258 struct resource *mem_base;
259 int irq;
260
261 adc = kmalloc(sizeof(*adc), GFP_KERNEL);
262 if (!adc) {
263 dev_err(&pdev->dev, "Failed to allocate driver structure\n");
264 return -ENOMEM;
265 }
266
267 adc->irq = platform_get_irq(pdev, 0);
268 if (adc->irq < 0) {
269 ret = adc->irq;
270 dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
271 goto err_free;
272 }
273
274 adc->irq_base = platform_get_irq(pdev, 1);
275 if (adc->irq_base < 0) {
276 ret = adc->irq_base;
277 dev_err(&pdev->dev, "Failed to get irq base: %d\n", ret);
278 goto err_free;
279 }
280
281 mem_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
282 if (!mem_base) {
283 ret = -ENOENT;
284 dev_err(&pdev->dev, "Failed to get platform mmio resource\n");
285 goto err_free;
286 }
287
288
289 adc->mem = request_mem_region(mem_base->start, JZ_REG_ADC_STATUS,
290 pdev->name);
291 if (!adc->mem) {
292 ret = -EBUSY;
293 dev_err(&pdev->dev, "Failed to request mmio memory region\n");
294 goto err_free;
295 }
296
297 adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem));
298 if (!adc->base) {
299 ret = -EBUSY;
300 dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
301 goto err_release_mem_region;
302 }
303
304 adc->clk = clk_get(&pdev->dev, "adc");
305 if (IS_ERR(adc->clk)) {
306 ret = PTR_ERR(adc->clk);
307 dev_err(&pdev->dev, "Failed to get clock: %d\n", ret);
308 goto err_iounmap;
309 }
310
311 spin_lock_init(&adc->lock);
312 atomic_set(&adc->clk_ref, 0);
313
314 platform_set_drvdata(pdev, adc);
315
316 for (irq = adc->irq_base; irq < adc->irq_base + 5; ++irq) {
317 set_irq_chip_data(irq, adc);
318 set_irq_chip_and_handler(irq, &jz4740_adc_irq_chip,
319 handle_level_irq);
320 }
321
322 set_irq_data(adc->irq, adc);
323 set_irq_chained_handler(adc->irq, jz4740_adc_irq_demux);
324
325 writeb(0x00, adc->base + JZ_REG_ADC_ENABLE);
326 writeb(0xff, adc->base + JZ_REG_ADC_CTRL);
327
328 ret = mfd_add_devices(&pdev->dev, 0, jz4740_adc_cells,
329 ARRAY_SIZE(jz4740_adc_cells), mem_base, adc->irq_base);
330 if (ret < 0)
331 goto err_clk_put;
332
333 return 0;
334
335err_clk_put:
336 clk_put(adc->clk);
337err_iounmap:
338 platform_set_drvdata(pdev, NULL);
339 iounmap(adc->base);
340err_release_mem_region:
341 release_mem_region(adc->mem->start, resource_size(adc->mem));
342err_free:
343 kfree(adc);
344
345 return ret;
346}
347
348static int __devexit jz4740_adc_remove(struct platform_device *pdev)
349{
350 struct jz4740_adc *adc = platform_get_drvdata(pdev);
351
352 mfd_remove_devices(&pdev->dev);
353
354 set_irq_data(adc->irq, NULL);
355 set_irq_chained_handler(adc->irq, NULL);
356
357 iounmap(adc->base);
358 release_mem_region(adc->mem->start, resource_size(adc->mem));
359
360 clk_put(adc->clk);
361
362 platform_set_drvdata(pdev, NULL);
363
364 kfree(adc);
365
366 return 0;
367}
368
369struct platform_driver jz4740_adc_driver = {
370 .probe = jz4740_adc_probe,
371 .remove = __devexit_p(jz4740_adc_remove),
372 .driver = {
373 .name = "jz4740-adc",
374 .owner = THIS_MODULE,
375 },
376};
377
378static int __init jz4740_adc_init(void)
379{
380 return platform_driver_register(&jz4740_adc_driver);
381}
382module_init(jz4740_adc_init);
383
384static void __exit jz4740_adc_exit(void)
385{
386 platform_driver_unregister(&jz4740_adc_driver);
387}
388module_exit(jz4740_adc_exit);
389
390MODULE_DESCRIPTION("JZ4740 SoC ADC driver");
391MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
392MODULE_LICENSE("GPL");
393MODULE_ALIAS("platform:jz4740-adc");
394
