LXR linux/drivers/mmc/host/sdhci-esdhc-imx.c

   1/*
   2 * Freescale eSDHC i.MX controller driver for the platform bus.
   3 *
   4 * derived from the OF-version.
   5 *
   6 * Copyright (c) 2010 Pengutronix e.K.
   7 *   Author: Wolfram Sang <w.sang@pengutronix.de>
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License as published by
  11 * the Free Software Foundation; either version 2 of the License.
  12 */
  13
  14#include <linux/io.h>
  15#include <linux/delay.h>
  16#include <linux/err.h>
  17#include <linux/clk.h>
  18#include <linux/mmc/host.h>
  19#include <linux/mmc/sdhci-pltfm.h>
  20#include <mach/hardware.h>
  21#include "sdhci.h"
  22#include "sdhci-pltfm.h"
  23#include "sdhci-esdhc.h"
  24
  25static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
  26{
  27        void __iomem *base = host->ioaddr + (reg & ~0x3);
  28        u32 shift = (reg & 0x3) * 8;
  29
  30        writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
  31}
  32
  33static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
  34{
  35        if (unlikely(reg == SDHCI_HOST_VERSION))
  36                reg ^= 2;
  37
  38        return readw(host->ioaddr + reg);
  39}
  40
  41static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
  42{
  43        struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  44
  45        switch (reg) {
  46        case SDHCI_TRANSFER_MODE:
  47                /*
  48                 * Postpone this write, we must do it together with a
  49                 * command write that is down below.
  50                 */
  51                pltfm_host->scratchpad = val;
  52                return;
  53        case SDHCI_COMMAND:
  54                writel(val << 16 | pltfm_host->scratchpad,
  55                        host->ioaddr + SDHCI_TRANSFER_MODE);
  56                return;
  57        case SDHCI_BLOCK_SIZE:
  58                val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
  59                break;
  60        }
  61        esdhc_clrset_le(host, 0xffff, val, reg);
  62}
  63
  64static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
  65{
  66        u32 new_val;
  67
  68        switch (reg) {
  69        case SDHCI_POWER_CONTROL:
  70                /*
  71                 * FSL put some DMA bits here
  72                 * If your board has a regulator, code should be here
  73                 */
  74                return;
  75        case SDHCI_HOST_CONTROL:
  76                /* FSL messed up here, so we can just keep those two */
  77                new_val = val & (SDHCI_CTRL_LED | SDHCI_CTRL_4BITBUS);
  78                /* ensure the endianess */
  79                new_val |= ESDHC_HOST_CONTROL_LE;
  80                /* DMA mode bits are shifted */
  81                new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
  82
  83                esdhc_clrset_le(host, 0xffff, new_val, reg);
  84                return;
  85        }
  86        esdhc_clrset_le(host, 0xff, val, reg);
  87}
  88
  89static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
  90{
  91        struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  92
  93        return clk_get_rate(pltfm_host->clk);
  94}
  95
  96static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
  97{
  98        struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  99
 100        return clk_get_rate(pltfm_host->clk) / 256 / 16;
 101}
 102
 103static int esdhc_pltfm_init(struct sdhci_host *host, struct sdhci_pltfm_data *pdata)
 104{
 105        struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 106        struct clk *clk;
 107
 108        clk = clk_get(mmc_dev(host->mmc), NULL);
 109        if (IS_ERR(clk)) {
 110                dev_err(mmc_dev(host->mmc), "clk err\n");
 111                return PTR_ERR(clk);
 112        }
 113        clk_enable(clk);
 114        pltfm_host->clk = clk;
 115
 116        if (cpu_is_mx35() || cpu_is_mx51())
 117                host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
 118
 119        /* Fix errata ENGcm07207 which is present on i.MX25 and i.MX35 */
 120        if (cpu_is_mx25() || cpu_is_mx35())
 121                host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK;
 122
 123        return 0;
 124}
 125
 126static void esdhc_pltfm_exit(struct sdhci_host *host)
 127{
 128        struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 129
 130        clk_disable(pltfm_host->clk);
 131        clk_put(pltfm_host->clk);
 132}
 133
 134static struct sdhci_ops sdhci_esdhc_ops = {
 135        .read_w = esdhc_readw_le,
 136        .write_w = esdhc_writew_le,
 137        .write_b = esdhc_writeb_le,
 138        .set_clock = esdhc_set_clock,
 139        .get_max_clock = esdhc_pltfm_get_max_clock,
 140        .get_min_clock = esdhc_pltfm_get_min_clock,
 141};
 142
 143struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
 144        .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_ADMA,
 145        /* ADMA has issues. Might be fixable */
 146        .ops = &sdhci_esdhc_ops,
 147        .init = esdhc_pltfm_init,
 148        .exit = esdhc_pltfm_exit,
 149};
 150