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23#include <linux/module.h>
24#include <linux/types.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/init.h>
28#include <asm/io.h>
29#include <asm/byteorder.h>
30
31#include <linux/errno.h>
32#include <linux/slab.h>
33#include <linux/delay.h>
34#include <linux/interrupt.h>
35#include <linux/reboot.h>
36#include <linux/mtd/map.h>
37#include <linux/mtd/mtd.h>
38#include <linux/mtd/cfi.h>
39#include <linux/mtd/xip.h>
40
41#define AMD_BOOTLOC_BUG
42#define FORCE_WORD_WRITE 0
43
44#define MAX_WORD_RETRIES 3
45
46#define SST49LF004B 0x0060
47#define SST49LF040B 0x0050
48#define SST49LF008A 0x005a
49#define AT49BV6416 0x00d6
50
51static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
52static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
53static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
54static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
55static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
56static void cfi_amdstd_sync (struct mtd_info *);
57static int cfi_amdstd_suspend (struct mtd_info *);
58static void cfi_amdstd_resume (struct mtd_info *);
59static int cfi_amdstd_reboot(struct notifier_block *, unsigned long, void *);
60static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
61
62static void cfi_amdstd_destroy(struct mtd_info *);
63
64struct mtd_info *cfi_cmdset_0002(struct map_info *, int);
65static struct mtd_info *cfi_amdstd_setup (struct mtd_info *);
66
67static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode);
68static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr);
69#include "fwh_lock.h"
70
71static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
72static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
73
74static struct mtd_chip_driver cfi_amdstd_chipdrv = {
75 .probe = NULL,
76 .destroy = cfi_amdstd_destroy,
77 .name = "cfi_cmdset_0002",
78 .module = THIS_MODULE
79};
80
81
82
83
84
85#ifdef DEBUG_CFI_FEATURES
86static void cfi_tell_features(struct cfi_pri_amdstd *extp)
87{
88 const char* erase_suspend[3] = {
89 "Not supported", "Read only", "Read/write"
90 };
91 const char* top_bottom[6] = {
92 "No WP", "8x8KiB sectors at top & bottom, no WP",
93 "Bottom boot", "Top boot",
94 "Uniform, Bottom WP", "Uniform, Top WP"
95 };
96
97 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1);
98 printk(" Address sensitive unlock: %s\n",
99 (extp->SiliconRevision & 1) ? "Not required" : "Required");
100
101 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend))
102 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]);
103 else
104 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend);
105
106 if (extp->BlkProt == 0)
107 printk(" Block protection: Not supported\n");
108 else
109 printk(" Block protection: %d sectors per group\n", extp->BlkProt);
110
111
112 printk(" Temporary block unprotect: %s\n",
113 extp->TmpBlkUnprotect ? "Supported" : "Not supported");
114 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot);
115 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps);
116 printk(" Burst mode: %s\n",
117 extp->BurstMode ? "Supported" : "Not supported");
118 if (extp->PageMode == 0)
119 printk(" Page mode: Not supported\n");
120 else
121 printk(" Page mode: %d word page\n", extp->PageMode << 2);
122
123 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
124 extp->VppMin >> 4, extp->VppMin & 0xf);
125 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
126 extp->VppMax >> 4, extp->VppMax & 0xf);
127
128 if (extp->TopBottom < ARRAY_SIZE(top_bottom))
129 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]);
130 else
131 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom);
132}
133#endif
134
135#ifdef AMD_BOOTLOC_BUG
136
137static void fixup_amd_bootblock(struct mtd_info *mtd)
138{
139 struct map_info *map = mtd->priv;
140 struct cfi_private *cfi = map->fldrv_priv;
141 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
142 __u8 major = extp->MajorVersion;
143 __u8 minor = extp->MinorVersion;
144
145 if (((major << 8) | minor) < 0x3131) {
146
147
148 DEBUG(MTD_DEBUG_LEVEL1,
149 "%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n",
150 map->name, cfi->mfr, cfi->id);
151
152
153
154
155
156
157 if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) &&
158
159
160
161
162
163
164
165
166
167
168 (cfi->mfr == CFI_MFR_MACRONIX)) {
169 DEBUG(MTD_DEBUG_LEVEL1,
170 "%s: Macronix MX29LV400C with bottom boot block"
171 " detected\n", map->name);
172 extp->TopBottom = 2;
173 } else
174 if (cfi->id & 0x80) {
175 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id);
176 extp->TopBottom = 3;
177 } else {
178 extp->TopBottom = 2;
179 }
180
181 DEBUG(MTD_DEBUG_LEVEL1,
182 "%s: AMD CFI PRI V%c.%c has no boot block field;"
183 " deduced %s from Device ID\n", map->name, major, minor,
184 extp->TopBottom == 2 ? "bottom" : "top");
185 }
186}
187#endif
188
189static void fixup_use_write_buffers(struct mtd_info *mtd)
190{
191 struct map_info *map = mtd->priv;
192 struct cfi_private *cfi = map->fldrv_priv;
193 if (cfi->cfiq->BufWriteTimeoutTyp) {
194 DEBUG(MTD_DEBUG_LEVEL1, "Using buffer write method\n" );
195 mtd->write = cfi_amdstd_write_buffers;
196 }
197}
198
199
200static void fixup_convert_atmel_pri(struct mtd_info *mtd)
201{
202 struct map_info *map = mtd->priv;
203 struct cfi_private *cfi = map->fldrv_priv;
204 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
205 struct cfi_pri_atmel atmel_pri;
206
207 memcpy(&atmel_pri, extp, sizeof(atmel_pri));
208 memset((char *)extp + 5, 0, sizeof(*extp) - 5);
209
210 if (atmel_pri.Features & 0x02)
211 extp->EraseSuspend = 2;
212
213
214 if (cfi->id == AT49BV6416) {
215 if (atmel_pri.BottomBoot)
216 extp->TopBottom = 3;
217 else
218 extp->TopBottom = 2;
219 } else {
220 if (atmel_pri.BottomBoot)
221 extp->TopBottom = 2;
222 else
223 extp->TopBottom = 3;
224 }
225
226
227 cfi->cfiq->BufWriteTimeoutTyp = 0;
228 cfi->cfiq->BufWriteTimeoutMax = 0;
229}
230
231static void fixup_use_secsi(struct mtd_info *mtd)
232{
233
234 mtd->read_user_prot_reg = cfi_amdstd_secsi_read;
235 mtd->read_fact_prot_reg = cfi_amdstd_secsi_read;
236}
237
238static void fixup_use_erase_chip(struct mtd_info *mtd)
239{
240 struct map_info *map = mtd->priv;
241 struct cfi_private *cfi = map->fldrv_priv;
242 if ((cfi->cfiq->NumEraseRegions == 1) &&
243 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) {
244 mtd->erase = cfi_amdstd_erase_chip;
245 }
246
247}
248
249
250
251
252
253static void fixup_use_atmel_lock(struct mtd_info *mtd)
254{
255 mtd->lock = cfi_atmel_lock;
256 mtd->unlock = cfi_atmel_unlock;
257 mtd->flags |= MTD_POWERUP_LOCK;
258}
259
260static void fixup_old_sst_eraseregion(struct mtd_info *mtd)
261{
262 struct map_info *map = mtd->priv;
263 struct cfi_private *cfi = map->fldrv_priv;
264
265
266
267
268
269
270
271 cfi->cfiq->NumEraseRegions = 1;
272}
273
274static void fixup_sst39vf(struct mtd_info *mtd)
275{
276 struct map_info *map = mtd->priv;
277 struct cfi_private *cfi = map->fldrv_priv;
278
279 fixup_old_sst_eraseregion(mtd);
280
281 cfi->addr_unlock1 = 0x5555;
282 cfi->addr_unlock2 = 0x2AAA;
283}
284
285static void fixup_sst39vf_rev_b(struct mtd_info *mtd)
286{
287 struct map_info *map = mtd->priv;
288 struct cfi_private *cfi = map->fldrv_priv;
289
290 fixup_old_sst_eraseregion(mtd);
291
292 cfi->addr_unlock1 = 0x555;
293 cfi->addr_unlock2 = 0x2AA;
294
295 cfi->sector_erase_cmd = CMD(0x50);
296}
297
298static void fixup_sst38vf640x_sectorsize(struct mtd_info *mtd)
299{
300 struct map_info *map = mtd->priv;
301 struct cfi_private *cfi = map->fldrv_priv;
302
303 fixup_sst39vf_rev_b(mtd);
304
305
306
307
308
309 cfi->cfiq->EraseRegionInfo[0] = 0x002003ff;
310 pr_warning("%s: Bad 38VF640x CFI data; adjusting sector size from 64 to 8KiB\n", mtd->name);
311}
312
313static void fixup_s29gl064n_sectors(struct mtd_info *mtd)
314{
315 struct map_info *map = mtd->priv;
316 struct cfi_private *cfi = map->fldrv_priv;
317
318 if ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0x003f) {
319 cfi->cfiq->EraseRegionInfo[0] |= 0x0040;
320 pr_warning("%s: Bad S29GL064N CFI data, adjust from 64 to 128 sectors\n", mtd->name);
321 }
322}
323
324static void fixup_s29gl032n_sectors(struct mtd_info *mtd)
325{
326 struct map_info *map = mtd->priv;
327 struct cfi_private *cfi = map->fldrv_priv;
328
329 if ((cfi->cfiq->EraseRegionInfo[1] & 0xffff) == 0x007e) {
330 cfi->cfiq->EraseRegionInfo[1] &= ~0x0040;
331 pr_warning("%s: Bad S29GL032N CFI data, adjust from 127 to 63 sectors\n", mtd->name);
332 }
333}
334
335
336static struct cfi_fixup cfi_nopri_fixup_table[] = {
337 { CFI_MFR_SST, 0x234a, fixup_sst39vf },
338 { CFI_MFR_SST, 0x234b, fixup_sst39vf },
339 { CFI_MFR_SST, 0x235a, fixup_sst39vf },
340 { CFI_MFR_SST, 0x235b, fixup_sst39vf },
341 { CFI_MFR_SST, 0x235c, fixup_sst39vf_rev_b },
342 { CFI_MFR_SST, 0x235d, fixup_sst39vf_rev_b },
343 { CFI_MFR_SST, 0x236c, fixup_sst39vf_rev_b },
344 { CFI_MFR_SST, 0x236d, fixup_sst39vf_rev_b },
345 { 0, 0, NULL }
346};
347
348static struct cfi_fixup cfi_fixup_table[] = {
349 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri },
350#ifdef AMD_BOOTLOC_BUG
351 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock },
352 { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock },
353#endif
354 { CFI_MFR_AMD, 0x0050, fixup_use_secsi },
355 { CFI_MFR_AMD, 0x0053, fixup_use_secsi },
356 { CFI_MFR_AMD, 0x0055, fixup_use_secsi },
357 { CFI_MFR_AMD, 0x0056, fixup_use_secsi },
358 { CFI_MFR_AMD, 0x005C, fixup_use_secsi },
359 { CFI_MFR_AMD, 0x005F, fixup_use_secsi },
360 { CFI_MFR_AMD, 0x0c01, fixup_s29gl064n_sectors },
361 { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors },
362 { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors },
363 { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors },
364 { CFI_MFR_SST, 0x536a, fixup_sst38vf640x_sectorsize },
365 { CFI_MFR_SST, 0x536b, fixup_sst38vf640x_sectorsize },
366 { CFI_MFR_SST, 0x536c, fixup_sst38vf640x_sectorsize },
367 { CFI_MFR_SST, 0x536d, fixup_sst38vf640x_sectorsize },
368#if !FORCE_WORD_WRITE
369 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers },
370#endif
371 { 0, 0, NULL }
372};
373static struct cfi_fixup jedec_fixup_table[] = {
374 { CFI_MFR_SST, SST49LF004B, fixup_use_fwh_lock },
375 { CFI_MFR_SST, SST49LF040B, fixup_use_fwh_lock },
376 { CFI_MFR_SST, SST49LF008A, fixup_use_fwh_lock },
377 { 0, 0, NULL }
378};
379
380static struct cfi_fixup fixup_table[] = {
381
382
383
384
385
386 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip },
387 { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock },
388 { 0, 0, NULL }
389};
390
391
392static void cfi_fixup_major_minor(struct cfi_private *cfi,
393 struct cfi_pri_amdstd *extp)
394{
395 if (cfi->mfr == CFI_MFR_SAMSUNG) {
396 if ((extp->MajorVersion == '0' && extp->MinorVersion == '0') ||
397 (extp->MajorVersion == '3' && extp->MinorVersion == '3')) {
398
399
400
401
402
403 printk(KERN_NOTICE " Fixing Samsung's Amd/Fujitsu"
404 " Extended Query version to 1.%c\n",
405 extp->MinorVersion);
406 extp->MajorVersion = '1';
407 }
408 }
409
410
411
412
413 if (cfi->mfr == CFI_MFR_SST && (cfi->id >> 4) == 0x0536) {
414 extp->MajorVersion = '1';
415 extp->MinorVersion = '0';
416 }
417}
418
419struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
420{
421 struct cfi_private *cfi = map->fldrv_priv;
422 struct mtd_info *mtd;
423 int i;
424
425 mtd = kzalloc(sizeof(*mtd), GFP_KERNEL);
426 if (!mtd) {
427 printk(KERN_WARNING "Failed to allocate memory for MTD device\n");
428 return NULL;
429 }
430 mtd->priv = map;
431 mtd->type = MTD_NORFLASH;
432
433
434 mtd->erase = cfi_amdstd_erase_varsize;
435 mtd->write = cfi_amdstd_write_words;
436 mtd->read = cfi_amdstd_read;
437 mtd->sync = cfi_amdstd_sync;
438 mtd->suspend = cfi_amdstd_suspend;
439 mtd->resume = cfi_amdstd_resume;
440 mtd->flags = MTD_CAP_NORFLASH;
441 mtd->name = map->name;
442 mtd->writesize = 1;
443 mtd->writebufsize = 1 << cfi->cfiq->MaxBufWriteSize;
444
445 DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): write buffer size %d\n",
446 __func__, mtd->writebufsize);
447
448 mtd->reboot_notifier.notifier_call = cfi_amdstd_reboot;
449
450 if (cfi->cfi_mode==CFI_MODE_CFI){
451 unsigned char bootloc;
452 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR;
453 struct cfi_pri_amdstd *extp;
454
455 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu");
456 if (extp) {
457
458
459
460
461 cfi_fixup_major_minor(cfi, extp);
462
463
464
465
466
467
468
469 if (extp->MajorVersion != '1' ||
470 (extp->MajorVersion == '1' && (extp->MinorVersion < '0' || extp->MinorVersion > '4'))) {
471 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query "
472 "version %c.%c (%#02x/%#02x).\n",
473 extp->MajorVersion, extp->MinorVersion,
474 extp->MajorVersion, extp->MinorVersion);
475 kfree(extp);
476 kfree(mtd);
477 return NULL;
478 }
479
480 printk(KERN_INFO " Amd/Fujitsu Extended Query version %c.%c.\n",
481 extp->MajorVersion, extp->MinorVersion);
482
483
484 cfi->cmdset_priv = extp;
485
486
487 cfi_fixup(mtd, cfi_fixup_table);
488
489#ifdef DEBUG_CFI_FEATURES
490
491 cfi_tell_features(extp);
492#endif
493
494 bootloc = extp->TopBottom;
495 if ((bootloc < 2) || (bootloc > 5)) {
496 printk(KERN_WARNING "%s: CFI contains unrecognised boot "
497 "bank location (%d). Assuming bottom.\n",
498 map->name, bootloc);
499 bootloc = 2;
500 }
501
502 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) {
503 printk(KERN_WARNING "%s: Swapping erase regions for top-boot CFI table.\n", map->name);
504
505 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) {
506 int j = (cfi->cfiq->NumEraseRegions-1)-i;
507 __u32 swap;
508
509 swap = cfi->cfiq->EraseRegionInfo[i];
510 cfi->cfiq->EraseRegionInfo[i] = cfi->cfiq->EraseRegionInfo[j];
511 cfi->cfiq->EraseRegionInfo[j] = swap;
512 }
513 }
514
515 cfi->addr_unlock1 = 0x555;
516 cfi->addr_unlock2 = 0x2aa;
517 }
518 cfi_fixup(mtd, cfi_nopri_fixup_table);
519
520 if (!cfi->addr_unlock1 || !cfi->addr_unlock2) {
521 kfree(mtd);
522 return NULL;
523 }
524
525 }
526 else if (cfi->cfi_mode == CFI_MODE_JEDEC) {
527
528 cfi_fixup(mtd, jedec_fixup_table);
529 }
530
531 cfi_fixup(mtd, fixup_table);
532
533 for (i=0; i< cfi->numchips; i++) {
534 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp;
535 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp;
536 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp;
537 cfi->chips[i].ref_point_counter = 0;
538 init_waitqueue_head(&(cfi->chips[i].wq));
539 }
540
541 map->fldrv = &cfi_amdstd_chipdrv;
542
543 return cfi_amdstd_setup(mtd);
544}
545struct mtd_info *cfi_cmdset_0006(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
546struct mtd_info *cfi_cmdset_0701(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
547EXPORT_SYMBOL_GPL(cfi_cmdset_0002);
548EXPORT_SYMBOL_GPL(cfi_cmdset_0006);
549EXPORT_SYMBOL_GPL(cfi_cmdset_0701);
550
551static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd)
552{
553 struct map_info *map = mtd->priv;
554 struct cfi_private *cfi = map->fldrv_priv;
555 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave;
556 unsigned long offset = 0;
557 int i,j;
558
559 printk(KERN_NOTICE "number of %s chips: %d\n",
560 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips);
561
562 mtd->size = devsize * cfi->numchips;
563
564 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips;
565 mtd->eraseregions = kmalloc(sizeof(struct mtd_erase_region_info)
566 * mtd->numeraseregions, GFP_KERNEL);
567 if (!mtd->eraseregions) {
568 printk(KERN_WARNING "Failed to allocate memory for MTD erase region info\n");
569 goto setup_err;
570 }
571
572 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) {
573 unsigned long ernum, ersize;
574 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave;
575 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1;
576
577 if (mtd->erasesize < ersize) {
578 mtd->erasesize = ersize;
579 }
580 for (j=0; j<cfi->numchips; j++) {
581 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset;
582 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize;
583 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum;
584 }
585 offset += (ersize * ernum);
586 }
587 if (offset != devsize) {
588
589 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize);
590 goto setup_err;
591 }
592
593 __module_get(THIS_MODULE);
594 register_reboot_notifier(&mtd->reboot_notifier);
595 return mtd;
596
597 setup_err:
598 kfree(mtd->eraseregions);
599 kfree(mtd);
600 kfree(cfi->cmdset_priv);
601 kfree(cfi->cfiq);
602 return NULL;
603}
604
605
606
607
608
609
610
611
612
613
614
615
616static int __xipram chip_ready(struct map_info *map, unsigned long addr)
617{
618 map_word d, t;
619
620 d = map_read(map, addr);
621 t = map_read(map, addr);
622
623 return map_word_equal(map, d, t);
624}
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected)
642{
643 map_word oldd, curd;
644
645 oldd = map_read(map, addr);
646 curd = map_read(map, addr);
647
648 return map_word_equal(map, oldd, curd) &&
649 map_word_equal(map, curd, expected);
650}
651
652static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode)
653{
654 DECLARE_WAITQUEUE(wait, current);
655 struct cfi_private *cfi = map->fldrv_priv;
656 unsigned long timeo;
657 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv;
658
659 resettime:
660 timeo = jiffies + HZ;
661 retry:
662 switch (chip->state) {
663
664 case FL_STATUS:
665 for (;;) {
666 if (chip_ready(map, adr))
667 break;
668
669 if (time_after(jiffies, timeo)) {
670 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
671 return -EIO;
672 }
673 mutex_unlock(&chip->mutex);
674 cfi_udelay(1);
675 mutex_lock(&chip->mutex);
676
677 goto retry;
678 }
679
680 case FL_READY:
681 case FL_CFI_QUERY:
682 case FL_JEDEC_QUERY:
683 return 0;
684
685 case FL_ERASING:
686 if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) ||
687 !(mode == FL_READY || mode == FL_POINT ||
688 (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))))
689 goto sleep;
690
691
692
693
694
695
696
697
698 map_write(map, CMD(0xB0), chip->in_progress_block_addr);
699 chip->oldstate = FL_ERASING;
700 chip->state = FL_ERASE_SUSPENDING;
701 chip->erase_suspended = 1;
702 for (;;) {
703 if (chip_ready(map, adr))
704 break;
705
706 if (time_after(jiffies, timeo)) {
707
708
709
710
711
712 map_write(map, cfi->sector_erase_cmd, chip->in_progress_block_addr);
713 chip->state = FL_ERASING;
714 chip->oldstate = FL_READY;
715 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__);
716 return -EIO;
717 }
718
719 mutex_unlock(&chip->mutex);
720 cfi_udelay(1);
721 mutex_lock(&chip->mutex);
722
723
724 }
725 chip->state = FL_READY;
726 return 0;
727
728 case FL_XIP_WHILE_ERASING:
729 if (mode != FL_READY && mode != FL_POINT &&
730 (!cfip || !(cfip->EraseSuspend&2)))
731 goto sleep;
732 chip->oldstate = chip->state;
733 chip->state = FL_READY;
734 return 0;
735
736 case FL_SHUTDOWN:
737
738 return -EIO;
739
740 case FL_POINT:
741
742 if (mode == FL_READY && chip->oldstate == FL_READY)
743 return 0;
744
745 default:
746 sleep:
747 set_current_state(TASK_UNINTERRUPTIBLE);
748 add_wait_queue(&chip->wq, &wait);
749 mutex_unlock(&chip->mutex);
750 schedule();
751 remove_wait_queue(&chip->wq, &wait);
752 mutex_lock(&chip->mutex);
753 goto resettime;
754 }
755}
756
757
758static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr)
759{
760 struct cfi_private *cfi = map->fldrv_priv;
761
762 switch(chip->oldstate) {
763 case FL_ERASING:
764 chip->state = chip->oldstate;
765 map_write(map, cfi->sector_erase_cmd, chip->in_progress_block_addr);
766 chip->oldstate = FL_READY;
767 chip->state = FL_ERASING;
768 break;
769
770 case FL_XIP_WHILE_ERASING:
771 chip->state = chip->oldstate;
772 chip->oldstate = FL_READY;
773 break;
774
775 case FL_READY:
776 case FL_STATUS:
777
778 DISABLE_VPP(map);
779 break;
780 default:
781 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
782 }
783 wake_up(&chip->wq);
784}
785
786#ifdef CONFIG_MTD_XIP
787
788
789
790
791
792
793
794
795
796
797
798
799static void xip_disable(struct map_info *map, struct flchip *chip,
800 unsigned long adr)
801{
802
803 (void) map_read(map, adr);
804 local_irq_disable();
805}
806
807static void __xipram xip_enable(struct map_info *map, struct flchip *chip,
808 unsigned long adr)
809{
810 struct cfi_private *cfi = map->fldrv_priv;
811
812 if (chip->state != FL_POINT && chip->state != FL_READY) {
813 map_write(map, CMD(0xf0), adr);
814 chip->state = FL_READY;
815 }
816 (void) map_read(map, adr);
817 xip_iprefetch();
818 local_irq_enable();
819}
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834static void __xipram xip_udelay(struct map_info *map, struct flchip *chip,
835 unsigned long adr, int usec)
836{
837 struct cfi_private *cfi = map->fldrv_priv;
838 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
839 map_word status, OK = CMD(0x80);
840 unsigned long suspended, start = xip_currtime();
841 flstate_t oldstate;
842
843 do {
844 cpu_relax();
845 if (xip_irqpending() && extp &&
846 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) &&
847 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
848
849
850
851
852
853
854
855
856
857
858 map_write(map, CMD(0xb0), adr);
859 usec -= xip_elapsed_since(start);
860 suspended = xip_currtime();
861 do {
862 if (xip_elapsed_since(suspended) > 100000) {
863
864
865
866
867
868
869 return;
870 }
871 status = map_read(map, adr);
872 } while (!map_word_andequal(map, status, OK, OK));
873
874
875 oldstate = chip->state;
876 if (!map_word_bitsset(map, status, CMD(0x40)))
877 break;
878 chip->state = FL_XIP_WHILE_ERASING;
879 chip->erase_suspended = 1;
880 map_write(map, CMD(0xf0), adr);
881 (void) map_read(map, adr);
882 xip_iprefetch();
883 local_irq_enable();
884 mutex_unlock(&chip->mutex);
885 xip_iprefetch();
886 cond_resched();
887
888
889
890
891
892
893
894 mutex_lock(&chip->mutex);
895 while (chip->state != FL_XIP_WHILE_ERASING) {
896 DECLARE_WAITQUEUE(wait, current);
897 set_current_state(TASK_UNINTERRUPTIBLE);
898 add_wait_queue(&chip->wq, &wait);
899 mutex_unlock(&chip->mutex);
900 schedule();
901 remove_wait_queue(&chip->wq, &wait);
902 mutex_lock(&chip->mutex);
903 }
904
905 local_irq_disable();
906
907
908 map_write(map, cfi->sector_erase_cmd, adr);
909 chip->state = oldstate;
910 start = xip_currtime();
911 } else if (usec >= 1000000/HZ) {
912
913
914
915
916
917 xip_cpu_idle();
918 }
919 status = map_read(map, adr);
920 } while (!map_word_andequal(map, status, OK, OK)
921 && xip_elapsed_since(start) < usec);
922}
923
924#define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
925
926
927
928
929
930
931
932
933#define XIP_INVAL_CACHED_RANGE(map, from, size) \
934 INVALIDATE_CACHED_RANGE(map, from, size)
935
936#define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
937 UDELAY(map, chip, adr, usec)
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956#else
957
958#define xip_disable(map, chip, adr)
959#define xip_enable(map, chip, adr)
960#define XIP_INVAL_CACHED_RANGE(x...)
961
962#define UDELAY(map, chip, adr, usec) \
963do { \
964 mutex_unlock(&chip->mutex); \
965 cfi_udelay(usec); \
966 mutex_lock(&chip->mutex); \
967} while (0)
968
969#define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
970do { \
971 mutex_unlock(&chip->mutex); \
972 INVALIDATE_CACHED_RANGE(map, adr, len); \
973 cfi_udelay(usec); \
974 mutex_lock(&chip->mutex); \
975} while (0)
976
977#endif
978
979static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
980{
981 unsigned long cmd_addr;
982 struct cfi_private *cfi = map->fldrv_priv;
983 int ret;
984
985 adr += chip->start;
986
987
988 cmd_addr = adr & ~(map_bankwidth(map)-1);
989
990 mutex_lock(&chip->mutex);
991 ret = get_chip(map, chip, cmd_addr, FL_READY);
992 if (ret) {
993 mutex_unlock(&chip->mutex);
994 return ret;
995 }
996
997 if (chip->state != FL_POINT && chip->state != FL_READY) {
998 map_write(map, CMD(0xf0), cmd_addr);
999 chip->state = FL_READY;
1000 }
1001
1002 map_copy_from(map, buf, adr, len);
1003
1004 put_chip(map, chip, cmd_addr);
1005
1006 mutex_unlock(&chip->mutex);
1007 return 0;
1008}
1009
1010
1011static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1012{
1013 struct map_info *map = mtd->priv;
1014 struct cfi_private *cfi = map->fldrv_priv;
1015 unsigned long ofs;
1016 int chipnum;
1017 int ret = 0;
1018
1019
1020
1021 chipnum = (from >> cfi->chipshift);
1022 ofs = from - (chipnum << cfi->chipshift);
1023
1024
1025 *retlen = 0;
1026
1027 while (len) {
1028 unsigned long thislen;
1029
1030 if (chipnum >= cfi->numchips)
1031 break;
1032
1033 if ((len + ofs -1) >> cfi->chipshift)
1034 thislen = (1<<cfi->chipshift) - ofs;
1035 else
1036 thislen = len;
1037
1038 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
1039 if (ret)
1040 break;
1041
1042 *retlen += thislen;
1043 len -= thislen;
1044 buf += thislen;
1045
1046 ofs = 0;
1047 chipnum++;
1048 }
1049 return ret;
1050}
1051
1052
1053static inline int do_read_secsi_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
1054{
1055 DECLARE_WAITQUEUE(wait, current);
1056 unsigned long timeo = jiffies + HZ;
1057 struct cfi_private *cfi = map->fldrv_priv;
1058
1059 retry:
1060 mutex_lock(&chip->mutex);
1061
1062 if (chip->state != FL_READY){
1063 set_current_state(TASK_UNINTERRUPTIBLE);
1064 add_wait_queue(&chip->wq, &wait);
1065
1066 mutex_unlock(&chip->mutex);
1067
1068 schedule();
1069 remove_wait_queue(&chip->wq, &wait);
1070 timeo = jiffies + HZ;
1071
1072 goto retry;
1073 }
1074
1075 adr += chip->start;
1076
1077 chip->state = FL_READY;
1078
1079 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1080 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1081 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1082
1083 map_copy_from(map, buf, adr, len);
1084
1085 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1086 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1087 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1088 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1089
1090 wake_up(&chip->wq);
1091 mutex_unlock(&chip->mutex);
1092
1093 return 0;
1094}
1095
1096static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1097{
1098 struct map_info *map = mtd->priv;
1099 struct cfi_private *cfi = map->fldrv_priv;
1100 unsigned long ofs;
1101 int chipnum;
1102 int ret = 0;
1103
1104
1105
1106
1107
1108 chipnum=from>>3;
1109 ofs=from & 7;
1110
1111
1112 *retlen = 0;
1113
1114 while (len) {
1115 unsigned long thislen;
1116
1117 if (chipnum >= cfi->numchips)
1118 break;
1119
1120 if ((len + ofs -1) >> 3)
1121 thislen = (1<<3) - ofs;
1122 else
1123 thislen = len;
1124
1125 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
1126 if (ret)
1127 break;
1128
1129 *retlen += thislen;
1130 len -= thislen;
1131 buf += thislen;
1132
1133 ofs = 0;
1134 chipnum++;
1135 }
1136 return ret;
1137}
1138
1139
1140static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip, unsigned long adr, map_word datum)
1141{
1142 struct cfi_private *cfi = map->fldrv_priv;
1143 unsigned long timeo = jiffies + HZ;
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
1154 int ret = 0;
1155 map_word oldd;
1156 int retry_cnt = 0;
1157
1158 adr += chip->start;
1159
1160 mutex_lock(&chip->mutex);
1161 ret = get_chip(map, chip, adr, FL_WRITING);
1162 if (ret) {
1163 mutex_unlock(&chip->mutex);
1164 return ret;
1165 }
1166
1167 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1168 __func__, adr, datum.x[0] );
1169
1170
1171
1172
1173
1174
1175
1176 oldd = map_read(map, adr);
1177 if (map_word_equal(map, oldd, datum)) {
1178 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): NOP\n",
1179 __func__);
1180 goto op_done;
1181 }
1182
1183 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map));
1184 ENABLE_VPP(map);
1185 xip_disable(map, chip, adr);
1186 retry:
1187 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1188 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1189 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1190 map_write(map, datum, adr);
1191 chip->state = FL_WRITING;
1192
1193 INVALIDATE_CACHE_UDELAY(map, chip,
1194 adr, map_bankwidth(map),
1195 chip->word_write_time);
1196
1197
1198 timeo = jiffies + uWriteTimeout;
1199 for (;;) {
1200 if (chip->state != FL_WRITING) {
1201
1202 DECLARE_WAITQUEUE(wait, current);
1203
1204 set_current_state(TASK_UNINTERRUPTIBLE);
1205 add_wait_queue(&chip->wq, &wait);
1206 mutex_unlock(&chip->mutex);
1207 schedule();
1208 remove_wait_queue(&chip->wq, &wait);
1209 timeo = jiffies + (HZ / 2);
1210 mutex_lock(&chip->mutex);
1211 continue;
1212 }
1213
1214 if (time_after(jiffies, timeo) && !chip_ready(map, adr)){
1215 xip_enable(map, chip, adr);
1216 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__);
1217 xip_disable(map, chip, adr);
1218 break;
1219 }
1220
1221 if (chip_ready(map, adr))
1222 break;
1223
1224
1225 UDELAY(map, chip, adr, 1);
1226 }
1227
1228 if (!chip_good(map, adr, datum)) {
1229
1230 map_write( map, CMD(0xF0), chip->start );
1231
1232
1233 if (++retry_cnt <= MAX_WORD_RETRIES)
1234 goto retry;
1235
1236 ret = -EIO;
1237 }
1238 xip_enable(map, chip, adr);
1239 op_done:
1240 chip->state = FL_READY;
1241 put_chip(map, chip, adr);
1242 mutex_unlock(&chip->mutex);
1243
1244 return ret;
1245}
1246
1247
1248static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
1249 size_t *retlen, const u_char *buf)
1250{
1251 struct map_info *map = mtd->priv;
1252 struct cfi_private *cfi = map->fldrv_priv;
1253 int ret = 0;
1254 int chipnum;
1255 unsigned long ofs, chipstart;
1256 DECLARE_WAITQUEUE(wait, current);
1257
1258 *retlen = 0;
1259 if (!len)
1260 return 0;
1261
1262 chipnum = to >> cfi->chipshift;
1263 ofs = to - (chipnum << cfi->chipshift);
1264 chipstart = cfi->chips[chipnum].start;
1265
1266
1267 if (ofs & (map_bankwidth(map)-1)) {
1268 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1);
1269 int i = ofs - bus_ofs;
1270 int n = 0;
1271 map_word tmp_buf;
1272
1273 retry:
1274 mutex_lock(&cfi->chips[chipnum].mutex);
1275
1276 if (cfi->chips[chipnum].state != FL_READY) {
1277 set_current_state(TASK_UNINTERRUPTIBLE);
1278 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1279
1280 mutex_unlock(&cfi->chips[chipnum].mutex);
1281
1282 schedule();
1283 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1284 goto retry;
1285 }
1286
1287
1288 tmp_buf = map_read(map, bus_ofs+chipstart);
1289
1290 mutex_unlock(&cfi->chips[chipnum].mutex);
1291
1292
1293 n = min_t(int, len, map_bankwidth(map)-i);
1294
1295 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
1296
1297 ret = do_write_oneword(map, &cfi->chips[chipnum],
1298 bus_ofs, tmp_buf);
1299 if (ret)
1300 return ret;
1301
1302 ofs += n;
1303 buf += n;
1304 (*retlen) += n;
1305 len -= n;
1306
1307 if (ofs >> cfi->chipshift) {
1308 chipnum ++;
1309 ofs = 0;
1310 if (chipnum == cfi->numchips)
1311 return 0;
1312 }
1313 }
1314
1315
1316 while(len >= map_bankwidth(map)) {
1317 map_word datum;
1318
1319 datum = map_word_load(map, buf);
1320
1321 ret = do_write_oneword(map, &cfi->chips[chipnum],
1322 ofs, datum);
1323 if (ret)
1324 return ret;
1325
1326 ofs += map_bankwidth(map);
1327 buf += map_bankwidth(map);
1328 (*retlen) += map_bankwidth(map);
1329 len -= map_bankwidth(map);
1330
1331 if (ofs >> cfi->chipshift) {
1332 chipnum ++;
1333 ofs = 0;
1334 if (chipnum == cfi->numchips)
1335 return 0;
1336 chipstart = cfi->chips[chipnum].start;
1337 }
1338 }
1339
1340
1341 if (len & (map_bankwidth(map)-1)) {
1342 map_word tmp_buf;
1343
1344 retry1:
1345 mutex_lock(&cfi->chips[chipnum].mutex);
1346
1347 if (cfi->chips[chipnum].state != FL_READY) {
1348 set_current_state(TASK_UNINTERRUPTIBLE);
1349 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1350
1351 mutex_unlock(&cfi->chips[chipnum].mutex);
1352
1353 schedule();
1354 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1355 goto retry1;
1356 }
1357
1358 tmp_buf = map_read(map, ofs + chipstart);
1359
1360 mutex_unlock(&cfi->chips[chipnum].mutex);
1361
1362 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
1363
1364 ret = do_write_oneword(map, &cfi->chips[chipnum],
1365 ofs, tmp_buf);
1366 if (ret)
1367 return ret;
1368
1369 (*retlen) += len;
1370 }
1371
1372 return 0;
1373}
1374
1375
1376
1377
1378
1379static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
1380 unsigned long adr, const u_char *buf,
1381 int len)
1382{
1383 struct cfi_private *cfi = map->fldrv_priv;
1384 unsigned long timeo = jiffies + HZ;
1385
1386 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
1387 int ret = -EIO;
1388 unsigned long cmd_adr;
1389 int z, words;
1390 map_word datum;
1391
1392 adr += chip->start;
1393 cmd_adr = adr;
1394
1395 mutex_lock(&chip->mutex);
1396 ret = get_chip(map, chip, adr, FL_WRITING);
1397 if (ret) {
1398 mutex_unlock(&chip->mutex);
1399 return ret;
1400 }
1401
1402 datum = map_word_load(map, buf);
1403
1404 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1405 __func__, adr, datum.x[0] );
1406
1407 XIP_INVAL_CACHED_RANGE(map, adr, len);
1408 ENABLE_VPP(map);
1409 xip_disable(map, chip, cmd_adr);
1410
1411 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1412 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1413
1414
1415 map_write(map, CMD(0x25), cmd_adr);
1416
1417 chip->state = FL_WRITING_TO_BUFFER;
1418
1419
1420 words = len / map_bankwidth(map);
1421 map_write(map, CMD(words - 1), cmd_adr);
1422
1423 z = 0;
1424 while(z < words * map_bankwidth(map)) {
1425 datum = map_word_load(map, buf);
1426 map_write(map, datum, adr + z);
1427
1428 z += map_bankwidth(map);
1429 buf += map_bankwidth(map);
1430 }
1431 z -= map_bankwidth(map);
1432
1433 adr += z;
1434
1435
1436 map_write(map, CMD(0x29), cmd_adr);
1437 chip->state = FL_WRITING;
1438
1439 INVALIDATE_CACHE_UDELAY(map, chip,
1440 adr, map_bankwidth(map),
1441 chip->word_write_time);
1442
1443 timeo = jiffies + uWriteTimeout;
1444
1445 for (;;) {
1446 if (chip->state != FL_WRITING) {
1447
1448 DECLARE_WAITQUEUE(wait, current);
1449
1450 set_current_state(TASK_UNINTERRUPTIBLE);
1451 add_wait_queue(&chip->wq, &wait);
1452 mutex_unlock(&chip->mutex);
1453 schedule();
1454 remove_wait_queue(&chip->wq, &wait);
1455 timeo = jiffies + (HZ / 2);
1456 mutex_lock(&chip->mutex);
1457 continue;
1458 }
1459
1460 if (time_after(jiffies, timeo) && !chip_ready(map, adr))
1461 break;
1462
1463 if (chip_ready(map, adr)) {
1464 xip_enable(map, chip, adr);
1465 goto op_done;
1466 }
1467
1468
1469 UDELAY(map, chip, adr, 1);
1470 }
1471
1472
1473 map_write( map, CMD(0xF0), chip->start );
1474 xip_enable(map, chip, adr);
1475
1476
1477 printk(KERN_WARNING "MTD %s(): software timeout\n",
1478 __func__ );
1479
1480 ret = -EIO;
1481 op_done:
1482 chip->state = FL_READY;
1483 put_chip(map, chip, adr);
1484 mutex_unlock(&chip->mutex);
1485
1486 return ret;
1487}
1488
1489
1490static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
1491 size_t *retlen, const u_char *buf)
1492{
1493 struct map_info *map = mtd->priv;
1494 struct cfi_private *cfi = map->fldrv_priv;
1495 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
1496 int ret = 0;
1497 int chipnum;
1498 unsigned long ofs;
1499
1500 *retlen = 0;
1501 if (!len)
1502 return 0;
1503
1504 chipnum = to >> cfi->chipshift;
1505 ofs = to - (chipnum << cfi->chipshift);
1506
1507
1508 if (ofs & (map_bankwidth(map)-1)) {
1509 size_t local_len = (-ofs)&(map_bankwidth(map)-1);
1510 if (local_len > len)
1511 local_len = len;
1512 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1513 local_len, retlen, buf);
1514 if (ret)
1515 return ret;
1516 ofs += local_len;
1517 buf += local_len;
1518 len -= local_len;
1519
1520 if (ofs >> cfi->chipshift) {
1521 chipnum ++;
1522 ofs = 0;
1523 if (chipnum == cfi->numchips)
1524 return 0;
1525 }
1526 }
1527
1528
1529 while (len >= map_bankwidth(map) * 2) {
1530
1531 int size = wbufsize - (ofs & (wbufsize-1));
1532
1533 if (size > len)
1534 size = len;
1535 if (size % map_bankwidth(map))
1536 size -= size % map_bankwidth(map);
1537
1538 ret = do_write_buffer(map, &cfi->chips[chipnum],
1539 ofs, buf, size);
1540 if (ret)
1541 return ret;
1542
1543 ofs += size;
1544 buf += size;
1545 (*retlen) += size;
1546 len -= size;
1547
1548 if (ofs >> cfi->chipshift) {
1549 chipnum ++;
1550 ofs = 0;
1551 if (chipnum == cfi->numchips)
1552 return 0;
1553 }
1554 }
1555
1556 if (len) {
1557 size_t retlen_dregs = 0;
1558
1559 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1560 len, &retlen_dregs, buf);
1561
1562 *retlen += retlen_dregs;
1563 return ret;
1564 }
1565
1566 return 0;
1567}
1568
1569
1570
1571
1572
1573
1574static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
1575{
1576 struct cfi_private *cfi = map->fldrv_priv;
1577 unsigned long timeo = jiffies + HZ;
1578 unsigned long int adr;
1579 DECLARE_WAITQUEUE(wait, current);
1580 int ret = 0;
1581
1582 adr = cfi->addr_unlock1;
1583
1584 mutex_lock(&chip->mutex);
1585 ret = get_chip(map, chip, adr, FL_WRITING);
1586 if (ret) {
1587 mutex_unlock(&chip->mutex);
1588 return ret;
1589 }
1590
1591 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n",
1592 __func__, chip->start );
1593
1594 XIP_INVAL_CACHED_RANGE(map, adr, map->size);
1595 ENABLE_VPP(map);
1596 xip_disable(map, chip, adr);
1597
1598 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1599 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1600 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1601 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1602 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1603 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1604
1605 chip->state = FL_ERASING;
1606 chip->erase_suspended = 0;
1607 chip->in_progress_block_addr = adr;
1608
1609 INVALIDATE_CACHE_UDELAY(map, chip,
1610 adr, map->size,
1611 chip->erase_time*500);
1612
1613 timeo = jiffies + (HZ*20);
1614
1615 for (;;) {
1616 if (chip->state != FL_ERASING) {
1617
1618 set_current_state(TASK_UNINTERRUPTIBLE);
1619 add_wait_queue(&chip->wq, &wait);
1620 mutex_unlock(&chip->mutex);
1621 schedule();
1622 remove_wait_queue(&chip->wq, &wait);
1623 mutex_lock(&chip->mutex);
1624 continue;
1625 }
1626 if (chip->erase_suspended) {
1627
1628
1629 timeo = jiffies + (HZ*20);
1630 chip->erase_suspended = 0;
1631 }
1632
1633 if (chip_ready(map, adr))
1634 break;
1635
1636 if (time_after(jiffies, timeo)) {
1637 printk(KERN_WARNING "MTD %s(): software timeout\n",
1638 __func__ );
1639 break;
1640 }
1641
1642
1643 UDELAY(map, chip, adr, 1000000/HZ);
1644 }
1645
1646 if (!chip_good(map, adr, map_word_ff(map))) {
1647
1648 map_write( map, CMD(0xF0), chip->start );
1649
1650
1651 ret = -EIO;
1652 }
1653
1654 chip->state = FL_READY;
1655 xip_enable(map, chip, adr);
1656 put_chip(map, chip, adr);
1657 mutex_unlock(&chip->mutex);
1658
1659 return ret;
1660}
1661
1662
1663static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk)
1664{
1665 struct cfi_private *cfi = map->fldrv_priv;
1666 unsigned long timeo = jiffies + HZ;
1667 DECLARE_WAITQUEUE(wait, current);
1668 int ret = 0;
1669
1670 adr += chip->start;
1671
1672 mutex_lock(&chip->mutex);
1673 ret = get_chip(map, chip, adr, FL_ERASING);
1674 if (ret) {
1675 mutex_unlock(&chip->mutex);
1676 return ret;
1677 }
1678
1679 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n",
1680 __func__, adr );
1681
1682 XIP_INVAL_CACHED_RANGE(map, adr, len);
1683 ENABLE_VPP(map);
1684 xip_disable(map, chip, adr);
1685
1686 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1687 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1688 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1689 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1690 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1691 map_write(map, cfi->sector_erase_cmd, adr);
1692
1693 chip->state = FL_ERASING;
1694 chip->erase_suspended = 0;
1695 chip->in_progress_block_addr = adr;
1696
1697 INVALIDATE_CACHE_UDELAY(map, chip,
1698 adr, len,
1699 chip->erase_time*500);
1700
1701 timeo = jiffies + (HZ*20);
1702
1703 for (;;) {
1704 if (chip->state != FL_ERASING) {
1705
1706 set_current_state(TASK_UNINTERRUPTIBLE);
1707 add_wait_queue(&chip->wq, &wait);
1708 mutex_unlock(&chip->mutex);
1709 schedule();
1710 remove_wait_queue(&chip->wq, &wait);
1711 mutex_lock(&chip->mutex);
1712 continue;
1713 }
1714 if (chip->erase_suspended) {
1715
1716
1717 timeo = jiffies + (HZ*20);
1718 chip->erase_suspended = 0;
1719 }
1720
1721 if (chip_ready(map, adr)) {
1722 xip_enable(map, chip, adr);
1723 break;
1724 }
1725
1726 if (time_after(jiffies, timeo)) {
1727 xip_enable(map, chip, adr);
1728 printk(KERN_WARNING "MTD %s(): software timeout\n",
1729 __func__ );
1730 break;
1731 }
1732
1733
1734 UDELAY(map, chip, adr, 1000000/HZ);
1735 }
1736
1737 if (!chip_good(map, adr, map_word_ff(map))) {
1738
1739 map_write( map, CMD(0xF0), chip->start );
1740
1741
1742 ret = -EIO;
1743 }
1744
1745 chip->state = FL_READY;
1746 put_chip(map, chip, adr);
1747 mutex_unlock(&chip->mutex);
1748 return ret;
1749}
1750
1751
1752static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr)
1753{
1754 unsigned long ofs, len;
1755 int ret;
1756
1757 ofs = instr->addr;
1758 len = instr->len;
1759
1760 ret = cfi_varsize_frob(mtd, do_erase_oneblock, ofs, len, NULL);
1761 if (ret)
1762 return ret;
1763
1764 instr->state = MTD_ERASE_DONE;
1765 mtd_erase_callback(instr);
1766
1767 return 0;
1768}
1769
1770
1771static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr)
1772{
1773 struct map_info *map = mtd->priv;
1774 struct cfi_private *cfi = map->fldrv_priv;
1775 int ret = 0;
1776
1777 if (instr->addr != 0)
1778 return -EINVAL;
1779
1780 if (instr->len != mtd->size)
1781 return -EINVAL;
1782
1783 ret = do_erase_chip(map, &cfi->chips[0]);
1784 if (ret)
1785 return ret;
1786
1787 instr->state = MTD_ERASE_DONE;
1788 mtd_erase_callback(instr);
1789
1790 return 0;
1791}
1792
1793static int do_atmel_lock(struct map_info *map, struct flchip *chip,
1794 unsigned long adr, int len, void *thunk)
1795{
1796 struct cfi_private *cfi = map->fldrv_priv;
1797 int ret;
1798
1799 mutex_lock(&chip->mutex);
1800 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
1801 if (ret)
1802 goto out_unlock;
1803 chip->state = FL_LOCKING;
1804
1805 DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): LOCK 0x%08lx len %d\n",
1806 __func__, adr, len);
1807
1808 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1809 cfi->device_type, NULL);
1810 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1811 cfi->device_type, NULL);
1812 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi,
1813 cfi->device_type, NULL);
1814 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1815 cfi->device_type, NULL);
1816 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1817 cfi->device_type, NULL);
1818 map_write(map, CMD(0x40), chip->start + adr);
1819
1820 chip->state = FL_READY;
1821 put_chip(map, chip, adr + chip->start);
1822 ret = 0;
1823
1824out_unlock:
1825 mutex_unlock(&chip->mutex);
1826 return ret;
1827}
1828
1829static int do_atmel_unlock(struct map_info *map, struct flchip *chip,
1830 unsigned long adr, int len, void *thunk)
1831{
1832 struct cfi_private *cfi = map->fldrv_priv;
1833 int ret;
1834
1835 mutex_lock(&chip->mutex);
1836 ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
1837 if (ret)
1838 goto out_unlock;
1839 chip->state = FL_UNLOCKING;
1840
1841 DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): LOCK 0x%08lx len %d\n",
1842 __func__, adr, len);
1843
1844 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1845 cfi->device_type, NULL);
1846 map_write(map, CMD(0x70), adr);
1847
1848 chip->state = FL_READY;
1849 put_chip(map, chip, adr + chip->start);
1850 ret = 0;
1851
1852out_unlock:
1853 mutex_unlock(&chip->mutex);
1854 return ret;
1855}
1856
1857static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1858{
1859 return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL);
1860}
1861
1862static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1863{
1864 return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL);
1865}
1866
1867
1868static void cfi_amdstd_sync (struct mtd_info *mtd)
1869{
1870 struct map_info *map = mtd->priv;
1871 struct cfi_private *cfi = map->fldrv_priv;
1872 int i;
1873 struct flchip *chip;
1874 int ret = 0;
1875 DECLARE_WAITQUEUE(wait, current);
1876
1877 for (i=0; !ret && i<cfi->numchips; i++) {
1878 chip = &cfi->chips[i];
1879
1880 retry:
1881 mutex_lock(&chip->mutex);
1882
1883 switch(chip->state) {
1884 case FL_READY:
1885 case FL_STATUS:
1886 case FL_CFI_QUERY:
1887 case FL_JEDEC_QUERY:
1888 chip->oldstate = chip->state;
1889 chip->state = FL_SYNCING;
1890
1891
1892
1893
1894 case FL_SYNCING:
1895 mutex_unlock(&chip->mutex);
1896 break;
1897
1898 default:
1899
1900 set_current_state(TASK_UNINTERRUPTIBLE);
1901 add_wait_queue(&chip->wq, &wait);
1902
1903 mutex_unlock(&chip->mutex);
1904
1905 schedule();
1906
1907 remove_wait_queue(&chip->wq, &wait);
1908
1909 goto retry;
1910 }
1911 }
1912
1913
1914
1915 for (i--; i >=0; i--) {
1916 chip = &cfi->chips[i];
1917
1918 mutex_lock(&chip->mutex);
1919
1920 if (chip->state == FL_SYNCING) {
1921 chip->state = chip->oldstate;
1922 wake_up(&chip->wq);
1923 }
1924 mutex_unlock(&chip->mutex);
1925 }
1926}
1927
1928
1929static int cfi_amdstd_suspend(struct mtd_info *mtd)
1930{
1931 struct map_info *map = mtd->priv;
1932 struct cfi_private *cfi = map->fldrv_priv;
1933 int i;
1934 struct flchip *chip;
1935 int ret = 0;
1936
1937 for (i=0; !ret && i<cfi->numchips; i++) {
1938 chip = &cfi->chips[i];
1939
1940 mutex_lock(&chip->mutex);
1941
1942 switch(chip->state) {
1943 case FL_READY:
1944 case FL_STATUS:
1945 case FL_CFI_QUERY:
1946 case FL_JEDEC_QUERY:
1947 chip->oldstate = chip->state;
1948 chip->state = FL_PM_SUSPENDED;
1949
1950
1951
1952
1953 case FL_PM_SUSPENDED:
1954 break;
1955
1956 default:
1957 ret = -EAGAIN;
1958 break;
1959 }
1960 mutex_unlock(&chip->mutex);
1961 }
1962
1963
1964
1965 if (ret) {
1966 for (i--; i >=0; i--) {
1967 chip = &cfi->chips[i];
1968
1969 mutex_lock(&chip->mutex);
1970
1971 if (chip->state == FL_PM_SUSPENDED) {
1972 chip->state = chip->oldstate;
1973 wake_up(&chip->wq);
1974 }
1975 mutex_unlock(&chip->mutex);
1976 }
1977 }
1978
1979 return ret;
1980}
1981
1982
1983static void cfi_amdstd_resume(struct mtd_info *mtd)
1984{
1985 struct map_info *map = mtd->priv;
1986 struct cfi_private *cfi = map->fldrv_priv;
1987 int i;
1988 struct flchip *chip;
1989
1990 for (i=0; i<cfi->numchips; i++) {
1991
1992 chip = &cfi->chips[i];
1993
1994 mutex_lock(&chip->mutex);
1995
1996 if (chip->state == FL_PM_SUSPENDED) {
1997 chip->state = FL_READY;
1998 map_write(map, CMD(0xF0), chip->start);
1999 wake_up(&chip->wq);
2000 }
2001 else
2002 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n");
2003
2004 mutex_unlock(&chip->mutex);
2005 }
2006}
2007
2008
2009
2010
2011
2012
2013
2014
2015static int cfi_amdstd_reset(struct mtd_info *mtd)
2016{
2017 struct map_info *map = mtd->priv;
2018 struct cfi_private *cfi = map->fldrv_priv;
2019 int i, ret;
2020 struct flchip *chip;
2021
2022 for (i = 0; i < cfi->numchips; i++) {
2023
2024 chip = &cfi->chips[i];
2025
2026 mutex_lock(&chip->mutex);
2027
2028 ret = get_chip(map, chip, chip->start, FL_SHUTDOWN);
2029 if (!ret) {
2030 map_write(map, CMD(0xF0), chip->start);
2031 chip->state = FL_SHUTDOWN;
2032 put_chip(map, chip, chip->start);
2033 }
2034
2035 mutex_unlock(&chip->mutex);
2036 }
2037
2038 return 0;
2039}
2040
2041
2042static int cfi_amdstd_reboot(struct notifier_block *nb, unsigned long val,
2043 void *v)
2044{
2045 struct mtd_info *mtd;
2046
2047 mtd = container_of(nb, struct mtd_info, reboot_notifier);
2048 cfi_amdstd_reset(mtd);
2049 return NOTIFY_DONE;
2050}
2051
2052
2053static void cfi_amdstd_destroy(struct mtd_info *mtd)
2054{
2055 struct map_info *map = mtd->priv;
2056 struct cfi_private *cfi = map->fldrv_priv;
2057
2058 cfi_amdstd_reset(mtd);
2059 unregister_reboot_notifier(&mtd->reboot_notifier);
2060 kfree(cfi->cmdset_priv);
2061 kfree(cfi->cfiq);
2062 kfree(cfi);
2063 kfree(mtd->eraseregions);
2064}
2065
2066MODULE_LICENSE("GPL");
2067MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
2068MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");
2069MODULE_ALIAS("cfi_cmdset_0006");
2070MODULE_ALIAS("cfi_cmdset_0701");
2071