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53#include <linux/module.h>
54#include <linux/moduleparam.h>
55#include <linux/types.h>
56#include <linux/errno.h>
57#include <linux/ioport.h>
58#include <linux/pci.h>
59#include <linux/dma-mapping.h>
60#include <linux/kernel.h>
61#include <linux/netdevice.h>
62#include <linux/etherdevice.h>
63#include <linux/skbuff.h>
64#include <linux/init.h>
65#include <linux/delay.h>
66#include <linux/mm.h>
67#include <linux/highmem.h>
68#include <linux/sockios.h>
69#include <linux/firmware.h>
70#include <linux/slab.h>
71
72#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
73#include <linux/if_vlan.h>
74#endif
75
76#ifdef SIOCETHTOOL
77#include <linux/ethtool.h>
78#endif
79
80#include <net/sock.h>
81#include <net/ip.h>
82
83#include <asm/system.h>
84#include <asm/io.h>
85#include <asm/irq.h>
86#include <asm/byteorder.h>
87#include <asm/uaccess.h>
88
89
90#define DRV_NAME "acenic"
91
92#undef INDEX_DEBUG
93
94#ifdef CONFIG_ACENIC_OMIT_TIGON_I
95#define ACE_IS_TIGON_I(ap) 0
96#define ACE_TX_RING_ENTRIES(ap) MAX_TX_RING_ENTRIES
97#else
98#define ACE_IS_TIGON_I(ap) (ap->version == 1)
99#define ACE_TX_RING_ENTRIES(ap) ap->tx_ring_entries
100#endif
101
102#ifndef PCI_VENDOR_ID_ALTEON
103#define PCI_VENDOR_ID_ALTEON 0x12ae
104#endif
105#ifndef PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE
106#define PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 0x0001
107#define PCI_DEVICE_ID_ALTEON_ACENIC_COPPER 0x0002
108#endif
109#ifndef PCI_DEVICE_ID_3COM_3C985
110#define PCI_DEVICE_ID_3COM_3C985 0x0001
111#endif
112#ifndef PCI_VENDOR_ID_NETGEAR
113#define PCI_VENDOR_ID_NETGEAR 0x1385
114#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a
115#endif
116#ifndef PCI_DEVICE_ID_NETGEAR_GA620T
117#define PCI_DEVICE_ID_NETGEAR_GA620T 0x630a
118#endif
119
120
121
122
123
124
125#ifndef PCI_DEVICE_ID_FARALLON_PN9000SX
126#define PCI_DEVICE_ID_FARALLON_PN9000SX 0x1a
127#endif
128#ifndef PCI_DEVICE_ID_FARALLON_PN9100T
129#define PCI_DEVICE_ID_FARALLON_PN9100T 0xfa
130#endif
131#ifndef PCI_VENDOR_ID_SGI
132#define PCI_VENDOR_ID_SGI 0x10a9
133#endif
134#ifndef PCI_DEVICE_ID_SGI_ACENIC
135#define PCI_DEVICE_ID_SGI_ACENIC 0x0009
136#endif
137
138static DEFINE_PCI_DEVICE_TABLE(acenic_pci_tbl) = {
139 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE,
140 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
141 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_COPPER,
142 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
143 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C985,
144 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
145 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620,
146 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
147 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620T,
148 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
149
150
151
152
153 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_FARALLON_PN9000SX,
154 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
155 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_FARALLON_PN9100T,
156 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
157 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_ACENIC,
158 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
159 { }
160};
161MODULE_DEVICE_TABLE(pci, acenic_pci_tbl);
162
163#define ace_sync_irq(irq) synchronize_irq(irq)
164
165#ifndef offset_in_page
166#define offset_in_page(ptr) ((unsigned long)(ptr) & ~PAGE_MASK)
167#endif
168
169#define ACE_MAX_MOD_PARMS 8
170#define BOARD_IDX_STATIC 0
171#define BOARD_IDX_OVERFLOW -1
172
173#if (defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)) && \
174 defined(NETIF_F_HW_VLAN_RX)
175#define ACENIC_DO_VLAN 1
176#define ACE_RCB_VLAN_FLAG RCB_FLG_VLAN_ASSIST
177#else
178#define ACENIC_DO_VLAN 0
179#define ACE_RCB_VLAN_FLAG 0
180#endif
181
182#include "acenic.h"
183
184
185
186
187#define MAX_TEXT_LEN 96*1024
188#define MAX_RODATA_LEN 8*1024
189#define MAX_DATA_LEN 2*1024
190
191#ifndef tigon2FwReleaseLocal
192#define tigon2FwReleaseLocal 0
193#endif
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343#define RX_RING_SIZE 72
344#define RX_MINI_SIZE 64
345#define RX_JUMBO_SIZE 48
346
347#define RX_PANIC_STD_THRES 16
348#define RX_PANIC_STD_REFILL (3*RX_PANIC_STD_THRES)/2
349#define RX_LOW_STD_THRES (3*RX_RING_SIZE)/4
350#define RX_PANIC_MINI_THRES 12
351#define RX_PANIC_MINI_REFILL (3*RX_PANIC_MINI_THRES)/2
352#define RX_LOW_MINI_THRES (3*RX_MINI_SIZE)/4
353#define RX_PANIC_JUMBO_THRES 6
354#define RX_PANIC_JUMBO_REFILL (3*RX_PANIC_JUMBO_THRES)/2
355#define RX_LOW_JUMBO_THRES (3*RX_JUMBO_SIZE)/4
356
357
358
359
360
361
362#define ACE_MINI_SIZE 100
363
364#define ACE_MINI_BUFSIZE ACE_MINI_SIZE
365#define ACE_STD_BUFSIZE (ACE_STD_MTU + ETH_HLEN + 4)
366#define ACE_JUMBO_BUFSIZE (ACE_JUMBO_MTU + ETH_HLEN + 4)
367
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374
375
376#define DEF_TX_COAL 400
377#define DEF_TX_MAX_DESC 60
378#define DEF_RX_COAL 120
379#define DEF_RX_MAX_DESC 25
380#define DEF_TX_RATIO 21
381
382#define DEF_JUMBO_TX_COAL 20
383#define DEF_JUMBO_TX_MAX_DESC 60
384#define DEF_JUMBO_RX_COAL 30
385#define DEF_JUMBO_RX_MAX_DESC 6
386#define DEF_JUMBO_TX_RATIO 21
387
388#if tigon2FwReleaseLocal < 20001118
389
390
391
392
393
394
395
396#define TX_COAL_INTS_ONLY 1
397#else
398
399
400
401#define TX_COAL_INTS_ONLY 1
402#endif
403
404#define DEF_TRACE 0
405#define DEF_STAT (2 * TICKS_PER_SEC)
406
407
408static int link_state[ACE_MAX_MOD_PARMS];
409static int trace[ACE_MAX_MOD_PARMS];
410static int tx_coal_tick[ACE_MAX_MOD_PARMS];
411static int rx_coal_tick[ACE_MAX_MOD_PARMS];
412static int max_tx_desc[ACE_MAX_MOD_PARMS];
413static int max_rx_desc[ACE_MAX_MOD_PARMS];
414static int tx_ratio[ACE_MAX_MOD_PARMS];
415static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
416
417MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>");
418MODULE_LICENSE("GPL");
419MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver");
420#ifndef CONFIG_ACENIC_OMIT_TIGON_I
421MODULE_FIRMWARE("acenic/tg1.bin");
422#endif
423MODULE_FIRMWARE("acenic/tg2.bin");
424
425module_param_array_named(link, link_state, int, NULL, 0);
426module_param_array(trace, int, NULL, 0);
427module_param_array(tx_coal_tick, int, NULL, 0);
428module_param_array(max_tx_desc, int, NULL, 0);
429module_param_array(rx_coal_tick, int, NULL, 0);
430module_param_array(max_rx_desc, int, NULL, 0);
431module_param_array(tx_ratio, int, NULL, 0);
432MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state");
433MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level");
434MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives");
435MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait");
436MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives");
437MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait");
438MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)");
439
440
441static const char version[] __devinitconst =
442 "acenic.c: v0.92 08/05/2002 Jes Sorensen, linux-acenic@SunSITE.dk\n"
443 " http://home.cern.ch/~jes/gige/acenic.html\n";
444
445static int ace_get_settings(struct net_device *, struct ethtool_cmd *);
446static int ace_set_settings(struct net_device *, struct ethtool_cmd *);
447static void ace_get_drvinfo(struct net_device *, struct ethtool_drvinfo *);
448
449static const struct ethtool_ops ace_ethtool_ops = {
450 .get_settings = ace_get_settings,
451 .set_settings = ace_set_settings,
452 .get_drvinfo = ace_get_drvinfo,
453};
454
455static void ace_watchdog(struct net_device *dev);
456
457static const struct net_device_ops ace_netdev_ops = {
458 .ndo_open = ace_open,
459 .ndo_stop = ace_close,
460 .ndo_tx_timeout = ace_watchdog,
461 .ndo_get_stats = ace_get_stats,
462 .ndo_start_xmit = ace_start_xmit,
463 .ndo_set_multicast_list = ace_set_multicast_list,
464 .ndo_validate_addr = eth_validate_addr,
465 .ndo_set_mac_address = ace_set_mac_addr,
466 .ndo_change_mtu = ace_change_mtu,
467#if ACENIC_DO_VLAN
468 .ndo_vlan_rx_register = ace_vlan_rx_register,
469#endif
470};
471
472static int __devinit acenic_probe_one(struct pci_dev *pdev,
473 const struct pci_device_id *id)
474{
475 struct net_device *dev;
476 struct ace_private *ap;
477 static int boards_found;
478
479 dev = alloc_etherdev(sizeof(struct ace_private));
480 if (dev == NULL) {
481 printk(KERN_ERR "acenic: Unable to allocate "
482 "net_device structure!\n");
483 return -ENOMEM;
484 }
485
486 SET_NETDEV_DEV(dev, &pdev->dev);
487
488 ap = netdev_priv(dev);
489 ap->pdev = pdev;
490 ap->name = pci_name(pdev);
491
492 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
493#if ACENIC_DO_VLAN
494 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
495#endif
496
497 dev->watchdog_timeo = 5*HZ;
498
499 dev->netdev_ops = &ace_netdev_ops;
500 SET_ETHTOOL_OPS(dev, &ace_ethtool_ops);
501
502
503 if (!boards_found)
504 printk(version);
505
506 if (pci_enable_device(pdev))
507 goto fail_free_netdev;
508
509
510
511
512
513
514 pci_set_master(pdev);
515
516 pci_read_config_word(pdev, PCI_COMMAND, &ap->pci_command);
517
518
519 if (!(ap->pci_command & PCI_COMMAND_MEMORY)) {
520 printk(KERN_INFO "%s: Enabling PCI Memory Mapped "
521 "access - was not enabled by BIOS/Firmware\n",
522 ap->name);
523 ap->pci_command = ap->pci_command | PCI_COMMAND_MEMORY;
524 pci_write_config_word(ap->pdev, PCI_COMMAND,
525 ap->pci_command);
526 wmb();
527 }
528
529 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ap->pci_latency);
530 if (ap->pci_latency <= 0x40) {
531 ap->pci_latency = 0x40;
532 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ap->pci_latency);
533 }
534
535
536
537
538
539
540 dev->base_addr = pci_resource_start(pdev, 0);
541 ap->regs = ioremap(dev->base_addr, 0x4000);
542 if (!ap->regs) {
543 printk(KERN_ERR "%s: Unable to map I/O register, "
544 "AceNIC %i will be disabled.\n",
545 ap->name, boards_found);
546 goto fail_free_netdev;
547 }
548
549 switch(pdev->vendor) {
550 case PCI_VENDOR_ID_ALTEON:
551 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T) {
552 printk(KERN_INFO "%s: Farallon PN9100-T ",
553 ap->name);
554 } else {
555 printk(KERN_INFO "%s: Alteon AceNIC ",
556 ap->name);
557 }
558 break;
559 case PCI_VENDOR_ID_3COM:
560 printk(KERN_INFO "%s: 3Com 3C985 ", ap->name);
561 break;
562 case PCI_VENDOR_ID_NETGEAR:
563 printk(KERN_INFO "%s: NetGear GA620 ", ap->name);
564 break;
565 case PCI_VENDOR_ID_DEC:
566 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX) {
567 printk(KERN_INFO "%s: Farallon PN9000-SX ",
568 ap->name);
569 break;
570 }
571 case PCI_VENDOR_ID_SGI:
572 printk(KERN_INFO "%s: SGI AceNIC ", ap->name);
573 break;
574 default:
575 printk(KERN_INFO "%s: Unknown AceNIC ", ap->name);
576 break;
577 }
578
579 printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr);
580 printk("irq %d\n", pdev->irq);
581
582#ifdef CONFIG_ACENIC_OMIT_TIGON_I
583 if ((readl(&ap->regs->HostCtrl) >> 28) == 4) {
584 printk(KERN_ERR "%s: Driver compiled without Tigon I"
585 " support - NIC disabled\n", dev->name);
586 goto fail_uninit;
587 }
588#endif
589
590 if (ace_allocate_descriptors(dev))
591 goto fail_free_netdev;
592
593#ifdef MODULE
594 if (boards_found >= ACE_MAX_MOD_PARMS)
595 ap->board_idx = BOARD_IDX_OVERFLOW;
596 else
597 ap->board_idx = boards_found;
598#else
599 ap->board_idx = BOARD_IDX_STATIC;
600#endif
601
602 if (ace_init(dev))
603 goto fail_free_netdev;
604
605 if (register_netdev(dev)) {
606 printk(KERN_ERR "acenic: device registration failed\n");
607 goto fail_uninit;
608 }
609 ap->name = dev->name;
610
611 if (ap->pci_using_dac)
612 dev->features |= NETIF_F_HIGHDMA;
613
614 pci_set_drvdata(pdev, dev);
615
616 boards_found++;
617 return 0;
618
619 fail_uninit:
620 ace_init_cleanup(dev);
621 fail_free_netdev:
622 free_netdev(dev);
623 return -ENODEV;
624}
625
626static void __devexit acenic_remove_one(struct pci_dev *pdev)
627{
628 struct net_device *dev = pci_get_drvdata(pdev);
629 struct ace_private *ap = netdev_priv(dev);
630 struct ace_regs __iomem *regs = ap->regs;
631 short i;
632
633 unregister_netdev(dev);
634
635 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl);
636 if (ap->version >= 2)
637 writel(readl(®s->CpuBCtrl) | CPU_HALT, ®s->CpuBCtrl);
638
639
640
641
642 writel(1, ®s->Mb0Lo);
643 readl(®s->CpuCtrl);
644
645
646
647
648
649
650
651
652
653
654 ace_sync_irq(dev->irq);
655
656 for (i = 0; i < RX_STD_RING_ENTRIES; i++) {
657 struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb;
658
659 if (skb) {
660 struct ring_info *ringp;
661 dma_addr_t mapping;
662
663 ringp = &ap->skb->rx_std_skbuff[i];
664 mapping = dma_unmap_addr(ringp, mapping);
665 pci_unmap_page(ap->pdev, mapping,
666 ACE_STD_BUFSIZE,
667 PCI_DMA_FROMDEVICE);
668
669 ap->rx_std_ring[i].size = 0;
670 ap->skb->rx_std_skbuff[i].skb = NULL;
671 dev_kfree_skb(skb);
672 }
673 }
674
675 if (ap->version >= 2) {
676 for (i = 0; i < RX_MINI_RING_ENTRIES; i++) {
677 struct sk_buff *skb = ap->skb->rx_mini_skbuff[i].skb;
678
679 if (skb) {
680 struct ring_info *ringp;
681 dma_addr_t mapping;
682
683 ringp = &ap->skb->rx_mini_skbuff[i];
684 mapping = dma_unmap_addr(ringp,mapping);
685 pci_unmap_page(ap->pdev, mapping,
686 ACE_MINI_BUFSIZE,
687 PCI_DMA_FROMDEVICE);
688
689 ap->rx_mini_ring[i].size = 0;
690 ap->skb->rx_mini_skbuff[i].skb = NULL;
691 dev_kfree_skb(skb);
692 }
693 }
694 }
695
696 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
697 struct sk_buff *skb = ap->skb->rx_jumbo_skbuff[i].skb;
698 if (skb) {
699 struct ring_info *ringp;
700 dma_addr_t mapping;
701
702 ringp = &ap->skb->rx_jumbo_skbuff[i];
703 mapping = dma_unmap_addr(ringp, mapping);
704 pci_unmap_page(ap->pdev, mapping,
705 ACE_JUMBO_BUFSIZE,
706 PCI_DMA_FROMDEVICE);
707
708 ap->rx_jumbo_ring[i].size = 0;
709 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
710 dev_kfree_skb(skb);
711 }
712 }
713
714 ace_init_cleanup(dev);
715 free_netdev(dev);
716}
717
718static struct pci_driver acenic_pci_driver = {
719 .name = "acenic",
720 .id_table = acenic_pci_tbl,
721 .probe = acenic_probe_one,
722 .remove = __devexit_p(acenic_remove_one),
723};
724
725static int __init acenic_init(void)
726{
727 return pci_register_driver(&acenic_pci_driver);
728}
729
730static void __exit acenic_exit(void)
731{
732 pci_unregister_driver(&acenic_pci_driver);
733}
734
735module_init(acenic_init);
736module_exit(acenic_exit);
737
738static void ace_free_descriptors(struct net_device *dev)
739{
740 struct ace_private *ap = netdev_priv(dev);
741 int size;
742
743 if (ap->rx_std_ring != NULL) {
744 size = (sizeof(struct rx_desc) *
745 (RX_STD_RING_ENTRIES +
746 RX_JUMBO_RING_ENTRIES +
747 RX_MINI_RING_ENTRIES +
748 RX_RETURN_RING_ENTRIES));
749 pci_free_consistent(ap->pdev, size, ap->rx_std_ring,
750 ap->rx_ring_base_dma);
751 ap->rx_std_ring = NULL;
752 ap->rx_jumbo_ring = NULL;
753 ap->rx_mini_ring = NULL;
754 ap->rx_return_ring = NULL;
755 }
756 if (ap->evt_ring != NULL) {
757 size = (sizeof(struct event) * EVT_RING_ENTRIES);
758 pci_free_consistent(ap->pdev, size, ap->evt_ring,
759 ap->evt_ring_dma);
760 ap->evt_ring = NULL;
761 }
762 if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) {
763 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
764 pci_free_consistent(ap->pdev, size, ap->tx_ring,
765 ap->tx_ring_dma);
766 }
767 ap->tx_ring = NULL;
768
769 if (ap->evt_prd != NULL) {
770 pci_free_consistent(ap->pdev, sizeof(u32),
771 (void *)ap->evt_prd, ap->evt_prd_dma);
772 ap->evt_prd = NULL;
773 }
774 if (ap->rx_ret_prd != NULL) {
775 pci_free_consistent(ap->pdev, sizeof(u32),
776 (void *)ap->rx_ret_prd,
777 ap->rx_ret_prd_dma);
778 ap->rx_ret_prd = NULL;
779 }
780 if (ap->tx_csm != NULL) {
781 pci_free_consistent(ap->pdev, sizeof(u32),
782 (void *)ap->tx_csm, ap->tx_csm_dma);
783 ap->tx_csm = NULL;
784 }
785}
786
787
788static int ace_allocate_descriptors(struct net_device *dev)
789{
790 struct ace_private *ap = netdev_priv(dev);
791 int size;
792
793 size = (sizeof(struct rx_desc) *
794 (RX_STD_RING_ENTRIES +
795 RX_JUMBO_RING_ENTRIES +
796 RX_MINI_RING_ENTRIES +
797 RX_RETURN_RING_ENTRIES));
798
799 ap->rx_std_ring = pci_alloc_consistent(ap->pdev, size,
800 &ap->rx_ring_base_dma);
801 if (ap->rx_std_ring == NULL)
802 goto fail;
803
804 ap->rx_jumbo_ring = ap->rx_std_ring + RX_STD_RING_ENTRIES;
805 ap->rx_mini_ring = ap->rx_jumbo_ring + RX_JUMBO_RING_ENTRIES;
806 ap->rx_return_ring = ap->rx_mini_ring + RX_MINI_RING_ENTRIES;
807
808 size = (sizeof(struct event) * EVT_RING_ENTRIES);
809
810 ap->evt_ring = pci_alloc_consistent(ap->pdev, size, &ap->evt_ring_dma);
811
812 if (ap->evt_ring == NULL)
813 goto fail;
814
815
816
817
818
819 if (!ACE_IS_TIGON_I(ap)) {
820 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
821
822 ap->tx_ring = pci_alloc_consistent(ap->pdev, size,
823 &ap->tx_ring_dma);
824
825 if (ap->tx_ring == NULL)
826 goto fail;
827 }
828
829 ap->evt_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
830 &ap->evt_prd_dma);
831 if (ap->evt_prd == NULL)
832 goto fail;
833
834 ap->rx_ret_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
835 &ap->rx_ret_prd_dma);
836 if (ap->rx_ret_prd == NULL)
837 goto fail;
838
839 ap->tx_csm = pci_alloc_consistent(ap->pdev, sizeof(u32),
840 &ap->tx_csm_dma);
841 if (ap->tx_csm == NULL)
842 goto fail;
843
844 return 0;
845
846fail:
847
848 ace_init_cleanup(dev);
849 return 1;
850}
851
852
853
854
855
856
857static void ace_init_cleanup(struct net_device *dev)
858{
859 struct ace_private *ap;
860
861 ap = netdev_priv(dev);
862
863 ace_free_descriptors(dev);
864
865 if (ap->info)
866 pci_free_consistent(ap->pdev, sizeof(struct ace_info),
867 ap->info, ap->info_dma);
868 kfree(ap->skb);
869 kfree(ap->trace_buf);
870
871 if (dev->irq)
872 free_irq(dev->irq, dev);
873
874 iounmap(ap->regs);
875}
876
877
878
879
880
881static inline void ace_issue_cmd(struct ace_regs __iomem *regs, struct cmd *cmd)
882{
883 u32 idx;
884
885 idx = readl(®s->CmdPrd);
886
887 writel(*(u32 *)(cmd), ®s->CmdRng[idx]);
888 idx = (idx + 1) % CMD_RING_ENTRIES;
889
890 writel(idx, ®s->CmdPrd);
891}
892
893
894static int __devinit ace_init(struct net_device *dev)
895{
896 struct ace_private *ap;
897 struct ace_regs __iomem *regs;
898 struct ace_info *info = NULL;
899 struct pci_dev *pdev;
900 unsigned long myjif;
901 u64 tmp_ptr;
902 u32 tig_ver, mac1, mac2, tmp, pci_state;
903 int board_idx, ecode = 0;
904 short i;
905 unsigned char cache_size;
906
907 ap = netdev_priv(dev);
908 regs = ap->regs;
909
910 board_idx = ap->board_idx;
911
912
913
914
915
916
917 writel(HW_RESET | (HW_RESET << 24), ®s->HostCtrl);
918 readl(®s->HostCtrl);
919 udelay(5);
920
921
922
923
924#ifdef __BIG_ENDIAN
925
926
927
928
929 writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)),
930 ®s->HostCtrl);
931#else
932 writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)),
933 ®s->HostCtrl);
934#endif
935 readl(®s->HostCtrl);
936
937
938
939
940 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl);
941 readl(®s->CpuCtrl);
942 writel(0, ®s->Mb0Lo);
943
944 tig_ver = readl(®s->HostCtrl) >> 28;
945
946 switch(tig_ver){
947#ifndef CONFIG_ACENIC_OMIT_TIGON_I
948 case 4:
949 case 5:
950 printk(KERN_INFO " Tigon I (Rev. %i), Firmware: %i.%i.%i, ",
951 tig_ver, ap->firmware_major, ap->firmware_minor,
952 ap->firmware_fix);
953 writel(0, ®s->LocalCtrl);
954 ap->version = 1;
955 ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES;
956 break;
957#endif
958 case 6:
959 printk(KERN_INFO " Tigon II (Rev. %i), Firmware: %i.%i.%i, ",
960 tig_ver, ap->firmware_major, ap->firmware_minor,
961 ap->firmware_fix);
962 writel(readl(®s->CpuBCtrl) | CPU_HALT, ®s->CpuBCtrl);
963 readl(®s->CpuBCtrl);
964
965
966
967
968
969 writel(SRAM_BANK_512K, ®s->LocalCtrl);
970 writel(SYNC_SRAM_TIMING, ®s->MiscCfg);
971 ap->version = 2;
972 ap->tx_ring_entries = MAX_TX_RING_ENTRIES;
973 break;
974 default:
975 printk(KERN_WARNING " Unsupported Tigon version detected "
976 "(%i)\n", tig_ver);
977 ecode = -ENODEV;
978 goto init_error;
979 }
980
981
982
983
984
985
986
987
988#ifdef __BIG_ENDIAN
989 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD |
990 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, ®s->ModeStat);
991#else
992 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL |
993 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, ®s->ModeStat);
994#endif
995 readl(®s->ModeStat);
996
997 mac1 = 0;
998 for(i = 0; i < 4; i++) {
999 int t;
1000
1001 mac1 = mac1 << 8;
1002 t = read_eeprom_byte(dev, 0x8c+i);
1003 if (t < 0) {
1004 ecode = -EIO;
1005 goto init_error;
1006 } else
1007 mac1 |= (t & 0xff);
1008 }
1009 mac2 = 0;
1010 for(i = 4; i < 8; i++) {
1011 int t;
1012
1013 mac2 = mac2 << 8;
1014 t = read_eeprom_byte(dev, 0x8c+i);
1015 if (t < 0) {
1016 ecode = -EIO;
1017 goto init_error;
1018 } else
1019 mac2 |= (t & 0xff);
1020 }
1021
1022 writel(mac1, ®s->MacAddrHi);
1023 writel(mac2, ®s->MacAddrLo);
1024
1025 dev->dev_addr[0] = (mac1 >> 8) & 0xff;
1026 dev->dev_addr[1] = mac1 & 0xff;
1027 dev->dev_addr[2] = (mac2 >> 24) & 0xff;
1028 dev->dev_addr[3] = (mac2 >> 16) & 0xff;
1029 dev->dev_addr[4] = (mac2 >> 8) & 0xff;
1030 dev->dev_addr[5] = mac2 & 0xff;
1031
1032 printk("MAC: %pM\n", dev->dev_addr);
1033
1034
1035
1036
1037
1038
1039
1040 pdev = ap->pdev;
1041 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size);
1042 cache_size <<= 2;
1043 if (cache_size != SMP_CACHE_BYTES) {
1044 printk(KERN_INFO " PCI cache line size set incorrectly "
1045 "(%i bytes) by BIOS/FW, ", cache_size);
1046 if (cache_size > SMP_CACHE_BYTES)
1047 printk("expecting %i\n", SMP_CACHE_BYTES);
1048 else {
1049 printk("correcting to %i\n", SMP_CACHE_BYTES);
1050 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
1051 SMP_CACHE_BYTES >> 2);
1052 }
1053 }
1054
1055 pci_state = readl(®s->PciState);
1056 printk(KERN_INFO " PCI bus width: %i bits, speed: %iMHz, "
1057 "latency: %i clks\n",
1058 (pci_state & PCI_32BIT) ? 32 : 64,
1059 (pci_state & PCI_66MHZ) ? 66 : 33,
1060 ap->pci_latency);
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072 tmp = READ_CMD_MEM | WRITE_CMD_MEM;
1073 if (ap->version >= 2) {
1074 tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ));
1075
1076
1077
1078 if (board_idx == BOARD_IDX_OVERFLOW ||
1079 dis_pci_mem_inval[board_idx]) {
1080 if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1081 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1082 pci_write_config_word(pdev, PCI_COMMAND,
1083 ap->pci_command);
1084 printk(KERN_INFO " Disabling PCI memory "
1085 "write and invalidate\n");
1086 }
1087 } else if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1088 printk(KERN_INFO " PCI memory write & invalidate "
1089 "enabled by BIOS, enabling counter measures\n");
1090
1091 switch(SMP_CACHE_BYTES) {
1092 case 16:
1093 tmp |= DMA_WRITE_MAX_16;
1094 break;
1095 case 32:
1096 tmp |= DMA_WRITE_MAX_32;
1097 break;
1098 case 64:
1099 tmp |= DMA_WRITE_MAX_64;
1100 break;
1101 case 128:
1102 tmp |= DMA_WRITE_MAX_128;
1103 break;
1104 default:
1105 printk(KERN_INFO " Cache line size %i not "
1106 "supported, PCI write and invalidate "
1107 "disabled\n", SMP_CACHE_BYTES);
1108 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1109 pci_write_config_word(pdev, PCI_COMMAND,
1110 ap->pci_command);
1111 }
1112 }
1113 }
1114
1115#ifdef __sparc__
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127 tmp &= ~DMA_READ_WRITE_MASK;
1128 tmp |= DMA_READ_MAX_64;
1129 tmp |= DMA_WRITE_MAX_64;
1130#endif
1131#ifdef __alpha__
1132 tmp &= ~DMA_READ_WRITE_MASK;
1133 tmp |= DMA_READ_MAX_128;
1134
1135
1136
1137
1138
1139 tmp |= DMA_WRITE_MAX_128;
1140#endif
1141 writel(tmp, ®s->PciState);
1142
1143#if 0
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155 if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) {
1156 printk(KERN_INFO " Enabling PCI Fast Back to Back\n");
1157 ap->pci_command |= PCI_COMMAND_FAST_BACK;
1158 pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command);
1159 }
1160#endif
1161
1162
1163
1164
1165 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1166 ap->pci_using_dac = 1;
1167 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1168 ap->pci_using_dac = 0;
1169 } else {
1170 ecode = -ENODEV;
1171 goto init_error;
1172 }
1173
1174
1175
1176
1177
1178
1179 if (!(info = pci_alloc_consistent(ap->pdev, sizeof(struct ace_info),
1180 &ap->info_dma))) {
1181 ecode = -EAGAIN;
1182 goto init_error;
1183 }
1184 ap->info = info;
1185
1186
1187
1188
1189 if (!(ap->skb = kmalloc(sizeof(struct ace_skb), GFP_KERNEL))) {
1190 ecode = -EAGAIN;
1191 goto init_error;
1192 }
1193
1194 ecode = request_irq(pdev->irq, ace_interrupt, IRQF_SHARED,
1195 DRV_NAME, dev);
1196 if (ecode) {
1197 printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
1198 DRV_NAME, pdev->irq);
1199 goto init_error;
1200 } else
1201 dev->irq = pdev->irq;
1202
1203#ifdef INDEX_DEBUG
1204 spin_lock_init(&ap->debug_lock);
1205 ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1;
1206 ap->last_std_rx = 0;
1207 ap->last_mini_rx = 0;
1208#endif
1209
1210 memset(ap->info, 0, sizeof(struct ace_info));
1211 memset(ap->skb, 0, sizeof(struct ace_skb));
1212
1213 ecode = ace_load_firmware(dev);
1214 if (ecode)
1215 goto init_error;
1216
1217 ap->fw_running = 0;
1218
1219 tmp_ptr = ap->info_dma;
1220 writel(tmp_ptr >> 32, ®s->InfoPtrHi);
1221 writel(tmp_ptr & 0xffffffff, ®s->InfoPtrLo);
1222
1223 memset(ap->evt_ring, 0, EVT_RING_ENTRIES * sizeof(struct event));
1224
1225 set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma);
1226 info->evt_ctrl.flags = 0;
1227
1228 *(ap->evt_prd) = 0;
1229 wmb();
1230 set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma);
1231 writel(0, ®s->EvtCsm);
1232
1233 set_aceaddr(&info->cmd_ctrl.rngptr, 0x100);
1234 info->cmd_ctrl.flags = 0;
1235 info->cmd_ctrl.max_len = 0;
1236
1237 for (i = 0; i < CMD_RING_ENTRIES; i++)
1238 writel(0, ®s->CmdRng[i]);
1239
1240 writel(0, ®s->CmdPrd);
1241 writel(0, ®s->CmdCsm);
1242
1243 tmp_ptr = ap->info_dma;
1244 tmp_ptr += (unsigned long) &(((struct ace_info *)0)->s.stats);
1245 set_aceaddr(&info->stats2_ptr, (dma_addr_t) tmp_ptr);
1246
1247 set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma);
1248 info->rx_std_ctrl.max_len = ACE_STD_BUFSIZE;
1249 info->rx_std_ctrl.flags =
1250 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1251
1252 memset(ap->rx_std_ring, 0,
1253 RX_STD_RING_ENTRIES * sizeof(struct rx_desc));
1254
1255 for (i = 0; i < RX_STD_RING_ENTRIES; i++)
1256 ap->rx_std_ring[i].flags = BD_FLG_TCP_UDP_SUM;
1257
1258 ap->rx_std_skbprd = 0;
1259 atomic_set(&ap->cur_rx_bufs, 0);
1260
1261 set_aceaddr(&info->rx_jumbo_ctrl.rngptr,
1262 (ap->rx_ring_base_dma +
1263 (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES)));
1264 info->rx_jumbo_ctrl.max_len = 0;
1265 info->rx_jumbo_ctrl.flags =
1266 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1267
1268 memset(ap->rx_jumbo_ring, 0,
1269 RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc));
1270
1271 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++)
1272 ap->rx_jumbo_ring[i].flags = BD_FLG_TCP_UDP_SUM | BD_FLG_JUMBO;
1273
1274 ap->rx_jumbo_skbprd = 0;
1275 atomic_set(&ap->cur_jumbo_bufs, 0);
1276
1277 memset(ap->rx_mini_ring, 0,
1278 RX_MINI_RING_ENTRIES * sizeof(struct rx_desc));
1279
1280 if (ap->version >= 2) {
1281 set_aceaddr(&info->rx_mini_ctrl.rngptr,
1282 (ap->rx_ring_base_dma +
1283 (sizeof(struct rx_desc) *
1284 (RX_STD_RING_ENTRIES +
1285 RX_JUMBO_RING_ENTRIES))));
1286 info->rx_mini_ctrl.max_len = ACE_MINI_SIZE;
1287 info->rx_mini_ctrl.flags =
1288 RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|ACE_RCB_VLAN_FLAG;
1289
1290 for (i = 0; i < RX_MINI_RING_ENTRIES; i++)
1291 ap->rx_mini_ring[i].flags =
1292 BD_FLG_TCP_UDP_SUM | BD_FLG_MINI;
1293 } else {
1294 set_aceaddr(&info->rx_mini_ctrl.rngptr, 0);
1295 info->rx_mini_ctrl.flags = RCB_FLG_RNG_DISABLE;
1296 info->rx_mini_ctrl.max_len = 0;
1297 }
1298
1299 ap->rx_mini_skbprd = 0;
1300 atomic_set(&ap->cur_mini_bufs, 0);
1301
1302 set_aceaddr(&info->rx_return_ctrl.rngptr,
1303 (ap->rx_ring_base_dma +
1304 (sizeof(struct rx_desc) *
1305 (RX_STD_RING_ENTRIES +
1306 RX_JUMBO_RING_ENTRIES +
1307 RX_MINI_RING_ENTRIES))));
1308 info->rx_return_ctrl.flags = 0;
1309 info->rx_return_ctrl.max_len = RX_RETURN_RING_ENTRIES;
1310
1311 memset(ap->rx_return_ring, 0,
1312 RX_RETURN_RING_ENTRIES * sizeof(struct rx_desc));
1313
1314 set_aceaddr(&info->rx_ret_prd_ptr, ap->rx_ret_prd_dma);
1315 *(ap->rx_ret_prd) = 0;
1316
1317 writel(TX_RING_BASE, ®s->WinBase);
1318
1319 if (ACE_IS_TIGON_I(ap)) {
1320 ap->tx_ring = (__force struct tx_desc *) regs->Window;
1321 for (i = 0; i < (TIGON_I_TX_RING_ENTRIES
1322 * sizeof(struct tx_desc)) / sizeof(u32); i++)
1323 writel(0, (__force void __iomem *)ap->tx_ring + i * 4);
1324
1325 set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE);
1326 } else {
1327 memset(ap->tx_ring, 0,
1328 MAX_TX_RING_ENTRIES * sizeof(struct tx_desc));
1329
1330 set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma);
1331 }
1332
1333 info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap);
1334 tmp = RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1335
1336
1337
1338
1339 if (!ACE_IS_TIGON_I(ap))
1340 tmp |= RCB_FLG_TX_HOST_RING;
1341#if TX_COAL_INTS_ONLY
1342 tmp |= RCB_FLG_COAL_INT_ONLY;
1343#endif
1344 info->tx_ctrl.flags = tmp;
1345
1346 set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma);
1347
1348
1349
1350
1351#if 0
1352 writel(DMA_THRESH_16W, ®s->DmaReadCfg);
1353 writel(DMA_THRESH_16W, ®s->DmaWriteCfg);
1354#else
1355 writel(DMA_THRESH_8W, ®s->DmaReadCfg);
1356 writel(DMA_THRESH_8W, ®s->DmaWriteCfg);
1357#endif
1358
1359 writel(0, ®s->MaskInt);
1360 writel(1, ®s->IfIdx);
1361#if 0
1362
1363
1364
1365
1366 writel(1, ®s->AssistState);
1367#endif
1368
1369 writel(DEF_STAT, ®s->TuneStatTicks);
1370 writel(DEF_TRACE, ®s->TuneTrace);
1371
1372 ace_set_rxtx_parms(dev, 0);
1373
1374 if (board_idx == BOARD_IDX_OVERFLOW) {
1375 printk(KERN_WARNING "%s: more than %i NICs detected, "
1376 "ignoring module parameters!\n",
1377 ap->name, ACE_MAX_MOD_PARMS);
1378 } else if (board_idx >= 0) {
1379 if (tx_coal_tick[board_idx])
1380 writel(tx_coal_tick[board_idx],
1381 ®s->TuneTxCoalTicks);
1382 if (max_tx_desc[board_idx])
1383 writel(max_tx_desc[board_idx], ®s->TuneMaxTxDesc);
1384
1385 if (rx_coal_tick[board_idx])
1386 writel(rx_coal_tick[board_idx],
1387 ®s->TuneRxCoalTicks);
1388 if (max_rx_desc[board_idx])
1389 writel(max_rx_desc[board_idx], ®s->TuneMaxRxDesc);
1390
1391 if (trace[board_idx])
1392 writel(trace[board_idx], ®s->TuneTrace);
1393
1394 if ((tx_ratio[board_idx] > 0) && (tx_ratio[board_idx] < 64))
1395 writel(tx_ratio[board_idx], ®s->TxBufRat);
1396 }
1397
1398
1399
1400
1401 tmp = LNK_ENABLE | LNK_FULL_DUPLEX | LNK_1000MB | LNK_100MB |
1402 LNK_10MB | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE;
1403 if(ap->version >= 2)
1404 tmp |= LNK_TX_FLOW_CTL_Y;
1405
1406
1407
1408
1409 if ((board_idx >= 0) && link_state[board_idx]) {
1410 int option = link_state[board_idx];
1411
1412 tmp = LNK_ENABLE;
1413
1414 if (option & 0x01) {
1415 printk(KERN_INFO "%s: Setting half duplex link\n",
1416 ap->name);
1417 tmp &= ~LNK_FULL_DUPLEX;
1418 }
1419 if (option & 0x02)
1420 tmp &= ~LNK_NEGOTIATE;
1421 if (option & 0x10)
1422 tmp |= LNK_10MB;
1423 if (option & 0x20)
1424 tmp |= LNK_100MB;
1425 if (option & 0x40)
1426 tmp |= LNK_1000MB;
1427 if ((option & 0x70) == 0) {
1428 printk(KERN_WARNING "%s: No media speed specified, "
1429 "forcing auto negotiation\n", ap->name);
1430 tmp |= LNK_NEGOTIATE | LNK_1000MB |
1431 LNK_100MB | LNK_10MB;
1432 }
1433 if ((option & 0x100) == 0)
1434 tmp |= LNK_NEG_FCTL;
1435 else
1436 printk(KERN_INFO "%s: Disabling flow control "
1437 "negotiation\n", ap->name);
1438 if (option & 0x200)
1439 tmp |= LNK_RX_FLOW_CTL_Y;
1440 if ((option & 0x400) && (ap->version >= 2)) {
1441 printk(KERN_INFO "%s: Enabling TX flow control\n",
1442 ap->name);
1443 tmp |= LNK_TX_FLOW_CTL_Y;
1444 }
1445 }
1446
1447 ap->link = tmp;
1448 writel(tmp, ®s->TuneLink);
1449 if (ap->version >= 2)
1450 writel(tmp, ®s->TuneFastLink);
1451
1452 writel(ap->firmware_start, ®s->Pc);
1453
1454 writel(0, ®s->Mb0Lo);
1455
1456
1457
1458
1459
1460
1461
1462 ap->cur_rx = 0;
1463 ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0;
1464
1465 wmb();
1466 ace_set_txprd(regs, ap, 0);
1467 writel(0, ®s->RxRetCsm);
1468
1469
1470
1471
1472
1473
1474
1475 writel(1, ®s->AssistState);
1476
1477
1478
1479
1480 writel(readl(®s->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), ®s->CpuCtrl);
1481 readl(®s->CpuCtrl);
1482
1483
1484
1485
1486 myjif = jiffies + 3 * HZ;
1487 while (time_before(jiffies, myjif) && !ap->fw_running)
1488 cpu_relax();
1489
1490 if (!ap->fw_running) {
1491 printk(KERN_ERR "%s: Firmware NOT running!\n", ap->name);
1492
1493 ace_dump_trace(ap);
1494 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl);
1495 readl(®s->CpuCtrl);
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506 if (ap->version >= 2)
1507 writel(readl(®s->CpuBCtrl) | CPU_HALT,
1508 ®s->CpuBCtrl);
1509 writel(0, ®s->Mb0Lo);
1510 readl(®s->Mb0Lo);
1511
1512 ecode = -EBUSY;
1513 goto init_error;
1514 }
1515
1516
1517
1518
1519
1520 if (!test_and_set_bit(0, &ap->std_refill_busy))
1521 ace_load_std_rx_ring(ap, RX_RING_SIZE);
1522 else
1523 printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n",
1524 ap->name);
1525 if (ap->version >= 2) {
1526 if (!test_and_set_bit(0, &ap->mini_refill_busy))
1527 ace_load_mini_rx_ring(ap, RX_MINI_SIZE);
1528 else
1529 printk(KERN_ERR "%s: Someone is busy refilling "
1530 "the RX mini ring\n", ap->name);
1531 }
1532 return 0;
1533
1534 init_error:
1535 ace_init_cleanup(dev);
1536 return ecode;
1537}
1538
1539
1540static void ace_set_rxtx_parms(struct net_device *dev, int jumbo)
1541{
1542 struct ace_private *ap = netdev_priv(dev);
1543 struct ace_regs __iomem *regs = ap->regs;
1544 int board_idx = ap->board_idx;
1545
1546 if (board_idx >= 0) {
1547 if (!jumbo) {
1548 if (!tx_coal_tick[board_idx])
1549 writel(DEF_TX_COAL, ®s->TuneTxCoalTicks);
1550 if (!max_tx_desc[board_idx])
1551 writel(DEF_TX_MAX_DESC, ®s->TuneMaxTxDesc);
1552 if (!rx_coal_tick[board_idx])
1553 writel(DEF_RX_COAL, ®s->TuneRxCoalTicks);
1554 if (!max_rx_desc[board_idx])
1555 writel(DEF_RX_MAX_DESC, ®s->TuneMaxRxDesc);
1556 if (!tx_ratio[board_idx])
1557 writel(DEF_TX_RATIO, ®s->TxBufRat);
1558 } else {
1559 if (!tx_coal_tick[board_idx])
1560 writel(DEF_JUMBO_TX_COAL,
1561 ®s->TuneTxCoalTicks);
1562 if (!max_tx_desc[board_idx])
1563 writel(DEF_JUMBO_TX_MAX_DESC,
1564 ®s->TuneMaxTxDesc);
1565 if (!rx_coal_tick[board_idx])
1566 writel(DEF_JUMBO_RX_COAL,
1567 ®s->TuneRxCoalTicks);
1568 if (!max_rx_desc[board_idx])
1569 writel(DEF_JUMBO_RX_MAX_DESC,
1570 ®s->TuneMaxRxDesc);
1571 if (!tx_ratio[board_idx])
1572 writel(DEF_JUMBO_TX_RATIO, ®s->TxBufRat);
1573 }
1574 }
1575}
1576
1577
1578static void ace_watchdog(struct net_device *data)
1579{
1580 struct net_device *dev = data;
1581 struct ace_private *ap = netdev_priv(dev);
1582 struct ace_regs __iomem *regs = ap->regs;
1583
1584
1585
1586
1587
1588
1589 if (*ap->tx_csm != ap->tx_ret_csm) {
1590 printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n",
1591 dev->name, (unsigned int)readl(®s->HostCtrl));
1592
1593 } else {
1594 printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n",
1595 dev->name);
1596#if 0
1597 netif_wake_queue(dev);
1598#endif
1599 }
1600}
1601
1602
1603static void ace_tasklet(unsigned long dev)
1604{
1605 struct ace_private *ap = netdev_priv((struct net_device *)dev);
1606 int cur_size;
1607
1608 cur_size = atomic_read(&ap->cur_rx_bufs);
1609 if ((cur_size < RX_LOW_STD_THRES) &&
1610 !test_and_set_bit(0, &ap->std_refill_busy)) {
1611#ifdef DEBUG
1612 printk("refilling buffers (current %i)\n", cur_size);
1613#endif
1614 ace_load_std_rx_ring(ap, RX_RING_SIZE - cur_size);
1615 }
1616
1617 if (ap->version >= 2) {
1618 cur_size = atomic_read(&ap->cur_mini_bufs);
1619 if ((cur_size < RX_LOW_MINI_THRES) &&
1620 !test_and_set_bit(0, &ap->mini_refill_busy)) {
1621#ifdef DEBUG
1622 printk("refilling mini buffers (current %i)\n",
1623 cur_size);
1624#endif
1625 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
1626 }
1627 }
1628
1629 cur_size = atomic_read(&ap->cur_jumbo_bufs);
1630 if (ap->jumbo && (cur_size < RX_LOW_JUMBO_THRES) &&
1631 !test_and_set_bit(0, &ap->jumbo_refill_busy)) {
1632#ifdef DEBUG
1633 printk("refilling jumbo buffers (current %i)\n", cur_size);
1634#endif
1635 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
1636 }
1637 ap->tasklet_pending = 0;
1638}
1639
1640
1641
1642
1643
1644static void ace_dump_trace(struct ace_private *ap)
1645{
1646#if 0
1647 if (!ap->trace_buf)
1648 if (!(ap->trace_buf = kmalloc(ACE_TRACE_SIZE, GFP_KERNEL)))
1649 return;
1650#endif
1651}
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661static void ace_load_std_rx_ring(struct ace_private *ap, int nr_bufs)
1662{
1663 struct ace_regs __iomem *regs = ap->regs;
1664 short i, idx;
1665
1666
1667 prefetchw(&ap->cur_rx_bufs);
1668
1669 idx = ap->rx_std_skbprd;
1670
1671 for (i = 0; i < nr_bufs; i++) {
1672 struct sk_buff *skb;
1673 struct rx_desc *rd;
1674 dma_addr_t mapping;
1675
1676 skb = alloc_skb(ACE_STD_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1677 if (!skb)
1678 break;
1679
1680 skb_reserve(skb, NET_IP_ALIGN);
1681 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1682 offset_in_page(skb->data),
1683 ACE_STD_BUFSIZE,
1684 PCI_DMA_FROMDEVICE);
1685 ap->skb->rx_std_skbuff[idx].skb = skb;
1686 dma_unmap_addr_set(&ap->skb->rx_std_skbuff[idx],
1687 mapping, mapping);
1688
1689 rd = &ap->rx_std_ring[idx];
1690 set_aceaddr(&rd->addr, mapping);
1691 rd->size = ACE_STD_BUFSIZE;
1692 rd->idx = idx;
1693 idx = (idx + 1) % RX_STD_RING_ENTRIES;
1694 }
1695
1696 if (!i)
1697 goto error_out;
1698
1699 atomic_add(i, &ap->cur_rx_bufs);
1700 ap->rx_std_skbprd = idx;
1701
1702 if (ACE_IS_TIGON_I(ap)) {
1703 struct cmd cmd;
1704 cmd.evt = C_SET_RX_PRD_IDX;
1705 cmd.code = 0;
1706 cmd.idx = ap->rx_std_skbprd;
1707 ace_issue_cmd(regs, &cmd);
1708 } else {
1709 writel(idx, ®s->RxStdPrd);
1710 wmb();
1711 }
1712
1713 out:
1714 clear_bit(0, &ap->std_refill_busy);
1715 return;
1716
1717 error_out:
1718 printk(KERN_INFO "Out of memory when allocating "
1719 "standard receive buffers\n");
1720 goto out;
1721}
1722
1723
1724static void ace_load_mini_rx_ring(struct ace_private *ap, int nr_bufs)
1725{
1726 struct ace_regs __iomem *regs = ap->regs;
1727 short i, idx;
1728
1729 prefetchw(&ap->cur_mini_bufs);
1730
1731 idx = ap->rx_mini_skbprd;
1732 for (i = 0; i < nr_bufs; i++) {
1733 struct sk_buff *skb;
1734 struct rx_desc *rd;
1735 dma_addr_t mapping;
1736
1737 skb = alloc_skb(ACE_MINI_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1738 if (!skb)
1739 break;
1740
1741 skb_reserve(skb, NET_IP_ALIGN);
1742 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1743 offset_in_page(skb->data),
1744 ACE_MINI_BUFSIZE,
1745 PCI_DMA_FROMDEVICE);
1746 ap->skb->rx_mini_skbuff[idx].skb = skb;
1747 dma_unmap_addr_set(&ap->skb->rx_mini_skbuff[idx],
1748 mapping, mapping);
1749
1750 rd = &ap->rx_mini_ring[idx];
1751 set_aceaddr(&rd->addr, mapping);
1752 rd->size = ACE_MINI_BUFSIZE;
1753 rd->idx = idx;
1754 idx = (idx + 1) % RX_MINI_RING_ENTRIES;
1755 }
1756
1757 if (!i)
1758 goto error_out;
1759
1760 atomic_add(i, &ap->cur_mini_bufs);
1761
1762 ap->rx_mini_skbprd = idx;
1763
1764 writel(idx, ®s->RxMiniPrd);
1765 wmb();
1766
1767 out:
1768 clear_bit(0, &ap->mini_refill_busy);
1769 return;
1770 error_out:
1771 printk(KERN_INFO "Out of memory when allocating "
1772 "mini receive buffers\n");
1773 goto out;
1774}
1775
1776
1777
1778
1779
1780
1781static void ace_load_jumbo_rx_ring(struct ace_private *ap, int nr_bufs)
1782{
1783 struct ace_regs __iomem *regs = ap->regs;
1784 short i, idx;
1785
1786 idx = ap->rx_jumbo_skbprd;
1787
1788 for (i = 0; i < nr_bufs; i++) {
1789 struct sk_buff *skb;
1790 struct rx_desc *rd;
1791 dma_addr_t mapping;
1792
1793 skb = alloc_skb(ACE_JUMBO_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1794 if (!skb)
1795 break;
1796
1797 skb_reserve(skb, NET_IP_ALIGN);
1798 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1799 offset_in_page(skb->data),
1800 ACE_JUMBO_BUFSIZE,
1801 PCI_DMA_FROMDEVICE);
1802 ap->skb->rx_jumbo_skbuff[idx].skb = skb;
1803 dma_unmap_addr_set(&ap->skb->rx_jumbo_skbuff[idx],
1804 mapping, mapping);
1805
1806 rd = &ap->rx_jumbo_ring[idx];
1807 set_aceaddr(&rd->addr, mapping);
1808 rd->size = ACE_JUMBO_BUFSIZE;
1809 rd->idx = idx;
1810 idx = (idx + 1) % RX_JUMBO_RING_ENTRIES;
1811 }
1812
1813 if (!i)
1814 goto error_out;
1815
1816 atomic_add(i, &ap->cur_jumbo_bufs);
1817 ap->rx_jumbo_skbprd = idx;
1818
1819 if (ACE_IS_TIGON_I(ap)) {
1820 struct cmd cmd;
1821 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1822 cmd.code = 0;
1823 cmd.idx = ap->rx_jumbo_skbprd;
1824 ace_issue_cmd(regs, &cmd);
1825 } else {
1826 writel(idx, ®s->RxJumboPrd);
1827 wmb();
1828 }
1829
1830 out:
1831 clear_bit(0, &ap->jumbo_refill_busy);
1832 return;
1833 error_out:
1834 if (net_ratelimit())
1835 printk(KERN_INFO "Out of memory when allocating "
1836 "jumbo receive buffers\n");
1837 goto out;
1838}
1839
1840
1841
1842
1843
1844
1845
1846static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd)
1847{
1848 struct ace_private *ap;
1849
1850 ap = netdev_priv(dev);
1851
1852 while (evtcsm != evtprd) {
1853 switch (ap->evt_ring[evtcsm].evt) {
1854 case E_FW_RUNNING:
1855 printk(KERN_INFO "%s: Firmware up and running\n",
1856 ap->name);
1857 ap->fw_running = 1;
1858 wmb();
1859 break;
1860 case E_STATS_UPDATED:
1861 break;
1862 case E_LNK_STATE:
1863 {
1864 u16 code = ap->evt_ring[evtcsm].code;
1865 switch (code) {
1866 case E_C_LINK_UP:
1867 {
1868 u32 state = readl(&ap->regs->GigLnkState);
1869 printk(KERN_WARNING "%s: Optical link UP "
1870 "(%s Duplex, Flow Control: %s%s)\n",
1871 ap->name,
1872 state & LNK_FULL_DUPLEX ? "Full":"Half",
1873 state & LNK_TX_FLOW_CTL_Y ? "TX " : "",
1874 state & LNK_RX_FLOW_CTL_Y ? "RX" : "");
1875 break;
1876 }
1877 case E_C_LINK_DOWN:
1878 printk(KERN_WARNING "%s: Optical link DOWN\n",
1879 ap->name);
1880 break;
1881 case E_C_LINK_10_100:
1882 printk(KERN_WARNING "%s: 10/100BaseT link "
1883 "UP\n", ap->name);
1884 break;
1885 default:
1886 printk(KERN_ERR "%s: Unknown optical link "
1887 "state %02x\n", ap->name, code);
1888 }
1889 break;
1890 }
1891 case E_ERROR:
1892 switch(ap->evt_ring[evtcsm].code) {
1893 case E_C_ERR_INVAL_CMD:
1894 printk(KERN_ERR "%s: invalid command error\n",
1895 ap->name);
1896 break;
1897 case E_C_ERR_UNIMP_CMD:
1898 printk(KERN_ERR "%s: unimplemented command "
1899 "error\n", ap->name);
1900 break;
1901 case E_C_ERR_BAD_CFG:
1902 printk(KERN_ERR "%s: bad config error\n",
1903 ap->name);
1904 break;
1905 default:
1906 printk(KERN_ERR "%s: unknown error %02x\n",
1907 ap->name, ap->evt_ring[evtcsm].code);
1908 }
1909 break;
1910 case E_RESET_JUMBO_RNG:
1911 {
1912 int i;
1913 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
1914 if (ap->skb->rx_jumbo_skbuff[i].skb) {
1915 ap->rx_jumbo_ring[i].size = 0;
1916 set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0);
1917 dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb);
1918 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
1919 }
1920 }
1921
1922 if (ACE_IS_TIGON_I(ap)) {
1923 struct cmd cmd;
1924 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1925 cmd.code = 0;
1926 cmd.idx = 0;
1927 ace_issue_cmd(ap->regs, &cmd);
1928 } else {
1929 writel(0, &((ap->regs)->RxJumboPrd));
1930 wmb();
1931 }
1932
1933 ap->jumbo = 0;
1934 ap->rx_jumbo_skbprd = 0;
1935 printk(KERN_INFO "%s: Jumbo ring flushed\n",
1936 ap->name);
1937 clear_bit(0, &ap->jumbo_refill_busy);
1938 break;
1939 }
1940 default:
1941 printk(KERN_ERR "%s: Unhandled event 0x%02x\n",
1942 ap->name, ap->evt_ring[evtcsm].evt);
1943 }
1944 evtcsm = (evtcsm + 1) % EVT_RING_ENTRIES;
1945 }
1946
1947 return evtcsm;
1948}
1949
1950
1951static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm)
1952{
1953 struct ace_private *ap = netdev_priv(dev);
1954 u32 idx;
1955 int mini_count = 0, std_count = 0;
1956
1957 idx = rxretcsm;
1958
1959 prefetchw(&ap->cur_rx_bufs);
1960 prefetchw(&ap->cur_mini_bufs);
1961
1962 while (idx != rxretprd) {
1963 struct ring_info *rip;
1964 struct sk_buff *skb;
1965 struct rx_desc *rxdesc, *retdesc;
1966 u32 skbidx;
1967 int bd_flags, desc_type, mapsize;
1968 u16 csum;
1969
1970
1971
1972 if (idx == rxretcsm)
1973 rmb();
1974
1975 retdesc = &ap->rx_return_ring[idx];
1976 skbidx = retdesc->idx;
1977 bd_flags = retdesc->flags;
1978 desc_type = bd_flags & (BD_FLG_JUMBO | BD_FLG_MINI);
1979
1980 switch(desc_type) {
1981
1982
1983
1984
1985
1986
1987
1988 case 0:
1989 rip = &ap->skb->rx_std_skbuff[skbidx];
1990 mapsize = ACE_STD_BUFSIZE;
1991 rxdesc = &ap->rx_std_ring[skbidx];
1992 std_count++;
1993 break;
1994 case BD_FLG_JUMBO:
1995 rip = &ap->skb->rx_jumbo_skbuff[skbidx];
1996 mapsize = ACE_JUMBO_BUFSIZE;
1997 rxdesc = &ap->rx_jumbo_ring[skbidx];
1998 atomic_dec(&ap->cur_jumbo_bufs);
1999 break;
2000 case BD_FLG_MINI:
2001 rip = &ap->skb->rx_mini_skbuff[skbidx];
2002 mapsize = ACE_MINI_BUFSIZE;
2003 rxdesc = &ap->rx_mini_ring[skbidx];
2004 mini_count++;
2005 break;
2006 default:
2007 printk(KERN_INFO "%s: unknown frame type (0x%02x) "
2008 "returned by NIC\n", dev->name,
2009 retdesc->flags);
2010 goto error;
2011 }
2012
2013 skb = rip->skb;
2014 rip->skb = NULL;
2015 pci_unmap_page(ap->pdev,
2016 dma_unmap_addr(rip, mapping),
2017 mapsize,
2018 PCI_DMA_FROMDEVICE);
2019 skb_put(skb, retdesc->size);
2020
2021
2022
2023
2024 csum = retdesc->tcp_udp_csum;
2025
2026 skb->protocol = eth_type_trans(skb, dev);
2027
2028
2029
2030
2031
2032 if (bd_flags & BD_FLG_TCP_UDP_SUM) {
2033 skb->csum = htons(csum);
2034 skb->ip_summed = CHECKSUM_COMPLETE;
2035 } else {
2036 skb_checksum_none_assert(skb);
2037 }
2038
2039
2040#if ACENIC_DO_VLAN
2041 if (ap->vlgrp && (bd_flags & BD_FLG_VLAN_TAG)) {
2042 vlan_hwaccel_rx(skb, ap->vlgrp, retdesc->vlan);
2043 } else
2044#endif
2045 netif_rx(skb);
2046
2047 dev->stats.rx_packets++;
2048 dev->stats.rx_bytes += retdesc->size;
2049
2050 idx = (idx + 1) % RX_RETURN_RING_ENTRIES;
2051 }
2052
2053 atomic_sub(std_count, &ap->cur_rx_bufs);
2054 if (!ACE_IS_TIGON_I(ap))
2055 atomic_sub(mini_count, &ap->cur_mini_bufs);
2056
2057 out:
2058
2059
2060
2061
2062 if (ACE_IS_TIGON_I(ap)) {
2063 writel(idx, &ap->regs->RxRetCsm);
2064 }
2065 ap->cur_rx = idx;
2066
2067 return;
2068 error:
2069 idx = rxretprd;
2070 goto out;
2071}
2072
2073
2074static inline void ace_tx_int(struct net_device *dev,
2075 u32 txcsm, u32 idx)
2076{
2077 struct ace_private *ap = netdev_priv(dev);
2078
2079 do {
2080 struct sk_buff *skb;
2081 struct tx_ring_info *info;
2082
2083 info = ap->skb->tx_skbuff + idx;
2084 skb = info->skb;
2085
2086 if (dma_unmap_len(info, maplen)) {
2087 pci_unmap_page(ap->pdev, dma_unmap_addr(info, mapping),
2088 dma_unmap_len(info, maplen),
2089 PCI_DMA_TODEVICE);
2090 dma_unmap_len_set(info, maplen, 0);
2091 }
2092
2093 if (skb) {
2094 dev->stats.tx_packets++;
2095 dev->stats.tx_bytes += skb->len;
2096 dev_kfree_skb_irq(skb);
2097 info->skb = NULL;
2098 }
2099
2100 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2101 } while (idx != txcsm);
2102
2103 if (netif_queue_stopped(dev))
2104 netif_wake_queue(dev);
2105
2106 wmb();
2107 ap->tx_ret_csm = txcsm;
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136}
2137
2138
2139static irqreturn_t ace_interrupt(int irq, void *dev_id)
2140{
2141 struct net_device *dev = (struct net_device *)dev_id;
2142 struct ace_private *ap = netdev_priv(dev);
2143 struct ace_regs __iomem *regs = ap->regs;
2144 u32 idx;
2145 u32 txcsm, rxretcsm, rxretprd;
2146 u32 evtcsm, evtprd;
2147
2148
2149
2150
2151
2152
2153 if (!(readl(®s->HostCtrl) & IN_INT))
2154 return IRQ_NONE;
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164 writel(0, ®s->Mb0Lo);
2165 readl(®s->Mb0Lo);
2166
2167
2168
2169
2170
2171
2172
2173
2174 rxretprd = *ap->rx_ret_prd;
2175 rxretcsm = ap->cur_rx;
2176
2177 if (rxretprd != rxretcsm)
2178 ace_rx_int(dev, rxretprd, rxretcsm);
2179
2180 txcsm = *ap->tx_csm;
2181 idx = ap->tx_ret_csm;
2182
2183 if (txcsm != idx) {
2184
2185
2186
2187
2188
2189
2190
2191 if (!tx_ring_full(ap, txcsm, ap->tx_prd))
2192 ace_tx_int(dev, txcsm, idx);
2193 }
2194
2195 evtcsm = readl(®s->EvtCsm);
2196 evtprd = *ap->evt_prd;
2197
2198 if (evtcsm != evtprd) {
2199 evtcsm = ace_handle_event(dev, evtcsm, evtprd);
2200 writel(evtcsm, ®s->EvtCsm);
2201 }
2202
2203
2204
2205
2206
2207 if (netif_running(dev)) {
2208 int cur_size;
2209 int run_tasklet = 0;
2210
2211 cur_size = atomic_read(&ap->cur_rx_bufs);
2212 if (cur_size < RX_LOW_STD_THRES) {
2213 if ((cur_size < RX_PANIC_STD_THRES) &&
2214 !test_and_set_bit(0, &ap->std_refill_busy)) {
2215#ifdef DEBUG
2216 printk("low on std buffers %i\n", cur_size);
2217#endif
2218 ace_load_std_rx_ring(ap,
2219 RX_RING_SIZE - cur_size);
2220 } else
2221 run_tasklet = 1;
2222 }
2223
2224 if (!ACE_IS_TIGON_I(ap)) {
2225 cur_size = atomic_read(&ap->cur_mini_bufs);
2226 if (cur_size < RX_LOW_MINI_THRES) {
2227 if ((cur_size < RX_PANIC_MINI_THRES) &&
2228 !test_and_set_bit(0,
2229 &ap->mini_refill_busy)) {
2230#ifdef DEBUG
2231 printk("low on mini buffers %i\n",
2232 cur_size);
2233#endif
2234 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
2235 } else
2236 run_tasklet = 1;
2237 }
2238 }
2239
2240 if (ap->jumbo) {
2241 cur_size = atomic_read(&ap->cur_jumbo_bufs);
2242 if (cur_size < RX_LOW_JUMBO_THRES) {
2243 if ((cur_size < RX_PANIC_JUMBO_THRES) &&
2244 !test_and_set_bit(0,
2245 &ap->jumbo_refill_busy)){
2246#ifdef DEBUG
2247 printk("low on jumbo buffers %i\n",
2248 cur_size);
2249#endif
2250 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
2251 } else
2252 run_tasklet = 1;
2253 }
2254 }
2255 if (run_tasklet && !ap->tasklet_pending) {
2256 ap->tasklet_pending = 1;
2257 tasklet_schedule(&ap->ace_tasklet);
2258 }
2259 }
2260
2261 return IRQ_HANDLED;
2262}
2263
2264
2265#if ACENIC_DO_VLAN
2266static void ace_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2267{
2268 struct ace_private *ap = netdev_priv(dev);
2269 unsigned long flags;
2270
2271 local_irq_save(flags);
2272 ace_mask_irq(dev);
2273
2274 ap->vlgrp = grp;
2275
2276 ace_unmask_irq(dev);
2277 local_irq_restore(flags);
2278}
2279#endif
2280
2281
2282static int ace_open(struct net_device *dev)
2283{
2284 struct ace_private *ap = netdev_priv(dev);
2285 struct ace_regs __iomem *regs = ap->regs;
2286 struct cmd cmd;
2287
2288 if (!(ap->fw_running)) {
2289 printk(KERN_WARNING "%s: Firmware not running!\n", dev->name);
2290 return -EBUSY;
2291 }
2292
2293 writel(dev->mtu + ETH_HLEN + 4, ®s->IfMtu);
2294
2295 cmd.evt = C_CLEAR_STATS;
2296 cmd.code = 0;
2297 cmd.idx = 0;
2298 ace_issue_cmd(regs, &cmd);
2299
2300 cmd.evt = C_HOST_STATE;
2301 cmd.code = C_C_STACK_UP;
2302 cmd.idx = 0;
2303 ace_issue_cmd(regs, &cmd);
2304
2305 if (ap->jumbo &&
2306 !test_and_set_bit(0, &ap->jumbo_refill_busy))
2307 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2308
2309 if (dev->flags & IFF_PROMISC) {
2310 cmd.evt = C_SET_PROMISC_MODE;
2311 cmd.code = C_C_PROMISC_ENABLE;
2312 cmd.idx = 0;
2313 ace_issue_cmd(regs, &cmd);
2314
2315 ap->promisc = 1;
2316 }else
2317 ap->promisc = 0;
2318 ap->mcast_all = 0;
2319
2320#if 0
2321 cmd.evt = C_LNK_NEGOTIATION;
2322 cmd.code = 0;
2323 cmd.idx = 0;
2324 ace_issue_cmd(regs, &cmd);
2325#endif
2326
2327 netif_start_queue(dev);
2328
2329
2330
2331
2332 tasklet_init(&ap->ace_tasklet, ace_tasklet, (unsigned long)dev);
2333 return 0;
2334}
2335
2336
2337static int ace_close(struct net_device *dev)
2338{
2339 struct ace_private *ap = netdev_priv(dev);
2340 struct ace_regs __iomem *regs = ap->regs;
2341 struct cmd cmd;
2342 unsigned long flags;
2343 short i;
2344
2345
2346
2347
2348
2349
2350 netif_stop_queue(dev);
2351
2352
2353 if (ap->promisc) {
2354 cmd.evt = C_SET_PROMISC_MODE;
2355 cmd.code = C_C_PROMISC_DISABLE;
2356 cmd.idx = 0;
2357 ace_issue_cmd(regs, &cmd);
2358 ap->promisc = 0;
2359 }
2360
2361 cmd.evt = C_HOST_STATE;
2362 cmd.code = C_C_STACK_DOWN;
2363 cmd.idx = 0;
2364 ace_issue_cmd(regs, &cmd);
2365
2366 tasklet_kill(&ap->ace_tasklet);
2367
2368
2369
2370
2371
2372
2373 local_irq_save(flags);
2374 ace_mask_irq(dev);
2375
2376 for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) {
2377 struct sk_buff *skb;
2378 struct tx_ring_info *info;
2379
2380 info = ap->skb->tx_skbuff + i;
2381 skb = info->skb;
2382
2383 if (dma_unmap_len(info, maplen)) {
2384 if (ACE_IS_TIGON_I(ap)) {
2385
2386 struct tx_desc __iomem *tx;
2387 tx = (__force struct tx_desc __iomem *) &ap->tx_ring[i];
2388 writel(0, &tx->addr.addrhi);
2389 writel(0, &tx->addr.addrlo);
2390 writel(0, &tx->flagsize);
2391 } else
2392 memset(ap->tx_ring + i, 0,
2393 sizeof(struct tx_desc));
2394 pci_unmap_page(ap->pdev, dma_unmap_addr(info, mapping),
2395 dma_unmap_len(info, maplen),
2396 PCI_DMA_TODEVICE);
2397 dma_unmap_len_set(info, maplen, 0);
2398 }
2399 if (skb) {
2400 dev_kfree_skb(skb);
2401 info->skb = NULL;
2402 }
2403 }
2404
2405 if (ap->jumbo) {
2406 cmd.evt = C_RESET_JUMBO_RNG;
2407 cmd.code = 0;
2408 cmd.idx = 0;
2409 ace_issue_cmd(regs, &cmd);
2410 }
2411
2412 ace_unmask_irq(dev);
2413 local_irq_restore(flags);
2414
2415 return 0;
2416}
2417
2418
2419static inline dma_addr_t
2420ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb,
2421 struct sk_buff *tail, u32 idx)
2422{
2423 dma_addr_t mapping;
2424 struct tx_ring_info *info;
2425
2426 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
2427 offset_in_page(skb->data),
2428 skb->len, PCI_DMA_TODEVICE);
2429
2430 info = ap->skb->tx_skbuff + idx;
2431 info->skb = tail;
2432 dma_unmap_addr_set(info, mapping, mapping);
2433 dma_unmap_len_set(info, maplen, skb->len);
2434 return mapping;
2435}
2436
2437
2438static inline void
2439ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr,
2440 u32 flagsize, u32 vlan_tag)
2441{
2442#if !USE_TX_COAL_NOW
2443 flagsize &= ~BD_FLG_COAL_NOW;
2444#endif
2445
2446 if (ACE_IS_TIGON_I(ap)) {
2447 struct tx_desc __iomem *io = (__force struct tx_desc __iomem *) desc;
2448 writel(addr >> 32, &io->addr.addrhi);
2449 writel(addr & 0xffffffff, &io->addr.addrlo);
2450 writel(flagsize, &io->flagsize);
2451#if ACENIC_DO_VLAN
2452 writel(vlan_tag, &io->vlanres);
2453#endif
2454 } else {
2455 desc->addr.addrhi = addr >> 32;
2456 desc->addr.addrlo = addr;
2457 desc->flagsize = flagsize;
2458#if ACENIC_DO_VLAN
2459 desc->vlanres = vlan_tag;
2460#endif
2461 }
2462}
2463
2464
2465static netdev_tx_t ace_start_xmit(struct sk_buff *skb,
2466 struct net_device *dev)
2467{
2468 struct ace_private *ap = netdev_priv(dev);
2469 struct ace_regs __iomem *regs = ap->regs;
2470 struct tx_desc *desc;
2471 u32 idx, flagsize;
2472 unsigned long maxjiff = jiffies + 3*HZ;
2473
2474restart:
2475 idx = ap->tx_prd;
2476
2477 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2478 goto overflow;
2479
2480 if (!skb_shinfo(skb)->nr_frags) {
2481 dma_addr_t mapping;
2482 u32 vlan_tag = 0;
2483
2484 mapping = ace_map_tx_skb(ap, skb, skb, idx);
2485 flagsize = (skb->len << 16) | (BD_FLG_END);
2486 if (skb->ip_summed == CHECKSUM_PARTIAL)
2487 flagsize |= BD_FLG_TCP_UDP_SUM;
2488#if ACENIC_DO_VLAN
2489 if (vlan_tx_tag_present(skb)) {
2490 flagsize |= BD_FLG_VLAN_TAG;
2491 vlan_tag = vlan_tx_tag_get(skb);
2492 }
2493#endif
2494 desc = ap->tx_ring + idx;
2495 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2496
2497
2498 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2499 flagsize |= BD_FLG_COAL_NOW;
2500
2501 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2502 } else {
2503 dma_addr_t mapping;
2504 u32 vlan_tag = 0;
2505 int i, len = 0;
2506
2507 mapping = ace_map_tx_skb(ap, skb, NULL, idx);
2508 flagsize = (skb_headlen(skb) << 16);
2509 if (skb->ip_summed == CHECKSUM_PARTIAL)
2510 flagsize |= BD_FLG_TCP_UDP_SUM;
2511#if ACENIC_DO_VLAN
2512 if (vlan_tx_tag_present(skb)) {
2513 flagsize |= BD_FLG_VLAN_TAG;
2514 vlan_tag = vlan_tx_tag_get(skb);
2515 }
2516#endif
2517
2518 ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag);
2519
2520 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2521
2522 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2523 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2524 struct tx_ring_info *info;
2525
2526 len += frag->size;
2527 info = ap->skb->tx_skbuff + idx;
2528 desc = ap->tx_ring + idx;
2529
2530 mapping = pci_map_page(ap->pdev, frag->page,
2531 frag->page_offset, frag->size,
2532 PCI_DMA_TODEVICE);
2533
2534 flagsize = (frag->size << 16);
2535 if (skb->ip_summed == CHECKSUM_PARTIAL)
2536 flagsize |= BD_FLG_TCP_UDP_SUM;
2537 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2538
2539 if (i == skb_shinfo(skb)->nr_frags - 1) {
2540 flagsize |= BD_FLG_END;
2541 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2542 flagsize |= BD_FLG_COAL_NOW;
2543
2544
2545
2546
2547
2548 info->skb = skb;
2549 } else {
2550 info->skb = NULL;
2551 }
2552 dma_unmap_addr_set(info, mapping, mapping);
2553 dma_unmap_len_set(info, maplen, frag->size);
2554 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2555 }
2556 }
2557
2558 wmb();
2559 ap->tx_prd = idx;
2560 ace_set_txprd(regs, ap, idx);
2561
2562 if (flagsize & BD_FLG_COAL_NOW) {
2563 netif_stop_queue(dev);
2564
2565
2566
2567
2568
2569
2570
2571 if (!tx_ring_full(ap, ap->tx_ret_csm, idx))
2572 netif_wake_queue(dev);
2573 }
2574
2575 return NETDEV_TX_OK;
2576
2577overflow:
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594 if (time_before(jiffies, maxjiff)) {
2595 barrier();
2596 cpu_relax();
2597 goto restart;
2598 }
2599
2600
2601 printk(KERN_WARNING "%s: Transmit ring stuck full\n", dev->name);
2602 return NETDEV_TX_BUSY;
2603}
2604
2605
2606static int ace_change_mtu(struct net_device *dev, int new_mtu)
2607{
2608 struct ace_private *ap = netdev_priv(dev);
2609 struct ace_regs __iomem *regs = ap->regs;
2610
2611 if (new_mtu > ACE_JUMBO_MTU)
2612 return -EINVAL;
2613
2614 writel(new_mtu + ETH_HLEN + 4, ®s->IfMtu);
2615 dev->mtu = new_mtu;
2616
2617 if (new_mtu > ACE_STD_MTU) {
2618 if (!(ap->jumbo)) {
2619 printk(KERN_INFO "%s: Enabling Jumbo frame "
2620 "support\n", dev->name);
2621 ap->jumbo = 1;
2622 if (!test_and_set_bit(0, &ap->jumbo_refill_busy))
2623 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2624 ace_set_rxtx_parms(dev, 1);
2625 }
2626 } else {
2627 while (test_and_set_bit(0, &ap->jumbo_refill_busy));
2628 ace_sync_irq(dev->irq);
2629 ace_set_rxtx_parms(dev, 0);
2630 if (ap->jumbo) {
2631 struct cmd cmd;
2632
2633 cmd.evt = C_RESET_JUMBO_RNG;
2634 cmd.code = 0;
2635 cmd.idx = 0;
2636 ace_issue_cmd(regs, &cmd);
2637 }
2638 }
2639
2640 return 0;
2641}
2642
2643static int ace_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2644{
2645 struct ace_private *ap = netdev_priv(dev);
2646 struct ace_regs __iomem *regs = ap->regs;
2647 u32 link;
2648
2649 memset(ecmd, 0, sizeof(struct ethtool_cmd));
2650 ecmd->supported =
2651 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2652 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2653 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full |
2654 SUPPORTED_Autoneg | SUPPORTED_FIBRE);
2655
2656 ecmd->port = PORT_FIBRE;
2657 ecmd->transceiver = XCVR_INTERNAL;
2658
2659 link = readl(®s->GigLnkState);
2660 if (link & LNK_1000MB)
2661 ecmd->speed = SPEED_1000;
2662 else {
2663 link = readl(®s->FastLnkState);
2664 if (link & LNK_100MB)
2665 ecmd->speed = SPEED_100;
2666 else if (link & LNK_10MB)
2667 ecmd->speed = SPEED_10;
2668 else
2669 ecmd->speed = 0;
2670 }
2671 if (link & LNK_FULL_DUPLEX)
2672 ecmd->duplex = DUPLEX_FULL;
2673 else
2674 ecmd->duplex = DUPLEX_HALF;
2675
2676 if (link & LNK_NEGOTIATE)
2677 ecmd->autoneg = AUTONEG_ENABLE;
2678 else
2679 ecmd->autoneg = AUTONEG_DISABLE;
2680
2681#if 0
2682
2683
2684
2685 ecmd->trace = readl(®s->TuneTrace);
2686
2687 ecmd->txcoal = readl(®s->TuneTxCoalTicks);
2688 ecmd->rxcoal = readl(®s->TuneRxCoalTicks);
2689#endif
2690 ecmd->maxtxpkt = readl(®s->TuneMaxTxDesc);
2691 ecmd->maxrxpkt = readl(®s->TuneMaxRxDesc);
2692
2693 return 0;
2694}
2695
2696static int ace_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2697{
2698 struct ace_private *ap = netdev_priv(dev);
2699 struct ace_regs __iomem *regs = ap->regs;
2700 u32 link, speed;
2701
2702 link = readl(®s->GigLnkState);
2703 if (link & LNK_1000MB)
2704 speed = SPEED_1000;
2705 else {
2706 link = readl(®s->FastLnkState);
2707 if (link & LNK_100MB)
2708 speed = SPEED_100;
2709 else if (link & LNK_10MB)
2710 speed = SPEED_10;
2711 else
2712 speed = SPEED_100;
2713 }
2714
2715 link = LNK_ENABLE | LNK_1000MB | LNK_100MB | LNK_10MB |
2716 LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL;
2717 if (!ACE_IS_TIGON_I(ap))
2718 link |= LNK_TX_FLOW_CTL_Y;
2719 if (ecmd->autoneg == AUTONEG_ENABLE)
2720 link |= LNK_NEGOTIATE;
2721 if (ecmd->speed != speed) {
2722 link &= ~(LNK_1000MB | LNK_100MB | LNK_10MB);
2723 switch (speed) {
2724 case SPEED_1000:
2725 link |= LNK_1000MB;
2726 break;
2727 case SPEED_100:
2728 link |= LNK_100MB;
2729 break;
2730 case SPEED_10:
2731 link |= LNK_10MB;
2732 break;
2733 }
2734 }
2735
2736 if (ecmd->duplex == DUPLEX_FULL)
2737 link |= LNK_FULL_DUPLEX;
2738
2739 if (link != ap->link) {
2740 struct cmd cmd;
2741 printk(KERN_INFO "%s: Renegotiating link state\n",
2742 dev->name);
2743
2744 ap->link = link;
2745 writel(link, ®s->TuneLink);
2746 if (!ACE_IS_TIGON_I(ap))
2747 writel(link, ®s->TuneFastLink);
2748 wmb();
2749
2750 cmd.evt = C_LNK_NEGOTIATION;
2751 cmd.code = 0;
2752 cmd.idx = 0;
2753 ace_issue_cmd(regs, &cmd);
2754 }
2755 return 0;
2756}
2757
2758static void ace_get_drvinfo(struct net_device *dev,
2759 struct ethtool_drvinfo *info)
2760{
2761 struct ace_private *ap = netdev_priv(dev);
2762
2763 strlcpy(info->driver, "acenic", sizeof(info->driver));
2764 snprintf(info->version, sizeof(info->version), "%i.%i.%i",
2765 ap->firmware_major, ap->firmware_minor,
2766 ap->firmware_fix);
2767
2768 if (ap->pdev)
2769 strlcpy(info->bus_info, pci_name(ap->pdev),
2770 sizeof(info->bus_info));
2771
2772}
2773
2774
2775
2776
2777static int ace_set_mac_addr(struct net_device *dev, void *p)
2778{
2779 struct ace_private *ap = netdev_priv(dev);
2780 struct ace_regs __iomem *regs = ap->regs;
2781 struct sockaddr *addr=p;
2782 u8 *da;
2783 struct cmd cmd;
2784
2785 if(netif_running(dev))
2786 return -EBUSY;
2787
2788 memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
2789
2790 da = (u8 *)dev->dev_addr;
2791
2792 writel(da[0] << 8 | da[1], ®s->MacAddrHi);
2793 writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5],
2794 ®s->MacAddrLo);
2795
2796 cmd.evt = C_SET_MAC_ADDR;
2797 cmd.code = 0;
2798 cmd.idx = 0;
2799 ace_issue_cmd(regs, &cmd);
2800
2801 return 0;
2802}
2803
2804
2805static void ace_set_multicast_list(struct net_device *dev)
2806{
2807 struct ace_private *ap = netdev_priv(dev);
2808 struct ace_regs __iomem *regs = ap->regs;
2809 struct cmd cmd;
2810
2811 if ((dev->flags & IFF_ALLMULTI) && !(ap->mcast_all)) {
2812 cmd.evt = C_SET_MULTICAST_MODE;
2813 cmd.code = C_C_MCAST_ENABLE;
2814 cmd.idx = 0;
2815 ace_issue_cmd(regs, &cmd);
2816 ap->mcast_all = 1;
2817 } else if (ap->mcast_all) {
2818 cmd.evt = C_SET_MULTICAST_MODE;
2819 cmd.code = C_C_MCAST_DISABLE;
2820 cmd.idx = 0;
2821 ace_issue_cmd(regs, &cmd);
2822 ap->mcast_all = 0;
2823 }
2824
2825 if ((dev->flags & IFF_PROMISC) && !(ap->promisc)) {
2826 cmd.evt = C_SET_PROMISC_MODE;
2827 cmd.code = C_C_PROMISC_ENABLE;
2828 cmd.idx = 0;
2829 ace_issue_cmd(regs, &cmd);
2830 ap->promisc = 1;
2831 }else if (!(dev->flags & IFF_PROMISC) && (ap->promisc)) {
2832 cmd.evt = C_SET_PROMISC_MODE;
2833 cmd.code = C_C_PROMISC_DISABLE;
2834 cmd.idx = 0;
2835 ace_issue_cmd(regs, &cmd);
2836 ap->promisc = 0;
2837 }
2838
2839
2840
2841
2842
2843
2844
2845 if (!netdev_mc_empty(dev) && !ap->mcast_all) {
2846 cmd.evt = C_SET_MULTICAST_MODE;
2847 cmd.code = C_C_MCAST_ENABLE;
2848 cmd.idx = 0;
2849 ace_issue_cmd(regs, &cmd);
2850 }else if (!ap->mcast_all) {
2851 cmd.evt = C_SET_MULTICAST_MODE;
2852 cmd.code = C_C_MCAST_DISABLE;
2853 cmd.idx = 0;
2854 ace_issue_cmd(regs, &cmd);
2855 }
2856}
2857
2858
2859static struct net_device_stats *ace_get_stats(struct net_device *dev)
2860{
2861 struct ace_private *ap = netdev_priv(dev);
2862 struct ace_mac_stats __iomem *mac_stats =
2863 (struct ace_mac_stats __iomem *)ap->regs->Stats;
2864
2865 dev->stats.rx_missed_errors = readl(&mac_stats->drop_space);
2866 dev->stats.multicast = readl(&mac_stats->kept_mc);
2867 dev->stats.collisions = readl(&mac_stats->coll);
2868
2869 return &dev->stats;
2870}
2871
2872
2873static void __devinit ace_copy(struct ace_regs __iomem *regs, const __be32 *src,
2874 u32 dest, int size)
2875{
2876 void __iomem *tdest;
2877 short tsize, i;
2878
2879 if (size <= 0)
2880 return;
2881
2882 while (size > 0) {
2883 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2884 min_t(u32, size, ACE_WINDOW_SIZE));
2885 tdest = (void __iomem *) ®s->Window +
2886 (dest & (ACE_WINDOW_SIZE - 1));
2887 writel(dest & ~(ACE_WINDOW_SIZE - 1), ®s->WinBase);
2888 for (i = 0; i < (tsize / 4); i++) {
2889
2890 writel(be32_to_cpup(src), tdest);
2891 src++;
2892 tdest += 4;
2893 dest += 4;
2894 size -= 4;
2895 }
2896 }
2897}
2898
2899
2900static void __devinit ace_clear(struct ace_regs __iomem *regs, u32 dest, int size)
2901{
2902 void __iomem *tdest;
2903 short tsize = 0, i;
2904
2905 if (size <= 0)
2906 return;
2907
2908 while (size > 0) {
2909 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2910 min_t(u32, size, ACE_WINDOW_SIZE));
2911 tdest = (void __iomem *) ®s->Window +
2912 (dest & (ACE_WINDOW_SIZE - 1));
2913 writel(dest & ~(ACE_WINDOW_SIZE - 1), ®s->WinBase);
2914
2915 for (i = 0; i < (tsize / 4); i++) {
2916 writel(0, tdest + i*4);
2917 }
2918
2919 dest += tsize;
2920 size -= tsize;
2921 }
2922}
2923
2924
2925
2926
2927
2928
2929
2930
2931static int __devinit ace_load_firmware(struct net_device *dev)
2932{
2933 const struct firmware *fw;
2934 const char *fw_name = "acenic/tg2.bin";
2935 struct ace_private *ap = netdev_priv(dev);
2936 struct ace_regs __iomem *regs = ap->regs;
2937 const __be32 *fw_data;
2938 u32 load_addr;
2939 int ret;
2940
2941 if (!(readl(®s->CpuCtrl) & CPU_HALTED)) {
2942 printk(KERN_ERR "%s: trying to download firmware while the "
2943 "CPU is running!\n", ap->name);
2944 return -EFAULT;
2945 }
2946
2947 if (ACE_IS_TIGON_I(ap))
2948 fw_name = "acenic/tg1.bin";
2949
2950 ret = request_firmware(&fw, fw_name, &ap->pdev->dev);
2951 if (ret) {
2952 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
2953 ap->name, fw_name);
2954 return ret;
2955 }
2956
2957 fw_data = (void *)fw->data;
2958
2959
2960
2961
2962
2963
2964 ap->firmware_major = fw->data[0];
2965 ap->firmware_minor = fw->data[1];
2966 ap->firmware_fix = fw->data[2];
2967
2968 ap->firmware_start = be32_to_cpu(fw_data[1]);
2969 if (ap->firmware_start < 0x4000 || ap->firmware_start >= 0x80000) {
2970 printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n",
2971 ap->name, ap->firmware_start, fw_name);
2972 ret = -EINVAL;
2973 goto out;
2974 }
2975
2976 load_addr = be32_to_cpu(fw_data[2]);
2977 if (load_addr < 0x4000 || load_addr >= 0x80000) {
2978 printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n",
2979 ap->name, load_addr, fw_name);
2980 ret = -EINVAL;
2981 goto out;
2982 }
2983
2984
2985
2986
2987
2988 ace_clear(regs, 0x2000, 0x80000-0x2000);
2989 ace_copy(regs, &fw_data[3], load_addr, fw->size-12);
2990 out:
2991 release_firmware(fw);
2992 return ret;
2993}
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011static void __devinit eeprom_start(struct ace_regs __iomem *regs)
3012{
3013 u32 local;
3014
3015 readl(®s->LocalCtrl);
3016 udelay(ACE_SHORT_DELAY);
3017 local = readl(®s->LocalCtrl);
3018 local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE;
3019 writel(local, ®s->LocalCtrl);
3020 readl(®s->LocalCtrl);
3021 mb();
3022 udelay(ACE_SHORT_DELAY);
3023 local |= EEPROM_CLK_OUT;
3024 writel(local, ®s->LocalCtrl);
3025 readl(®s->LocalCtrl);
3026 mb();
3027 udelay(ACE_SHORT_DELAY);
3028 local &= ~EEPROM_DATA_OUT;
3029 writel(local, ®s->LocalCtrl);
3030 readl(®s->LocalCtrl);
3031 mb();
3032 udelay(ACE_SHORT_DELAY);
3033 local &= ~EEPROM_CLK_OUT;
3034 writel(local, ®s->LocalCtrl);
3035 readl(®s->LocalCtrl);
3036 mb();
3037}
3038
3039
3040static void __devinit eeprom_prep(struct ace_regs __iomem *regs, u8 magic)
3041{
3042 short i;
3043 u32 local;
3044
3045 udelay(ACE_SHORT_DELAY);
3046 local = readl(®s->LocalCtrl);
3047 local &= ~EEPROM_DATA_OUT;
3048 local |= EEPROM_WRITE_ENABLE;
3049 writel(local, ®s->LocalCtrl);
3050 readl(®s->LocalCtrl);
3051 mb();
3052
3053 for (i = 0; i < 8; i++, magic <<= 1) {
3054 udelay(ACE_SHORT_DELAY);
3055 if (magic & 0x80)
3056 local |= EEPROM_DATA_OUT;
3057 else
3058 local &= ~EEPROM_DATA_OUT;
3059 writel(local, ®s->LocalCtrl);
3060 readl(®s->LocalCtrl);
3061 mb();
3062
3063 udelay(ACE_SHORT_DELAY);
3064 local |= EEPROM_CLK_OUT;
3065 writel(local, ®s->LocalCtrl);
3066 readl(®s->LocalCtrl);
3067 mb();
3068 udelay(ACE_SHORT_DELAY);
3069 local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT);
3070 writel(local, ®s->LocalCtrl);
3071 readl(®s->LocalCtrl);
3072 mb();
3073 }
3074}
3075
3076
3077static int __devinit eeprom_check_ack(struct ace_regs __iomem *regs)
3078{
3079 int state;
3080 u32 local;
3081
3082 local = readl(®s->LocalCtrl);
3083 local &= ~EEPROM_WRITE_ENABLE;
3084 writel(local, ®s->LocalCtrl);
3085 readl(®s->LocalCtrl);
3086 mb();
3087 udelay(ACE_LONG_DELAY);
3088 local |= EEPROM_CLK_OUT;
3089 writel(local, ®s->LocalCtrl);
3090 readl(®s->LocalCtrl);
3091 mb();
3092 udelay(ACE_SHORT_DELAY);
3093
3094 state = (readl(®s->LocalCtrl) & EEPROM_DATA_IN) != 0;
3095 udelay(ACE_SHORT_DELAY);
3096 mb();
3097 writel(readl(®s->LocalCtrl) & ~EEPROM_CLK_OUT, ®s->LocalCtrl);
3098 readl(®s->LocalCtrl);
3099 mb();
3100
3101 return state;
3102}
3103
3104
3105static void __devinit eeprom_stop(struct ace_regs __iomem *regs)
3106{
3107 u32 local;
3108
3109 udelay(ACE_SHORT_DELAY);
3110 local = readl(®s->LocalCtrl);
3111 local |= EEPROM_WRITE_ENABLE;
3112 writel(local, ®s->LocalCtrl);
3113 readl(®s->LocalCtrl);
3114 mb();
3115 udelay(ACE_SHORT_DELAY);
3116 local &= ~EEPROM_DATA_OUT;
3117 writel(local, ®s->LocalCtrl);
3118 readl(®s->LocalCtrl);
3119 mb();
3120 udelay(ACE_SHORT_DELAY);
3121 local |= EEPROM_CLK_OUT;
3122 writel(local, ®s->LocalCtrl);
3123 readl(®s->LocalCtrl);
3124 mb();
3125 udelay(ACE_SHORT_DELAY);
3126 local |= EEPROM_DATA_OUT;
3127 writel(local, ®s->LocalCtrl);
3128 readl(®s->LocalCtrl);
3129 mb();
3130 udelay(ACE_LONG_DELAY);
3131 local &= ~EEPROM_CLK_OUT;
3132 writel(local, ®s->LocalCtrl);
3133 mb();
3134}
3135
3136
3137
3138
3139
3140static int __devinit read_eeprom_byte(struct net_device *dev,
3141 unsigned long offset)
3142{
3143 struct ace_private *ap = netdev_priv(dev);
3144 struct ace_regs __iomem *regs = ap->regs;
3145 unsigned long flags;
3146 u32 local;
3147 int result = 0;
3148 short i;
3149
3150
3151
3152
3153
3154 local_irq_save(flags);
3155
3156 eeprom_start(regs);
3157
3158 eeprom_prep(regs, EEPROM_WRITE_SELECT);
3159 if (eeprom_check_ack(regs)) {
3160 local_irq_restore(flags);
3161 printk(KERN_ERR "%s: Unable to sync eeprom\n", ap->name);
3162 result = -EIO;
3163 goto eeprom_read_error;
3164 }
3165
3166 eeprom_prep(regs, (offset >> 8) & 0xff);
3167 if (eeprom_check_ack(regs)) {
3168 local_irq_restore(flags);
3169 printk(KERN_ERR "%s: Unable to set address byte 0\n",
3170 ap->name);
3171 result = -EIO;
3172 goto eeprom_read_error;
3173 }
3174
3175 eeprom_prep(regs, offset & 0xff);
3176 if (eeprom_check_ack(regs)) {
3177 local_irq_restore(flags);
3178 printk(KERN_ERR "%s: Unable to set address byte 1\n",
3179 ap->name);
3180 result = -EIO;
3181 goto eeprom_read_error;
3182 }
3183
3184 eeprom_start(regs);
3185 eeprom_prep(regs, EEPROM_READ_SELECT);
3186 if (eeprom_check_ack(regs)) {
3187 local_irq_restore(flags);
3188 printk(KERN_ERR "%s: Unable to set READ_SELECT\n",
3189 ap->name);
3190 result = -EIO;
3191 goto eeprom_read_error;
3192 }
3193
3194 for (i = 0; i < 8; i++) {
3195 local = readl(®s->LocalCtrl);
3196 local &= ~EEPROM_WRITE_ENABLE;
3197 writel(local, ®s->LocalCtrl);
3198 readl(®s->LocalCtrl);
3199 udelay(ACE_LONG_DELAY);
3200 mb();
3201 local |= EEPROM_CLK_OUT;
3202 writel(local, ®s->LocalCtrl);
3203 readl(®s->LocalCtrl);
3204 mb();
3205 udelay(ACE_SHORT_DELAY);
3206
3207 result = (result << 1) |
3208 ((readl(®s->LocalCtrl) & EEPROM_DATA_IN) != 0);
3209 udelay(ACE_SHORT_DELAY);
3210 mb();
3211 local = readl(®s->LocalCtrl);
3212 local &= ~EEPROM_CLK_OUT;
3213 writel(local, ®s->LocalCtrl);
3214 readl(®s->LocalCtrl);
3215 udelay(ACE_SHORT_DELAY);
3216 mb();
3217 if (i == 7) {
3218 local |= EEPROM_WRITE_ENABLE;
3219 writel(local, ®s->LocalCtrl);
3220 readl(®s->LocalCtrl);
3221 mb();
3222 udelay(ACE_SHORT_DELAY);
3223 }
3224 }
3225
3226 local |= EEPROM_DATA_OUT;
3227 writel(local, ®s->LocalCtrl);
3228 readl(®s->LocalCtrl);
3229 mb();
3230 udelay(ACE_SHORT_DELAY);
3231 writel(readl(®s->LocalCtrl) | EEPROM_CLK_OUT, ®s->LocalCtrl);
3232 readl(®s->LocalCtrl);
3233 udelay(ACE_LONG_DELAY);
3234 writel(readl(®s->LocalCtrl) & ~EEPROM_CLK_OUT, ®s->LocalCtrl);
3235 readl(®s->LocalCtrl);
3236 mb();
3237 udelay(ACE_SHORT_DELAY);
3238 eeprom_stop(regs);
3239
3240 local_irq_restore(flags);
3241 out:
3242 return result;
3243
3244 eeprom_read_error:
3245 printk(KERN_ERR "%s: Unable to read eeprom byte 0x%02lx\n",
3246 ap->name, offset);
3247 goto out;
3248}
3249