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9#ifndef BNX2X_HSI_H
10#define BNX2X_HSI_H
11
12#include "bnx2x_fw_defs.h"
13
14struct license_key {
15 u32 reserved[6];
16
17#if defined(__BIG_ENDIAN)
18 u16 max_iscsi_init_conn;
19 u16 max_iscsi_trgt_conn;
20#elif defined(__LITTLE_ENDIAN)
21 u16 max_iscsi_trgt_conn;
22 u16 max_iscsi_init_conn;
23#endif
24
25 u32 reserved_a[6];
26};
27
28
29#define PORT_0 0
30#define PORT_1 1
31#define PORT_MAX 2
32
33
34
35
36struct shared_hw_cfg {
37
38 u8 part_num[16];
39
40 u32 config;
41#define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
42#define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
43#define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
44#define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
45#define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
46
47#define SHARED_HW_CFG_PORT_SWAP 0x00000004
48
49#define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
50
51#define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
52#define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
53
54
55#define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
56#define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
57#define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
58#define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
59
60
61#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
62
63
64#define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
65
66
67#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
68
69#define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
70#define SHARED_HW_CFG_LED_MODE_SHIFT 16
71#define SHARED_HW_CFG_LED_MAC1 0x00000000
72#define SHARED_HW_CFG_LED_PHY1 0x00010000
73#define SHARED_HW_CFG_LED_PHY2 0x00020000
74#define SHARED_HW_CFG_LED_PHY3 0x00030000
75#define SHARED_HW_CFG_LED_MAC2 0x00040000
76#define SHARED_HW_CFG_LED_PHY4 0x00050000
77#define SHARED_HW_CFG_LED_PHY5 0x00060000
78#define SHARED_HW_CFG_LED_PHY6 0x00070000
79#define SHARED_HW_CFG_LED_MAC3 0x00080000
80#define SHARED_HW_CFG_LED_PHY7 0x00090000
81#define SHARED_HW_CFG_LED_PHY9 0x000a0000
82#define SHARED_HW_CFG_LED_PHY11 0x000b0000
83#define SHARED_HW_CFG_LED_MAC4 0x000c0000
84#define SHARED_HW_CFG_LED_PHY8 0x000d0000
85#define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000
86
87
88#define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
89#define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
90#define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
91#define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
92#define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
93#define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
94#define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
95#define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
96
97 u32 config2;
98
99#define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
100#define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
101
102#define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
103
104
105
106#define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
107#define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
108
109#define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
110#define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
111
112#define SHARED_HW_CFG_HIDE_PORT1 0x00002000
113
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121
122
123#define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
124#define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19
125#define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
126#define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
127#define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
128
129
130#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000
131#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26
132#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000
133#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000
134#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000
135#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000
136#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000
137
138
139#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000
140#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29
141#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000
142#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000
143#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000
144#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000
145#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000
146 u32 power_dissipated;
147#define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
148#define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
149
150#define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000
151#define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16
152#define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000
153#define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000
154#define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000
155#define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000
156
157 u32 ump_nc_si_config;
158#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
159#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
160#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
161#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
162#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
163#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
164
165#define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
166#define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
167
168#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
169#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
170#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
171#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
172
173 u32 board;
174#define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000
175#define SHARED_HW_CFG_BOARD_REV_SHIFT 16
176
177#define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000
178#define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24
179
180#define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000
181#define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28
182
183 u32 reserved;
184
185};
186
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188
189
190
191struct port_hw_cfg {
192
193 u32 pci_id;
194#define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
195#define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
196
197 u32 pci_sub_id;
198#define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
199#define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
200
201 u32 power_dissipated;
202#define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
203#define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
204#define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
205#define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
206#define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
207#define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
208#define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
209#define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
210
211 u32 power_consumed;
212#define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
213#define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
214#define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
215#define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
216#define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
217#define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
218#define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
219#define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
220
221 u32 mac_upper;
222#define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
223#define PORT_HW_CFG_UPPERMAC_SHIFT 0
224 u32 mac_lower;
225
226 u32 iscsi_mac_upper;
227 u32 iscsi_mac_lower;
228
229 u32 rdma_mac_upper;
230 u32 rdma_mac_lower;
231
232 u32 serdes_config;
233#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF
234#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
235
236#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000
237#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
238
239
240 u32 Reserved0[16];
241
242
243 u16 xgxs_config_rx[4];
244
245 u16 xgxs_config_tx[4];
246
247 u32 Reserved1[56];
248 u32 default_cfg;
249
250#define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000
251#define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20
252#define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000
253#define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000
254
255 u32 speed_capability_mask2;
256#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
257#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
258#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
259#define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002
260#define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004
261#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
262#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
263#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020
264#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040
265#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_12G 0x00000080
266#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_12_DOT_5G 0x00000100
267#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_13G 0x00000200
268#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_15G 0x00000400
269#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_16G 0x00000800
270
271#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000
272#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16
273#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000
274#define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000
275#define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000
276#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000
277#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000
278#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000
279#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000
280#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_12G 0x00800000
281#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_12_DOT_5G 0x01000000
282#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_13G 0x02000000
283#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_15G 0x04000000
284#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_16G 0x08000000
285
286
287
288
289
290 u32 multi_phy_config;
291#define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007
292#define PORT_HW_CFG_PHY_SELECTION_SHIFT 0
293#define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000
294#define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001
295#define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002
296#define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
297#define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
298
299
300
301#define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008
302#define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3
303#define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000
304#define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008
305
306
307
308 u32 external_phy_config2;
309#define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF
310#define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0
311
312
313#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00
314#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8
315#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000
316#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100
317#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200
318#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300
319#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400
320#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500
321#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600
322#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700
323#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800
324#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900
325#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00
326#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00
327#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00
328#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00
329#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
330#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
331
332
333
334 u16 xgxs_config2_rx[4];
335 u16 xgxs_config2_tx[4];
336
337 u32 lane_config;
338#define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
339#define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
340
341#define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
342#define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
343#define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
344#define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
345#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
346#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
347
348#define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
349
350#define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
351
352#define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
353
354#define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
355
356#define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000
357#define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000
358#define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000
359
360 u32 external_phy_config;
361#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
362#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
363#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
364#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
365#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
366
367#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
368#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
369
370#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
371#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
372#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
373#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
374#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
375#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
376#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
377#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
378#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
379#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
380#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
381#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
382#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
383#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
384#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
385#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
386
387#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
388#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
389
390 u32 speed_capability_mask;
391#define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
392#define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
393#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
394#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
395#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
396#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
397#define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
398#define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
399#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
400#define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G 0x00800000
401#define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G 0x01000000
402#define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G 0x02000000
403#define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G 0x04000000
404#define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G 0x08000000
405#define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
406
407#define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
408#define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
409#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
410#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
411#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
412#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
413#define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
414#define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
415#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
416#define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G 0x00000080
417#define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G 0x00000100
418#define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G 0x00000200
419#define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G 0x00000400
420#define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G 0x00000800
421#define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
422
423 u32 reserved[2];
424
425};
426
427
428
429
430
431struct shared_feat_cfg {
432
433 u32 config;
434#define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
435
436
437
438#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED 0x00000000
439#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED 0x00000002
440
441#define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700
442#define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8
443#define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000
444#define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100
445#define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
446#define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
447
448};
449
450
451
452
453
454struct port_feat_cfg {
455
456 u32 config;
457#define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
458#define PORT_FEATURE_BAR1_SIZE_SHIFT 0
459#define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
460#define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
461#define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
462#define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
463#define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
464#define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
465#define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
466#define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
467#define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
468#define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
469#define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
470#define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
471#define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
472#define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
473#define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
474#define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
475#define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
476#define PORT_FEATURE_BAR2_SIZE_SHIFT 4
477#define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
478#define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
479#define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
480#define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
481#define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
482#define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
483#define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
484#define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
485#define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
486#define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
487#define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
488#define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
489#define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
490#define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
491#define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
492#define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
493#define PORT_FEATURE_EN_SIZE_MASK 0x07000000
494#define PORT_FEATURE_EN_SIZE_SHIFT 24
495#define PORT_FEATURE_WOL_ENABLED 0x01000000
496#define PORT_FEATURE_MBA_ENABLED 0x02000000
497#define PORT_FEATURE_MFW_ENABLED 0x04000000
498
499
500
501
502#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000
503#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29
504#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT 0x00000000
505#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER 0x20000000
506#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000
507#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000
508
509
510 u32 wol_config;
511
512#define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
513#define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
514#define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
515#define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
516#define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
517#define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
518#define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
519#define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
520#define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
521
522 u32 mba_config;
523#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000003
524#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
525#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
526#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
527#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
528#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
529#define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
530#define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
531#define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
532#define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
533#define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
534#define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
535#define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
536#define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
537#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
538#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
539#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
540#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
541#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
542#define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
543#define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
544#define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
545#define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
546#define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
547#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
548#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
549#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
550#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
551#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
552#define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
553#define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
554#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
555#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
556#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
557#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
558#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
559#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
560#define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
561#define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
562#define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
563#define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
564#define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
565#define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
566#define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
567#define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
568#define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
569#define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
570#define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4 0x20000000
571#define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR 0x24000000
572#define PORT_FEATURE_MBA_LINK_SPEED_12GBPS 0x28000000
573#define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS 0x2c000000
574#define PORT_FEATURE_MBA_LINK_SPEED_13GBPS 0x30000000
575#define PORT_FEATURE_MBA_LINK_SPEED_15GBPS 0x34000000
576#define PORT_FEATURE_MBA_LINK_SPEED_16GBPS 0x38000000
577
578 u32 bmc_config;
579#define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
580#define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
581
582 u32 mba_vlan_cfg;
583#define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
584#define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
585#define PORT_FEATURE_MBA_VLAN_EN 0x00010000
586
587 u32 resource_cfg;
588#define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
589#define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
590#define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
591#define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
592#define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
593
594 u32 smbus_config;
595
596#define PORT_FEATURE_SMBUS_EN 0x00000001
597#define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
598#define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
599
600 u32 reserved1;
601
602 u32 link_config;
603#define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
604#define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
605
606#define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
607
608#define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
609#define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
610#define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
611
612#define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
613#define PORT_FEATURE_LINK_SPEED_SHIFT 16
614#define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
615#define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
616#define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
617#define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
618#define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
619#define PORT_FEATURE_LINK_SPEED_1G 0x00050000
620#define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
621#define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
622#define PORT_FEATURE_LINK_SPEED_10G_KX4 0x00080000
623#define PORT_FEATURE_LINK_SPEED_10G_KR 0x00090000
624#define PORT_FEATURE_LINK_SPEED_12G 0x000a0000
625#define PORT_FEATURE_LINK_SPEED_12_5G 0x000b0000
626#define PORT_FEATURE_LINK_SPEED_13G 0x000c0000
627#define PORT_FEATURE_LINK_SPEED_15G 0x000d0000
628#define PORT_FEATURE_LINK_SPEED_16G 0x000e0000
629
630#define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
631#define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
632#define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
633#define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
634#define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
635#define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
636#define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
637
638
639
640 u32 mfw_wol_link_cfg;
641
642
643 u32 link_config2;
644
645
646
647 u32 mfw_wol_link_cfg2;
648
649 u32 Reserved2[17];
650
651};
652
653
654
655
656
657struct shm_dev_info {
658
659 u32 bc_rev;
660
661 struct shared_hw_cfg shared_hw_config;
662
663 struct port_hw_cfg port_hw_config[PORT_MAX];
664
665 struct shared_feat_cfg shared_feature_config;
666
667 struct port_feat_cfg port_feature_config[PORT_MAX];
668
669};
670
671
672#define FUNC_0 0
673#define FUNC_1 1
674#define FUNC_2 2
675#define FUNC_3 3
676#define FUNC_4 4
677#define FUNC_5 5
678#define FUNC_6 6
679#define FUNC_7 7
680#define E1_FUNC_MAX 2
681#define E1H_FUNC_MAX 8
682#define E2_FUNC_MAX 4
683
684#define VN_0 0
685#define VN_1 1
686#define VN_2 2
687#define VN_3 3
688#define E1VN_MAX 1
689#define E1HVN_MAX 4
690
691#define E2_VF_MAX 64
692
693
694
695#define DRV_PULSE_PERIOD_MS 250
696
697
698
699
700
701
702#define FW_ACK_TIME_OUT_MS 5000
703
704#define FW_ACK_POLL_TIME_MS 1
705
706#define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
707
708
709#define LED_BLINK_RATE_VAL 480
710
711
712
713
714struct drv_port_mb {
715
716 u32 link_status;
717
718
719#define LINK_STATUS_LINK_FLAG_MASK 0x00000001
720#define LINK_STATUS_LINK_UP 0x00000001
721#define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
722#define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
723#define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
724#define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
725#define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
726#define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
727#define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
728#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
729#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
730#define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
731#define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
732#define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
733#define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
734#define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
735#define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
736#define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD (11<<1)
737#define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD (11<<1)
738#define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD (12<<1)
739#define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD (12<<1)
740#define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD (13<<1)
741#define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD (13<<1)
742#define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD (14<<1)
743#define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD (14<<1)
744#define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD (15<<1)
745#define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD (15<<1)
746
747#define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
748#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
749
750#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
751#define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
752#define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
753
754#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
755#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
756#define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
757#define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
758#define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
759#define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
760#define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
761
762#define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
763#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
764
765#define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
766#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
767
768#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
769#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
770#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
771#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
772#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
773
774#define LINK_STATUS_SERDES_LINK 0x00100000
775
776#define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
777#define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
778#define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
779#define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE 0x01000000
780#define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE 0x02000000
781#define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE 0x04000000
782#define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000
783#define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000
784
785 u32 port_stx;
786
787 u32 stat_nig_timer;
788
789
790 u32 ext_phy_fw_version;
791
792};
793
794
795struct drv_func_mb {
796
797 u32 drv_mb_header;
798#define DRV_MSG_CODE_MASK 0xffff0000
799#define DRV_MSG_CODE_LOAD_REQ 0x10000000
800#define DRV_MSG_CODE_LOAD_DONE 0x11000000
801#define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
802#define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
803#define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
804#define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
805#define DRV_MSG_CODE_DCC_OK 0x30000000
806#define DRV_MSG_CODE_DCC_FAILURE 0x31000000
807#define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
808#define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
809#define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
810#define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
811#define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
812#define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
813#define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
814
815
816
817
818#define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000
819#define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006
820
821
822
823
824#define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
825#define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
826
827#define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000
828#define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000
829#define DRV_MSG_CODE_SET_MF_BW 0xe0000000
830#define REQ_BC_VER_4_SET_MF_BW 0x00060202
831#define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000
832#define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
833#define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
834#define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
835#define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
836
837#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
838
839 u32 drv_mb_param;
840
841 u32 fw_mb_header;
842#define FW_MSG_CODE_MASK 0xffff0000
843#define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
844#define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
845#define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
846
847#define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000
848#define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000
849#define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
850#define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
851#define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
852#define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
853#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
854#define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
855#define FW_MSG_CODE_DCC_DONE 0x30100000
856#define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
857#define FW_MSG_CODE_DIAG_REFUSE 0x50200000
858#define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
859#define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
860#define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
861#define FW_MSG_CODE_GET_KEY_DONE 0x80100000
862#define FW_MSG_CODE_NO_KEY 0x80f00000
863#define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
864#define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
865#define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
866#define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
867#define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
868#define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
869#define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000
870#define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000
871#define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000
872
873#define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
874#define FW_MSG_CODE_LIC_RESPONSE 0xff020000
875#define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
876#define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
877
878#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
879
880 u32 fw_mb_param;
881
882 u32 drv_pulse_mb;
883#define DRV_PULSE_SEQ_MASK 0x00007fff
884#define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
885
886
887#define DRV_PULSE_ALWAYS_ALIVE 0x00008000
888
889
890
891
892 u32 mcp_pulse_mb;
893#define MCP_PULSE_SEQ_MASK 0x00007fff
894#define MCP_PULSE_ALWAYS_ALIVE 0x00008000
895
896
897#define MCP_EVENT_MASK 0xffff0000
898#define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
899
900 u32 iscsi_boot_signature;
901 u32 iscsi_boot_block_offset;
902
903 u32 drv_status;
904#define DRV_STATUS_PMF 0x00000001
905#define DRV_STATUS_SET_MF_BW 0x00000004
906
907#define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
908#define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
909#define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
910#define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
911#define DRV_STATUS_DCC_RESERVED1 0x00000800
912#define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
913#define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
914#define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000
915#define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000
916
917 u32 virt_mac_upper;
918#define VIRT_MAC_SIGN_MASK 0xffff0000
919#define VIRT_MAC_SIGNATURE 0x564d0000
920 u32 virt_mac_lower;
921
922};
923
924
925
926
927
928
929#define MGMTFW_STATE_WORD_SIZE 110
930
931struct mgmtfw_state {
932 u32 opaque[MGMTFW_STATE_WORD_SIZE];
933};
934
935
936
937
938
939struct shared_mf_cfg {
940
941 u32 clp_mb;
942#define SHARED_MF_CLP_SET_DEFAULT 0x00000000
943
944#define SHARED_MF_CLP_EXIT 0x00000001
945
946#define SHARED_MF_CLP_EXIT_DONE 0x00010000
947
948};
949
950struct port_mf_cfg {
951
952 u32 dynamic_cfg;
953#define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
954#define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
955#define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK
956
957 u32 reserved[3];
958
959};
960
961struct func_mf_cfg {
962
963 u32 config;
964
965
966#define FUNC_MF_CFG_FUNC_HIDE 0x00000001
967
968#define FUNC_MF_CFG_PROTOCOL_MASK 0x00000007
969#define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
970#define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
971#define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
972#define FUNC_MF_CFG_PROTOCOL_DEFAULT\
973 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
974
975#define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
976
977
978
979#define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
980#define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
981#define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
982
983
984
985#define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
986#define FUNC_MF_CFG_MIN_BW_SHIFT 16
987#define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
988#define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
989#define FUNC_MF_CFG_MAX_BW_SHIFT 24
990#define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
991
992 u32 mac_upper;
993#define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
994#define FUNC_MF_CFG_UPPERMAC_SHIFT 0
995#define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
996 u32 mac_lower;
997#define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
998
999 u32 e1hov_tag;
1000#define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1001#define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
1002#define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
1003
1004 u32 reserved[2];
1005
1006};
1007
1008
1009struct func_ext_cfg {
1010 u32 func_cfg;
1011#define MACP_FUNC_CFG_FLAGS_MASK 0x000000FF
1012#define MACP_FUNC_CFG_FLAGS_SHIFT 0
1013#define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001
1014#define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002
1015#define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004
1016#define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008
1017
1018 u32 iscsi_mac_addr_upper;
1019 u32 iscsi_mac_addr_lower;
1020
1021 u32 fcoe_mac_addr_upper;
1022 u32 fcoe_mac_addr_lower;
1023
1024 u32 fcoe_wwn_port_name_upper;
1025 u32 fcoe_wwn_port_name_lower;
1026
1027 u32 fcoe_wwn_node_name_upper;
1028 u32 fcoe_wwn_node_name_lower;
1029
1030 u32 preserve_data;
1031#define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0)
1032#define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1)
1033#define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2)
1034#define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3)
1035#define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4)
1036};
1037
1038struct mf_cfg {
1039
1040 struct shared_mf_cfg shared_mf_config;
1041 struct port_mf_cfg port_mf_config[PORT_MAX];
1042 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX];
1043
1044 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX];
1045};
1046
1047
1048
1049
1050
1051struct shmem_region {
1052
1053 u32 validity_map[PORT_MAX];
1054#define SHR_MEM_FORMAT_REV_ID ('A'<<24)
1055#define SHR_MEM_FORMAT_REV_MASK 0xff000000
1056
1057#define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
1058#define SHR_MEM_VALIDITY_MB 0x00200000
1059#define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
1060#define SHR_MEM_VALIDITY_RESERVED 0x00000007
1061
1062#define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
1063#define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
1064#define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
1065#define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
1066
1067#define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
1068#define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
1069#define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
1070#define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
1071#define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
1072#define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
1073
1074 struct shm_dev_info dev_info;
1075
1076 struct license_key drv_lic_key[PORT_MAX];
1077
1078
1079 u32 fw_info_fio_offset;
1080 struct mgmtfw_state mgmtfw_state;
1081
1082 struct drv_port_mb port_mb[PORT_MAX];
1083 struct drv_func_mb func_mb[];
1084
1085
1086};
1087
1088struct fw_flr_ack {
1089 u32 pf_ack;
1090 u32 vf_ack[1];
1091 u32 iov_dis_ack;
1092};
1093
1094struct fw_flr_mb {
1095 u32 aggint;
1096 u32 opgen_addr;
1097 struct fw_flr_ack ack;
1098};
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110#define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1)
1111#define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb)))
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137#define SHMEM_ARRAY_BITPOS(i, eb, fb) \
1138 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
1139 (((i)%((fb)/(eb))) * (eb)))
1140
1141#define SHMEM_ARRAY_GET(a, i, eb, fb) \
1142 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \
1143 SHMEM_ARRAY_MASK(eb))
1144
1145#define SHMEM_ARRAY_SET(a, i, eb, fb, val) \
1146do { \
1147 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \
1148 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1149 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \
1150 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1151} while (0)
1152
1153
1154
1155#define DCBX_MAX_NUM_PRI_PG_ENTRIES 8
1156#define DCBX_PRI_PG_BITWIDTH 4
1157#define DCBX_PRI_PG_FBITS 8
1158#define DCBX_PRI_PG_GET(a, i) \
1159 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
1160#define DCBX_PRI_PG_SET(a, i, val) \
1161 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
1162#define DCBX_MAX_NUM_PG_BW_ENTRIES 8
1163#define DCBX_BW_PG_BITWIDTH 8
1164#define DCBX_PG_BW_GET(a, i) \
1165 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
1166#define DCBX_PG_BW_SET(a, i, val) \
1167 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
1168#define DCBX_STRICT_PRI_PG 15
1169#define DCBX_MAX_APP_PROTOCOL 16
1170#define FCOE_APP_IDX 0
1171#define ISCSI_APP_IDX 1
1172#define PREDEFINED_APP_IDX_MAX 2
1173
1174struct dcbx_ets_feature {
1175 u32 enabled;
1176 u32 pg_bw_tbl[2];
1177 u32 pri_pg_tbl[1];
1178};
1179
1180struct dcbx_pfc_feature {
1181#ifdef __BIG_ENDIAN
1182 u8 pri_en_bitmap;
1183#define DCBX_PFC_PRI_0 0x01
1184#define DCBX_PFC_PRI_1 0x02
1185#define DCBX_PFC_PRI_2 0x04
1186#define DCBX_PFC_PRI_3 0x08
1187#define DCBX_PFC_PRI_4 0x10
1188#define DCBX_PFC_PRI_5 0x20
1189#define DCBX_PFC_PRI_6 0x40
1190#define DCBX_PFC_PRI_7 0x80
1191 u8 pfc_caps;
1192 u8 reserved;
1193 u8 enabled;
1194#elif defined(__LITTLE_ENDIAN)
1195 u8 enabled;
1196 u8 reserved;
1197 u8 pfc_caps;
1198 u8 pri_en_bitmap;
1199#define DCBX_PFC_PRI_0 0x01
1200#define DCBX_PFC_PRI_1 0x02
1201#define DCBX_PFC_PRI_2 0x04
1202#define DCBX_PFC_PRI_3 0x08
1203#define DCBX_PFC_PRI_4 0x10
1204#define DCBX_PFC_PRI_5 0x20
1205#define DCBX_PFC_PRI_6 0x40
1206#define DCBX_PFC_PRI_7 0x80
1207#endif
1208};
1209
1210struct dcbx_app_priority_entry {
1211#ifdef __BIG_ENDIAN
1212 u16 app_id;
1213 u8 pri_bitmap;
1214 u8 appBitfield;
1215#define DCBX_APP_ENTRY_VALID 0x01
1216#define DCBX_APP_ENTRY_SF_MASK 0x30
1217#define DCBX_APP_ENTRY_SF_SHIFT 4
1218#define DCBX_APP_SF_ETH_TYPE 0x10
1219#define DCBX_APP_SF_PORT 0x20
1220#elif defined(__LITTLE_ENDIAN)
1221 u8 appBitfield;
1222#define DCBX_APP_ENTRY_VALID 0x01
1223#define DCBX_APP_ENTRY_SF_MASK 0x30
1224#define DCBX_APP_ENTRY_SF_SHIFT 4
1225#define DCBX_APP_SF_ETH_TYPE 0x10
1226#define DCBX_APP_SF_PORT 0x20
1227 u8 pri_bitmap;
1228 u16 app_id;
1229#endif
1230};
1231
1232struct dcbx_app_priority_feature {
1233#ifdef __BIG_ENDIAN
1234 u8 reserved;
1235 u8 default_pri;
1236 u8 tc_supported;
1237 u8 enabled;
1238#elif defined(__LITTLE_ENDIAN)
1239 u8 enabled;
1240 u8 tc_supported;
1241 u8 default_pri;
1242 u8 reserved;
1243#endif
1244 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
1245};
1246
1247struct dcbx_features {
1248 struct dcbx_ets_feature ets;
1249 struct dcbx_pfc_feature pfc;
1250 struct dcbx_app_priority_feature app;
1251};
1252
1253struct lldp_params {
1254#ifdef __BIG_ENDIAN
1255 u8 msg_fast_tx_interval;
1256 u8 msg_tx_hold;
1257 u8 msg_tx_interval;
1258 u8 admin_status;
1259#define LLDP_TX_ONLY 0x01
1260#define LLDP_RX_ONLY 0x02
1261#define LLDP_TX_RX 0x03
1262#define LLDP_DISABLED 0x04
1263 u8 reserved1;
1264 u8 tx_fast;
1265 u8 tx_crd_max;
1266 u8 tx_crd;
1267#elif defined(__LITTLE_ENDIAN)
1268 u8 admin_status;
1269#define LLDP_TX_ONLY 0x01
1270#define LLDP_RX_ONLY 0x02
1271#define LLDP_TX_RX 0x03
1272#define LLDP_DISABLED 0x04
1273 u8 msg_tx_interval;
1274 u8 msg_tx_hold;
1275 u8 msg_fast_tx_interval;
1276 u8 tx_crd;
1277 u8 tx_crd_max;
1278 u8 tx_fast;
1279 u8 reserved1;
1280#endif
1281#define REM_CHASSIS_ID_STAT_LEN 4
1282#define REM_PORT_ID_STAT_LEN 4
1283 u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
1284 u32 peer_port_id[REM_PORT_ID_STAT_LEN];
1285};
1286
1287struct lldp_dcbx_stat {
1288#define LOCAL_CHASSIS_ID_STAT_LEN 2
1289#define LOCAL_PORT_ID_STAT_LEN 2
1290 u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
1291 u32 local_port_id[LOCAL_PORT_ID_STAT_LEN];
1292 u32 num_tx_dcbx_pkts;
1293 u32 num_rx_dcbx_pkts;
1294};
1295
1296struct lldp_admin_mib {
1297 u32 ver_cfg_flags;
1298#define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001
1299#define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002
1300#define DCBX_APP_CONFIG_TX_ENABLED 0x00000004
1301#define DCBX_ETS_RECO_TX_ENABLED 0x00000008
1302#define DCBX_ETS_RECO_VALID 0x00000010
1303#define DCBX_ETS_WILLING 0x00000020
1304#define DCBX_PFC_WILLING 0x00000040
1305#define DCBX_APP_WILLING 0x00000080
1306#define DCBX_VERSION_CEE 0x00000100
1307#define DCBX_VERSION_IEEE 0x00000200
1308#define DCBX_DCBX_ENABLED 0x00000400
1309#define DCBX_CEE_VERSION_MASK 0x0000f000
1310#define DCBX_CEE_VERSION_SHIFT 12
1311#define DCBX_CEE_MAX_VERSION_MASK 0x000f0000
1312#define DCBX_CEE_MAX_VERSION_SHIFT 16
1313 struct dcbx_features features;
1314};
1315
1316struct lldp_remote_mib {
1317 u32 prefix_seq_num;
1318 u32 flags;
1319#define DCBX_ETS_TLV_RX 0x00000001
1320#define DCBX_PFC_TLV_RX 0x00000002
1321#define DCBX_APP_TLV_RX 0x00000004
1322#define DCBX_ETS_RX_ERROR 0x00000010
1323#define DCBX_PFC_RX_ERROR 0x00000020
1324#define DCBX_APP_RX_ERROR 0x00000040
1325#define DCBX_ETS_REM_WILLING 0x00000100
1326#define DCBX_PFC_REM_WILLING 0x00000200
1327#define DCBX_APP_REM_WILLING 0x00000400
1328#define DCBX_REMOTE_ETS_RECO_VALID 0x00001000
1329 struct dcbx_features features;
1330 u32 suffix_seq_num;
1331};
1332
1333struct lldp_local_mib {
1334 u32 prefix_seq_num;
1335 u32 error;
1336#define DCBX_LOCAL_ETS_ERROR 0x00000001
1337#define DCBX_LOCAL_PFC_ERROR 0x00000002
1338#define DCBX_LOCAL_APP_ERROR 0x00000004
1339#define DCBX_LOCAL_PFC_MISMATCH 0x00000010
1340#define DCBX_LOCAL_APP_MISMATCH 0x00000020
1341 struct dcbx_features features;
1342 u32 suffix_seq_num;
1343};
1344
1345
1346struct shmem2_region {
1347
1348 u32 size;
1349
1350 u32 dcc_support;
1351#define SHMEM_DCC_SUPPORT_NONE 0x00000000
1352#define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
1353#define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
1354#define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
1355#define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
1356#define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
1357#define SHMEM_DCC_SUPPORT_DEFAULT SHMEM_DCC_SUPPORT_NONE
1358 u32 ext_phy_fw_version2[PORT_MAX];
1359
1360
1361
1362
1363
1364 u32 mf_cfg_addr;
1365#define SHMEM_MF_CFG_ADDR_NONE 0x00000000
1366
1367 struct fw_flr_mb flr_mb;
1368 u32 dcbx_lldp_params_offset;
1369#define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000
1370 u32 dcbx_neg_res_offset;
1371#define SHMEM_DCBX_NEG_RES_NONE 0x00000000
1372 u32 dcbx_remote_mib_offset;
1373#define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000
1374
1375
1376
1377
1378
1379
1380 u32 other_shmem_base_addr;
1381 u32 other_shmem2_base_addr;
1382 u32 reserved1[E2_VF_MAX / 32];
1383 u32 reserved2[E2_FUNC_MAX][E2_VF_MAX / 32];
1384 u32 dcbx_lldp_dcbx_stat_offset;
1385#define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000
1386};
1387
1388
1389struct emac_stats {
1390 u32 rx_stat_ifhcinoctets;
1391 u32 rx_stat_ifhcinbadoctets;
1392 u32 rx_stat_etherstatsfragments;
1393 u32 rx_stat_ifhcinucastpkts;
1394 u32 rx_stat_ifhcinmulticastpkts;
1395 u32 rx_stat_ifhcinbroadcastpkts;
1396 u32 rx_stat_dot3statsfcserrors;
1397 u32 rx_stat_dot3statsalignmenterrors;
1398 u32 rx_stat_dot3statscarriersenseerrors;
1399 u32 rx_stat_xonpauseframesreceived;
1400 u32 rx_stat_xoffpauseframesreceived;
1401 u32 rx_stat_maccontrolframesreceived;
1402 u32 rx_stat_xoffstateentered;
1403 u32 rx_stat_dot3statsframestoolong;
1404 u32 rx_stat_etherstatsjabbers;
1405 u32 rx_stat_etherstatsundersizepkts;
1406 u32 rx_stat_etherstatspkts64octets;
1407 u32 rx_stat_etherstatspkts65octetsto127octets;
1408 u32 rx_stat_etherstatspkts128octetsto255octets;
1409 u32 rx_stat_etherstatspkts256octetsto511octets;
1410 u32 rx_stat_etherstatspkts512octetsto1023octets;
1411 u32 rx_stat_etherstatspkts1024octetsto1522octets;
1412 u32 rx_stat_etherstatspktsover1522octets;
1413
1414 u32 rx_stat_falsecarriererrors;
1415
1416 u32 tx_stat_ifhcoutoctets;
1417 u32 tx_stat_ifhcoutbadoctets;
1418 u32 tx_stat_etherstatscollisions;
1419 u32 tx_stat_outxonsent;
1420 u32 tx_stat_outxoffsent;
1421 u32 tx_stat_flowcontroldone;
1422 u32 tx_stat_dot3statssinglecollisionframes;
1423 u32 tx_stat_dot3statsmultiplecollisionframes;
1424 u32 tx_stat_dot3statsdeferredtransmissions;
1425 u32 tx_stat_dot3statsexcessivecollisions;
1426 u32 tx_stat_dot3statslatecollisions;
1427 u32 tx_stat_ifhcoutucastpkts;
1428 u32 tx_stat_ifhcoutmulticastpkts;
1429 u32 tx_stat_ifhcoutbroadcastpkts;
1430 u32 tx_stat_etherstatspkts64octets;
1431 u32 tx_stat_etherstatspkts65octetsto127octets;
1432 u32 tx_stat_etherstatspkts128octetsto255octets;
1433 u32 tx_stat_etherstatspkts256octetsto511octets;
1434 u32 tx_stat_etherstatspkts512octetsto1023octets;
1435 u32 tx_stat_etherstatspkts1024octetsto1522octets;
1436 u32 tx_stat_etherstatspktsover1522octets;
1437 u32 tx_stat_dot3statsinternalmactransmiterrors;
1438};
1439
1440
1441struct bmac1_stats {
1442 u32 tx_stat_gtpkt_lo;
1443 u32 tx_stat_gtpkt_hi;
1444 u32 tx_stat_gtxpf_lo;
1445 u32 tx_stat_gtxpf_hi;
1446 u32 tx_stat_gtfcs_lo;
1447 u32 tx_stat_gtfcs_hi;
1448 u32 tx_stat_gtmca_lo;
1449 u32 tx_stat_gtmca_hi;
1450 u32 tx_stat_gtbca_lo;
1451 u32 tx_stat_gtbca_hi;
1452 u32 tx_stat_gtfrg_lo;
1453 u32 tx_stat_gtfrg_hi;
1454 u32 tx_stat_gtovr_lo;
1455 u32 tx_stat_gtovr_hi;
1456 u32 tx_stat_gt64_lo;
1457 u32 tx_stat_gt64_hi;
1458 u32 tx_stat_gt127_lo;
1459 u32 tx_stat_gt127_hi;
1460 u32 tx_stat_gt255_lo;
1461 u32 tx_stat_gt255_hi;
1462 u32 tx_stat_gt511_lo;
1463 u32 tx_stat_gt511_hi;
1464 u32 tx_stat_gt1023_lo;
1465 u32 tx_stat_gt1023_hi;
1466 u32 tx_stat_gt1518_lo;
1467 u32 tx_stat_gt1518_hi;
1468 u32 tx_stat_gt2047_lo;
1469 u32 tx_stat_gt2047_hi;
1470 u32 tx_stat_gt4095_lo;
1471 u32 tx_stat_gt4095_hi;
1472 u32 tx_stat_gt9216_lo;
1473 u32 tx_stat_gt9216_hi;
1474 u32 tx_stat_gt16383_lo;
1475 u32 tx_stat_gt16383_hi;
1476 u32 tx_stat_gtmax_lo;
1477 u32 tx_stat_gtmax_hi;
1478 u32 tx_stat_gtufl_lo;
1479 u32 tx_stat_gtufl_hi;
1480 u32 tx_stat_gterr_lo;
1481 u32 tx_stat_gterr_hi;
1482 u32 tx_stat_gtbyt_lo;
1483 u32 tx_stat_gtbyt_hi;
1484
1485 u32 rx_stat_gr64_lo;
1486 u32 rx_stat_gr64_hi;
1487 u32 rx_stat_gr127_lo;
1488 u32 rx_stat_gr127_hi;
1489 u32 rx_stat_gr255_lo;
1490 u32 rx_stat_gr255_hi;
1491 u32 rx_stat_gr511_lo;
1492 u32 rx_stat_gr511_hi;
1493 u32 rx_stat_gr1023_lo;
1494 u32 rx_stat_gr1023_hi;
1495 u32 rx_stat_gr1518_lo;
1496 u32 rx_stat_gr1518_hi;
1497 u32 rx_stat_gr2047_lo;
1498 u32 rx_stat_gr2047_hi;
1499 u32 rx_stat_gr4095_lo;
1500 u32 rx_stat_gr4095_hi;
1501 u32 rx_stat_gr9216_lo;
1502 u32 rx_stat_gr9216_hi;
1503 u32 rx_stat_gr16383_lo;
1504 u32 rx_stat_gr16383_hi;
1505 u32 rx_stat_grmax_lo;
1506 u32 rx_stat_grmax_hi;
1507 u32 rx_stat_grpkt_lo;
1508 u32 rx_stat_grpkt_hi;
1509 u32 rx_stat_grfcs_lo;
1510 u32 rx_stat_grfcs_hi;
1511 u32 rx_stat_grmca_lo;
1512 u32 rx_stat_grmca_hi;
1513 u32 rx_stat_grbca_lo;
1514 u32 rx_stat_grbca_hi;
1515 u32 rx_stat_grxcf_lo;
1516 u32 rx_stat_grxcf_hi;
1517 u32 rx_stat_grxpf_lo;
1518 u32 rx_stat_grxpf_hi;
1519 u32 rx_stat_grxuo_lo;
1520 u32 rx_stat_grxuo_hi;
1521 u32 rx_stat_grjbr_lo;
1522 u32 rx_stat_grjbr_hi;
1523 u32 rx_stat_grovr_lo;
1524 u32 rx_stat_grovr_hi;
1525 u32 rx_stat_grflr_lo;
1526 u32 rx_stat_grflr_hi;
1527 u32 rx_stat_grmeg_lo;
1528 u32 rx_stat_grmeg_hi;
1529 u32 rx_stat_grmeb_lo;
1530 u32 rx_stat_grmeb_hi;
1531 u32 rx_stat_grbyt_lo;
1532 u32 rx_stat_grbyt_hi;
1533 u32 rx_stat_grund_lo;
1534 u32 rx_stat_grund_hi;
1535 u32 rx_stat_grfrg_lo;
1536 u32 rx_stat_grfrg_hi;
1537 u32 rx_stat_grerb_lo;
1538 u32 rx_stat_grerb_hi;
1539 u32 rx_stat_grfre_lo;
1540 u32 rx_stat_grfre_hi;
1541 u32 rx_stat_gripj_lo;
1542 u32 rx_stat_gripj_hi;
1543};
1544
1545struct bmac2_stats {
1546 u32 tx_stat_gtpk_lo;
1547 u32 tx_stat_gtpk_hi;
1548 u32 tx_stat_gtxpf_lo;
1549 u32 tx_stat_gtxpf_hi;
1550 u32 tx_stat_gtpp_lo;
1551 u32 tx_stat_gtpp_hi;
1552 u32 tx_stat_gtfcs_lo;
1553 u32 tx_stat_gtfcs_hi;
1554 u32 tx_stat_gtuca_lo;
1555 u32 tx_stat_gtuca_hi;
1556 u32 tx_stat_gtmca_lo;
1557 u32 tx_stat_gtmca_hi;
1558 u32 tx_stat_gtbca_lo;
1559 u32 tx_stat_gtbca_hi;
1560 u32 tx_stat_gtovr_lo;
1561 u32 tx_stat_gtovr_hi;
1562 u32 tx_stat_gtfrg_lo;
1563 u32 tx_stat_gtfrg_hi;
1564 u32 tx_stat_gtpkt1_lo;
1565 u32 tx_stat_gtpkt1_hi;
1566 u32 tx_stat_gt64_lo;
1567 u32 tx_stat_gt64_hi;
1568 u32 tx_stat_gt127_lo;
1569 u32 tx_stat_gt127_hi;
1570 u32 tx_stat_gt255_lo;
1571 u32 tx_stat_gt255_hi;
1572 u32 tx_stat_gt511_lo;
1573 u32 tx_stat_gt511_hi;
1574 u32 tx_stat_gt1023_lo;
1575 u32 tx_stat_gt1023_hi;
1576 u32 tx_stat_gt1518_lo;
1577 u32 tx_stat_gt1518_hi;
1578 u32 tx_stat_gt2047_lo;
1579 u32 tx_stat_gt2047_hi;
1580 u32 tx_stat_gt4095_lo;
1581 u32 tx_stat_gt4095_hi;
1582 u32 tx_stat_gt9216_lo;
1583 u32 tx_stat_gt9216_hi;
1584 u32 tx_stat_gt16383_lo;
1585 u32 tx_stat_gt16383_hi;
1586 u32 tx_stat_gtmax_lo;
1587 u32 tx_stat_gtmax_hi;
1588 u32 tx_stat_gtufl_lo;
1589 u32 tx_stat_gtufl_hi;
1590 u32 tx_stat_gterr_lo;
1591 u32 tx_stat_gterr_hi;
1592 u32 tx_stat_gtbyt_lo;
1593 u32 tx_stat_gtbyt_hi;
1594
1595 u32 rx_stat_gr64_lo;
1596 u32 rx_stat_gr64_hi;
1597 u32 rx_stat_gr127_lo;
1598 u32 rx_stat_gr127_hi;
1599 u32 rx_stat_gr255_lo;
1600 u32 rx_stat_gr255_hi;
1601 u32 rx_stat_gr511_lo;
1602 u32 rx_stat_gr511_hi;
1603 u32 rx_stat_gr1023_lo;
1604 u32 rx_stat_gr1023_hi;
1605 u32 rx_stat_gr1518_lo;
1606 u32 rx_stat_gr1518_hi;
1607 u32 rx_stat_gr2047_lo;
1608 u32 rx_stat_gr2047_hi;
1609 u32 rx_stat_gr4095_lo;
1610 u32 rx_stat_gr4095_hi;
1611 u32 rx_stat_gr9216_lo;
1612 u32 rx_stat_gr9216_hi;
1613 u32 rx_stat_gr16383_lo;
1614 u32 rx_stat_gr16383_hi;
1615 u32 rx_stat_grmax_lo;
1616 u32 rx_stat_grmax_hi;
1617 u32 rx_stat_grpkt_lo;
1618 u32 rx_stat_grpkt_hi;
1619 u32 rx_stat_grfcs_lo;
1620 u32 rx_stat_grfcs_hi;
1621 u32 rx_stat_gruca_lo;
1622 u32 rx_stat_gruca_hi;
1623 u32 rx_stat_grmca_lo;
1624 u32 rx_stat_grmca_hi;
1625 u32 rx_stat_grbca_lo;
1626 u32 rx_stat_grbca_hi;
1627 u32 rx_stat_grxpf_lo;
1628 u32 rx_stat_grxpf_hi;
1629 u32 rx_stat_grpp_lo;
1630 u32 rx_stat_grpp_hi;
1631 u32 rx_stat_grxuo_lo;
1632 u32 rx_stat_grxuo_hi;
1633 u32 rx_stat_grjbr_lo;
1634 u32 rx_stat_grjbr_hi;
1635 u32 rx_stat_grovr_lo;
1636 u32 rx_stat_grovr_hi;
1637 u32 rx_stat_grxcf_lo;
1638 u32 rx_stat_grxcf_hi;
1639 u32 rx_stat_grflr_lo;
1640 u32 rx_stat_grflr_hi;
1641 u32 rx_stat_grpok_lo;
1642 u32 rx_stat_grpok_hi;
1643 u32 rx_stat_grmeg_lo;
1644 u32 rx_stat_grmeg_hi;
1645 u32 rx_stat_grmeb_lo;
1646 u32 rx_stat_grmeb_hi;
1647 u32 rx_stat_grbyt_lo;
1648 u32 rx_stat_grbyt_hi;
1649 u32 rx_stat_grund_lo;
1650 u32 rx_stat_grund_hi;
1651 u32 rx_stat_grfrg_lo;
1652 u32 rx_stat_grfrg_hi;
1653 u32 rx_stat_grerb_lo;
1654 u32 rx_stat_grerb_hi;
1655 u32 rx_stat_grfre_lo;
1656 u32 rx_stat_grfre_hi;
1657 u32 rx_stat_gripj_lo;
1658 u32 rx_stat_gripj_hi;
1659};
1660
1661union mac_stats {
1662 struct emac_stats emac_stats;
1663 struct bmac1_stats bmac1_stats;
1664 struct bmac2_stats bmac2_stats;
1665};
1666
1667
1668struct mac_stx {
1669
1670 u32 rx_stat_ifhcinbadoctets_hi;
1671 u32 rx_stat_ifhcinbadoctets_lo;
1672
1673
1674 u32 tx_stat_ifhcoutbadoctets_hi;
1675 u32 tx_stat_ifhcoutbadoctets_lo;
1676
1677
1678 u32 rx_stat_dot3statsfcserrors_hi;
1679 u32 rx_stat_dot3statsfcserrors_lo;
1680
1681 u32 rx_stat_dot3statsalignmenterrors_hi;
1682 u32 rx_stat_dot3statsalignmenterrors_lo;
1683
1684 u32 rx_stat_dot3statscarriersenseerrors_hi;
1685 u32 rx_stat_dot3statscarriersenseerrors_lo;
1686
1687 u32 rx_stat_falsecarriererrors_hi;
1688 u32 rx_stat_falsecarriererrors_lo;
1689
1690
1691 u32 rx_stat_etherstatsundersizepkts_hi;
1692 u32 rx_stat_etherstatsundersizepkts_lo;
1693
1694 u32 rx_stat_dot3statsframestoolong_hi;
1695 u32 rx_stat_dot3statsframestoolong_lo;
1696
1697
1698 u32 rx_stat_etherstatsfragments_hi;
1699 u32 rx_stat_etherstatsfragments_lo;
1700
1701 u32 rx_stat_etherstatsjabbers_hi;
1702 u32 rx_stat_etherstatsjabbers_lo;
1703
1704
1705 u32 rx_stat_maccontrolframesreceived_hi;
1706 u32 rx_stat_maccontrolframesreceived_lo;
1707 u32 rx_stat_bmac_xpf_hi;
1708 u32 rx_stat_bmac_xpf_lo;
1709 u32 rx_stat_bmac_xcf_hi;
1710 u32 rx_stat_bmac_xcf_lo;
1711
1712
1713 u32 rx_stat_xoffstateentered_hi;
1714 u32 rx_stat_xoffstateentered_lo;
1715
1716 u32 rx_stat_xonpauseframesreceived_hi;
1717 u32 rx_stat_xonpauseframesreceived_lo;
1718
1719 u32 rx_stat_xoffpauseframesreceived_hi;
1720 u32 rx_stat_xoffpauseframesreceived_lo;
1721
1722 u32 tx_stat_outxonsent_hi;
1723 u32 tx_stat_outxonsent_lo;
1724
1725 u32 tx_stat_outxoffsent_hi;
1726 u32 tx_stat_outxoffsent_lo;
1727
1728 u32 tx_stat_flowcontroldone_hi;
1729 u32 tx_stat_flowcontroldone_lo;
1730
1731
1732 u32 tx_stat_etherstatscollisions_hi;
1733 u32 tx_stat_etherstatscollisions_lo;
1734
1735 u32 tx_stat_dot3statssinglecollisionframes_hi;
1736 u32 tx_stat_dot3statssinglecollisionframes_lo;
1737
1738 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
1739 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
1740
1741 u32 tx_stat_dot3statsdeferredtransmissions_hi;
1742 u32 tx_stat_dot3statsdeferredtransmissions_lo;
1743
1744 u32 tx_stat_dot3statsexcessivecollisions_hi;
1745 u32 tx_stat_dot3statsexcessivecollisions_lo;
1746
1747 u32 tx_stat_dot3statslatecollisions_hi;
1748 u32 tx_stat_dot3statslatecollisions_lo;
1749
1750
1751 u32 tx_stat_etherstatspkts64octets_hi;
1752 u32 tx_stat_etherstatspkts64octets_lo;
1753
1754 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
1755 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
1756
1757 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
1758 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
1759
1760 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
1761 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
1762
1763 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
1764 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
1765
1766 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
1767 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
1768
1769 u32 tx_stat_etherstatspktsover1522octets_hi;
1770 u32 tx_stat_etherstatspktsover1522octets_lo;
1771 u32 tx_stat_bmac_2047_hi;
1772 u32 tx_stat_bmac_2047_lo;
1773 u32 tx_stat_bmac_4095_hi;
1774 u32 tx_stat_bmac_4095_lo;
1775 u32 tx_stat_bmac_9216_hi;
1776 u32 tx_stat_bmac_9216_lo;
1777 u32 tx_stat_bmac_16383_hi;
1778 u32 tx_stat_bmac_16383_lo;
1779
1780
1781 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
1782 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
1783
1784
1785 u32 tx_stat_bmac_ufl_hi;
1786 u32 tx_stat_bmac_ufl_lo;
1787};
1788
1789
1790#define MAC_STX_IDX_MAX 2
1791
1792struct host_port_stats {
1793 u32 host_port_stats_start;
1794
1795 struct mac_stx mac_stx[MAC_STX_IDX_MAX];
1796
1797 u32 brb_drop_hi;
1798 u32 brb_drop_lo;
1799
1800 u32 host_port_stats_end;
1801};
1802
1803
1804struct host_func_stats {
1805 u32 host_func_stats_start;
1806
1807 u32 total_bytes_received_hi;
1808 u32 total_bytes_received_lo;
1809
1810 u32 total_bytes_transmitted_hi;
1811 u32 total_bytes_transmitted_lo;
1812
1813 u32 total_unicast_packets_received_hi;
1814 u32 total_unicast_packets_received_lo;
1815
1816 u32 total_multicast_packets_received_hi;
1817 u32 total_multicast_packets_received_lo;
1818
1819 u32 total_broadcast_packets_received_hi;
1820 u32 total_broadcast_packets_received_lo;
1821
1822 u32 total_unicast_packets_transmitted_hi;
1823 u32 total_unicast_packets_transmitted_lo;
1824
1825 u32 total_multicast_packets_transmitted_hi;
1826 u32 total_multicast_packets_transmitted_lo;
1827
1828 u32 total_broadcast_packets_transmitted_hi;
1829 u32 total_broadcast_packets_transmitted_lo;
1830
1831 u32 valid_bytes_received_hi;
1832 u32 valid_bytes_received_lo;
1833
1834 u32 host_func_stats_end;
1835};
1836
1837
1838#define BCM_5710_FW_MAJOR_VERSION 6
1839#define BCM_5710_FW_MINOR_VERSION 2
1840#define BCM_5710_FW_REVISION_VERSION 5
1841#define BCM_5710_FW_ENGINEERING_VERSION 0
1842#define BCM_5710_FW_COMPILE_FLAGS 1
1843
1844
1845
1846
1847
1848struct atten_sp_status_block {
1849 __le32 attn_bits;
1850 __le32 attn_bits_ack;
1851 u8 status_block_id;
1852 u8 reserved0;
1853 __le16 attn_bits_index;
1854 __le32 reserved1;
1855};
1856
1857
1858
1859
1860
1861struct doorbell_hdr {
1862 u8 header;
1863#define DOORBELL_HDR_RX (0x1<<0)
1864#define DOORBELL_HDR_RX_SHIFT 0
1865#define DOORBELL_HDR_DB_TYPE (0x1<<1)
1866#define DOORBELL_HDR_DB_TYPE_SHIFT 1
1867#define DOORBELL_HDR_DPM_SIZE (0x3<<2)
1868#define DOORBELL_HDR_DPM_SIZE_SHIFT 2
1869#define DOORBELL_HDR_CONN_TYPE (0xF<<4)
1870#define DOORBELL_HDR_CONN_TYPE_SHIFT 4
1871};
1872
1873
1874
1875
1876struct doorbell {
1877#if defined(__BIG_ENDIAN)
1878 u16 zero_fill2;
1879 u8 zero_fill1;
1880 struct doorbell_hdr header;
1881#elif defined(__LITTLE_ENDIAN)
1882 struct doorbell_hdr header;
1883 u8 zero_fill1;
1884 u16 zero_fill2;
1885#endif
1886};
1887
1888
1889
1890
1891
1892struct doorbell_set_prod {
1893#if defined(__BIG_ENDIAN)
1894 u16 prod;
1895 u8 zero_fill1;
1896 struct doorbell_hdr header;
1897#elif defined(__LITTLE_ENDIAN)
1898 struct doorbell_hdr header;
1899 u8 zero_fill1;
1900 u16 prod;
1901#endif
1902};
1903
1904
1905
1906
1907
1908struct hc_status_block_e1x {
1909 __le16 index_values[HC_SB_MAX_INDICES_E1X];
1910 __le16 running_index[HC_SB_MAX_SM];
1911 u32 rsrv;
1912};
1913
1914
1915
1916
1917struct host_hc_status_block_e1x {
1918 struct hc_status_block_e1x sb;
1919};
1920
1921
1922
1923
1924
1925struct hc_status_block_e2 {
1926 __le16 index_values[HC_SB_MAX_INDICES_E2];
1927 __le16 running_index[HC_SB_MAX_SM];
1928 u32 reserved;
1929};
1930
1931
1932
1933
1934struct host_hc_status_block_e2 {
1935 struct hc_status_block_e2 sb;
1936};
1937
1938
1939
1940
1941
1942struct hc_sp_status_block {
1943 __le16 index_values[HC_SP_SB_MAX_INDICES];
1944 __le16 running_index;
1945 __le16 rsrv;
1946 u32 rsrv1;
1947};
1948
1949
1950
1951
1952struct host_sp_status_block {
1953 struct atten_sp_status_block atten_status_block;
1954 struct hc_sp_status_block sp_sb;
1955};
1956
1957
1958
1959
1960
1961struct igu_ack_register {
1962#if defined(__BIG_ENDIAN)
1963 u16 sb_id_and_flags;
1964#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1965#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1966#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1967#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1968#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1969#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1970#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1971#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1972#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1973#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1974 u16 status_block_index;
1975#elif defined(__LITTLE_ENDIAN)
1976 u16 status_block_index;
1977 u16 sb_id_and_flags;
1978#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1979#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1980#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1981#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1982#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1983#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1984#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1985#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1986#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1987#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1988#endif
1989};
1990
1991
1992
1993
1994
1995struct igu_backward_compatible {
1996 u32 sb_id_and_flags;
1997#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
1998#define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
1999#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
2000#define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
2001#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
2002#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
2003#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
2004#define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
2005#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
2006#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
2007#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
2008#define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
2009 u32 reserved_2;
2010};
2011
2012
2013
2014
2015
2016struct igu_regular {
2017 u32 sb_id_and_flags;
2018#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
2019#define IGU_REGULAR_SB_INDEX_SHIFT 0
2020#define IGU_REGULAR_RESERVED0 (0x1<<20)
2021#define IGU_REGULAR_RESERVED0_SHIFT 20
2022#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
2023#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
2024#define IGU_REGULAR_BUPDATE (0x1<<24)
2025#define IGU_REGULAR_BUPDATE_SHIFT 24
2026#define IGU_REGULAR_ENABLE_INT (0x3<<25)
2027#define IGU_REGULAR_ENABLE_INT_SHIFT 25
2028#define IGU_REGULAR_RESERVED_1 (0x1<<27)
2029#define IGU_REGULAR_RESERVED_1_SHIFT 27
2030#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
2031#define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
2032#define IGU_REGULAR_CLEANUP_SET (0x1<<30)
2033#define IGU_REGULAR_CLEANUP_SET_SHIFT 30
2034#define IGU_REGULAR_BCLEANUP (0x1<<31)
2035#define IGU_REGULAR_BCLEANUP_SHIFT 31
2036 u32 reserved_2;
2037};
2038
2039
2040
2041
2042union igu_consprod_reg {
2043 struct igu_regular regular;
2044 struct igu_backward_compatible backward_compatible;
2045};
2046
2047
2048
2049
2050
2051struct igu_ctrl_reg {
2052 u32 ctrl_data;
2053#define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
2054#define IGU_CTRL_REG_ADDRESS_SHIFT 0
2055#define IGU_CTRL_REG_FID (0x7F<<12)
2056#define IGU_CTRL_REG_FID_SHIFT 12
2057#define IGU_CTRL_REG_RESERVED (0x1<<19)
2058#define IGU_CTRL_REG_RESERVED_SHIFT 19
2059#define IGU_CTRL_REG_TYPE (0x1<<20)
2060#define IGU_CTRL_REG_TYPE_SHIFT 20
2061#define IGU_CTRL_REG_UNUSED (0x7FF<<21)
2062#define IGU_CTRL_REG_UNUSED_SHIFT 21
2063};
2064
2065
2066
2067
2068
2069struct parsing_flags {
2070 __le16 flags;
2071#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
2072#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
2073#define PARSING_FLAGS_VLAN (0x1<<1)
2074#define PARSING_FLAGS_VLAN_SHIFT 1
2075#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
2076#define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
2077#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
2078#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
2079#define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
2080#define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
2081#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
2082#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
2083#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
2084#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
2085#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
2086#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
2087#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
2088#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
2089#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
2090#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
2091#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
2092#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
2093#define PARSING_FLAGS_LLC_SNAP (0x1<<13)
2094#define PARSING_FLAGS_LLC_SNAP_SHIFT 13
2095#define PARSING_FLAGS_RESERVED0 (0x3<<14)
2096#define PARSING_FLAGS_RESERVED0_SHIFT 14
2097};
2098
2099
2100struct regpair {
2101 __le32 lo;
2102 __le32 hi;
2103};
2104
2105
2106
2107
2108
2109struct dmae_command {
2110 u32 opcode;
2111#define DMAE_COMMAND_SRC (0x1<<0)
2112#define DMAE_COMMAND_SRC_SHIFT 0
2113#define DMAE_COMMAND_DST (0x3<<1)
2114#define DMAE_COMMAND_DST_SHIFT 1
2115#define DMAE_COMMAND_C_DST (0x1<<3)
2116#define DMAE_COMMAND_C_DST_SHIFT 3
2117#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
2118#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
2119#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
2120#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
2121#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
2122#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
2123#define DMAE_COMMAND_ENDIANITY (0x3<<9)
2124#define DMAE_COMMAND_ENDIANITY_SHIFT 9
2125#define DMAE_COMMAND_PORT (0x1<<11)
2126#define DMAE_COMMAND_PORT_SHIFT 11
2127#define DMAE_COMMAND_CRC_RESET (0x1<<12)
2128#define DMAE_COMMAND_CRC_RESET_SHIFT 12
2129#define DMAE_COMMAND_SRC_RESET (0x1<<13)
2130#define DMAE_COMMAND_SRC_RESET_SHIFT 13
2131#define DMAE_COMMAND_DST_RESET (0x1<<14)
2132#define DMAE_COMMAND_DST_RESET_SHIFT 14
2133#define DMAE_COMMAND_E1HVN (0x3<<15)
2134#define DMAE_COMMAND_E1HVN_SHIFT 15
2135#define DMAE_COMMAND_DST_VN (0x3<<17)
2136#define DMAE_COMMAND_DST_VN_SHIFT 17
2137#define DMAE_COMMAND_C_FUNC (0x1<<19)
2138#define DMAE_COMMAND_C_FUNC_SHIFT 19
2139#define DMAE_COMMAND_ERR_POLICY (0x3<<20)
2140#define DMAE_COMMAND_ERR_POLICY_SHIFT 20
2141#define DMAE_COMMAND_RESERVED0 (0x3FF<<22)
2142#define DMAE_COMMAND_RESERVED0_SHIFT 22
2143 u32 src_addr_lo;
2144 u32 src_addr_hi;
2145 u32 dst_addr_lo;
2146 u32 dst_addr_hi;
2147#if defined(__BIG_ENDIAN)
2148 u16 reserved1;
2149 u16 len;
2150#elif defined(__LITTLE_ENDIAN)
2151 u16 len;
2152 u16 reserved1;
2153#endif
2154 u32 comp_addr_lo;
2155 u32 comp_addr_hi;
2156 u32 comp_val;
2157 u32 crc32;
2158 u32 crc32_c;
2159#if defined(__BIG_ENDIAN)
2160 u16 crc16_c;
2161 u16 crc16;
2162#elif defined(__LITTLE_ENDIAN)
2163 u16 crc16;
2164 u16 crc16_c;
2165#endif
2166#if defined(__BIG_ENDIAN)
2167 u16 reserved3;
2168 u16 crc_t10;
2169#elif defined(__LITTLE_ENDIAN)
2170 u16 crc_t10;
2171 u16 reserved3;
2172#endif
2173#if defined(__BIG_ENDIAN)
2174 u16 xsum8;
2175 u16 xsum16;
2176#elif defined(__LITTLE_ENDIAN)
2177 u16 xsum16;
2178 u16 xsum8;
2179#endif
2180};
2181
2182
2183struct double_regpair {
2184 u32 regpair0_lo;
2185 u32 regpair0_hi;
2186 u32 regpair1_lo;
2187 u32 regpair1_hi;
2188};
2189
2190
2191
2192
2193
2194struct sdm_op_gen {
2195 __le32 command;
2196#define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
2197#define SDM_OP_GEN_COMP_PARAM_SHIFT 0
2198#define SDM_OP_GEN_COMP_TYPE (0x7<<5)
2199#define SDM_OP_GEN_COMP_TYPE_SHIFT 5
2200#define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
2201#define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
2202#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
2203#define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
2204#define SDM_OP_GEN_RESERVED (0x7FFF<<17)
2205#define SDM_OP_GEN_RESERVED_SHIFT 17
2206};
2207
2208
2209
2210
2211struct eth_rx_bd {
2212 __le32 addr_lo;
2213 __le32 addr_hi;
2214};
2215
2216
2217
2218
2219struct eth_rx_sge {
2220 __le32 addr_lo;
2221 __le32 addr_hi;
2222};
2223
2224
2225
2226
2227
2228
2229struct ustorm_eth_st_context {
2230 u32 reserved0[48];
2231};
2232
2233
2234
2235
2236struct tstorm_eth_st_context {
2237 u32 __reserved0[28];
2238};
2239
2240
2241
2242
2243struct xstorm_eth_ag_context {
2244 u32 reserved0;
2245#if defined(__BIG_ENDIAN)
2246 u8 cdu_reserved;
2247 u8 reserved2;
2248 u16 reserved1;
2249#elif defined(__LITTLE_ENDIAN)
2250 u16 reserved1;
2251 u8 reserved2;
2252 u8 cdu_reserved;
2253#endif
2254 u32 reserved3[30];
2255};
2256
2257
2258
2259
2260struct tstorm_eth_ag_context {
2261 u32 __reserved0[14];
2262};
2263
2264
2265
2266
2267
2268struct cstorm_eth_ag_context {
2269 u32 __reserved0[10];
2270};
2271
2272
2273
2274
2275
2276struct ustorm_eth_ag_context {
2277 u32 __reserved0;
2278#if defined(__BIG_ENDIAN)
2279 u8 cdu_usage;
2280 u8 __reserved2;
2281 u16 __reserved1;
2282#elif defined(__LITTLE_ENDIAN)
2283 u16 __reserved1;
2284 u8 __reserved2;
2285 u8 cdu_usage;
2286#endif
2287 u32 __reserved3[6];
2288};
2289
2290
2291
2292
2293struct timers_block_context {
2294 u32 __reserved_0;
2295 u32 __reserved_1;
2296 u32 __reserved_2;
2297 u32 flags;
2298#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
2299#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
2300#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
2301#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
2302#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
2303#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
2304};
2305
2306
2307
2308
2309struct eth_tx_bd_flags {
2310 u8 as_bitfield;
2311#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
2312#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
2313#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
2314#define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
2315#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
2316#define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
2317#define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
2318#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
2319#define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
2320#define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
2321#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
2322#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
2323#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
2324#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
2325};
2326
2327
2328
2329
2330struct eth_tx_start_bd {
2331 __le32 addr_lo;
2332 __le32 addr_hi;
2333 __le16 nbd;
2334 __le16 nbytes;
2335 __le16 vlan_or_ethertype;
2336 struct eth_tx_bd_flags bd_flags;
2337 u8 general_data;
2338#define ETH_TX_START_BD_HDR_NBDS (0x3F<<0)
2339#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
2340#define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6)
2341#define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6
2342};
2343
2344
2345
2346
2347struct eth_tx_bd {
2348 __le32 addr_lo;
2349 __le32 addr_hi;
2350 __le16 total_pkt_bytes;
2351 __le16 nbytes;
2352 u8 reserved[4];
2353};
2354
2355
2356
2357
2358struct eth_tx_parse_bd_e1x {
2359 u8 global_data;
2360#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
2361#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
2362#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x1<<4)
2363#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 4
2364#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
2365#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
2366#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<6)
2367#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 6
2368#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<7)
2369#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 7
2370 u8 tcp_flags;
2371#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
2372#define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
2373#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
2374#define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
2375#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
2376#define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
2377#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
2378#define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
2379#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
2380#define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
2381#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
2382#define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
2383#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
2384#define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
2385#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
2386#define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
2387 u8 ip_hlen_w;
2388 s8 reserved;
2389 __le16 total_hlen_w;
2390 __le16 tcp_pseudo_csum;
2391 __le16 lso_mss;
2392 __le16 ip_id;
2393 __le32 tcp_send_seq;
2394};
2395
2396
2397
2398
2399struct eth_tx_parse_bd_e2 {
2400 __le16 dst_mac_addr_lo;
2401 __le16 dst_mac_addr_mid;
2402 __le16 dst_mac_addr_hi;
2403 __le16 src_mac_addr_lo;
2404 __le16 src_mac_addr_mid;
2405 __le16 src_mac_addr_hi;
2406 __le32 parsing_data;
2407#define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x1FFF<<0)
2408#define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0
2409#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<13)
2410#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 13
2411#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<17)
2412#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 17
2413#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<31)
2414#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 31
2415};
2416
2417
2418
2419
2420struct eth_tx_next_bd {
2421 __le32 addr_lo;
2422 __le32 addr_hi;
2423 u8 reserved[8];
2424};
2425
2426
2427
2428
2429union eth_tx_bd_types {
2430 struct eth_tx_start_bd start_bd;
2431 struct eth_tx_bd reg_bd;
2432 struct eth_tx_parse_bd_e1x parse_bd_e1x;
2433 struct eth_tx_parse_bd_e2 parse_bd_e2;
2434 struct eth_tx_next_bd next_bd;
2435};
2436
2437
2438
2439
2440
2441struct xstorm_eth_st_context {
2442 u32 reserved0[60];
2443};
2444
2445
2446
2447
2448struct cstorm_eth_st_context {
2449 u32 __reserved0[4];
2450};
2451
2452
2453
2454
2455struct eth_context {
2456 struct ustorm_eth_st_context ustorm_st_context;
2457 struct tstorm_eth_st_context tstorm_st_context;
2458 struct xstorm_eth_ag_context xstorm_ag_context;
2459 struct tstorm_eth_ag_context tstorm_ag_context;
2460 struct cstorm_eth_ag_context cstorm_ag_context;
2461 struct ustorm_eth_ag_context ustorm_ag_context;
2462 struct timers_block_context timers_context;
2463 struct xstorm_eth_st_context xstorm_st_context;
2464 struct cstorm_eth_st_context cstorm_st_context;
2465};
2466
2467
2468
2469
2470
2471struct eth_tx_doorbell {
2472#if defined(__BIG_ENDIAN)
2473 u16 npackets;
2474 u8 params;
2475#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2476#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2477#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2478#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2479#define ETH_TX_DOORBELL_SPARE (0x1<<7)
2480#define ETH_TX_DOORBELL_SPARE_SHIFT 7
2481 struct doorbell_hdr hdr;
2482#elif defined(__LITTLE_ENDIAN)
2483 struct doorbell_hdr hdr;
2484 u8 params;
2485#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2486#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2487#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2488#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2489#define ETH_TX_DOORBELL_SPARE (0x1<<7)
2490#define ETH_TX_DOORBELL_SPARE_SHIFT 7
2491 u16 npackets;
2492#endif
2493};
2494
2495
2496
2497
2498
2499struct client_init_fc_data {
2500 __le16 cqe_pause_thr_low;
2501 __le16 cqe_pause_thr_high;
2502 __le16 bd_pause_thr_low;
2503 __le16 bd_pause_thr_high;
2504 __le16 sge_pause_thr_low;
2505 __le16 sge_pause_thr_high;
2506 __le16 rx_cos_mask;
2507 u8 safc_group_num;
2508 u8 safc_group_en_flg;
2509 u8 traffic_type;
2510 u8 reserved0;
2511 __le16 reserved1;
2512 __le32 reserved2;
2513};
2514
2515
2516
2517
2518
2519struct client_init_general_data {
2520 u8 client_id;
2521 u8 statistics_counter_id;
2522 u8 statistics_en_flg;
2523 u8 is_fcoe_flg;
2524 u8 activate_flg;
2525 u8 sp_client_id;
2526 __le16 reserved0;
2527 __le32 reserved1[2];
2528};
2529
2530
2531
2532
2533
2534struct client_init_rx_data {
2535 u8 tpa_en_flg;
2536 u8 vmqueue_mode_en_flg;
2537 u8 extra_data_over_sgl_en_flg;
2538 u8 cache_line_alignment_log_size;
2539 u8 enable_dynamic_hc;
2540 u8 max_sges_for_packet;
2541 u8 client_qzone_id;
2542 u8 drop_ip_cs_err_flg;
2543 u8 drop_tcp_cs_err_flg;
2544 u8 drop_ttl0_flg;
2545 u8 drop_udp_cs_err_flg;
2546 u8 inner_vlan_removal_enable_flg;
2547 u8 outer_vlan_removal_enable_flg;
2548 u8 status_block_id;
2549 u8 rx_sb_index_number;
2550 u8 reserved0[3];
2551 __le16 bd_buff_size;
2552 __le16 sge_buff_size;
2553 __le16 mtu;
2554 struct regpair bd_page_base;
2555 struct regpair sge_page_base;
2556 struct regpair cqe_page_base;
2557 u8 is_leading_rss;
2558 u8 is_approx_mcast;
2559 __le16 max_agg_size;
2560 __le32 reserved2[3];
2561};
2562
2563
2564
2565
2566struct client_init_tx_data {
2567 u8 enforce_security_flg;
2568 u8 tx_status_block_id;
2569 u8 tx_sb_index_number;
2570 u8 reserved0;
2571 __le16 mtu;
2572 __le16 reserved1;
2573 struct regpair tx_bd_page_base;
2574 __le32 reserved2[2];
2575};
2576
2577
2578
2579
2580struct client_init_ramrod_data {
2581 struct client_init_general_data general;
2582 struct client_init_rx_data rx;
2583 struct client_init_tx_data tx;
2584 struct client_init_fc_data fc;
2585};
2586
2587
2588
2589
2590
2591struct eth_common_ramrod_data {
2592 u32 client_id;
2593 u32 reserved1;
2594};
2595
2596
2597
2598
2599
2600union eth_sgl_or_raw_data {
2601 __le16 sgl[8];
2602 u32 raw_data[4];
2603};
2604
2605
2606
2607
2608struct eth_fast_path_rx_cqe {
2609 u8 type_error_flags;
2610#define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0)
2611#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
2612#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1)
2613#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1
2614#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2)
2615#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2
2616#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3)
2617#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3
2618#define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4)
2619#define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4
2620#define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5)
2621#define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5
2622#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x3<<6)
2623#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 6
2624 u8 status_flags;
2625#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
2626#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
2627#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
2628#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
2629#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
2630#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
2631#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
2632#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
2633#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
2634#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
2635#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
2636#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
2637 u8 placement_offset;
2638 u8 queue_index;
2639 __le32 rss_hash_result;
2640 __le16 vlan_tag;
2641 __le16 pkt_len;
2642 __le16 len_on_bd;
2643 struct parsing_flags pars_flags;
2644 union eth_sgl_or_raw_data sgl_or_raw_data;
2645};
2646
2647
2648
2649
2650
2651struct eth_halt_ramrod_data {
2652 u32 client_id;
2653 u32 reserved0;
2654};
2655
2656
2657
2658
2659struct common_query_ramrod_data {
2660#if defined(__BIG_ENDIAN)
2661 u8 reserved0;
2662 u8 collect_port;
2663 u16 drv_counter;
2664#elif defined(__LITTLE_ENDIAN)
2665 u16 drv_counter;
2666 u8 collect_port;
2667 u8 reserved0;
2668#endif
2669 u32 ctr_id_vector;
2670};
2671
2672
2673
2674
2675
2676struct ramrod_data {
2677 __le32 data_lo;
2678 __le32 data_hi;
2679};
2680
2681
2682
2683
2684union eth_ramrod_data {
2685 struct ramrod_data general;
2686};
2687
2688
2689
2690
2691
2692struct common_ramrod_eth_rx_cqe {
2693 u8 ramrod_type;
2694#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0)
2695#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
2696#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<1)
2697#define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 1
2698#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x3F<<2)
2699#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 2
2700 u8 conn_type;
2701 __le16 reserved1;
2702 __le32 conn_and_cmd_data;
2703#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
2704#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
2705#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
2706#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
2707 struct ramrod_data protocol_data;
2708 __le32 reserved2[4];
2709};
2710
2711
2712
2713
2714struct eth_rx_cqe_next_page {
2715 __le32 addr_lo;
2716 __le32 addr_hi;
2717 __le32 reserved[6];
2718};
2719
2720
2721
2722
2723union eth_rx_cqe {
2724 struct eth_fast_path_rx_cqe fast_path_cqe;
2725 struct common_ramrod_eth_rx_cqe ramrod_cqe;
2726 struct eth_rx_cqe_next_page next_page_cqe;
2727};
2728
2729
2730
2731
2732
2733struct spe_hdr {
2734 __le32 conn_and_cmd_data;
2735#define SPE_HDR_CID (0xFFFFFF<<0)
2736#define SPE_HDR_CID_SHIFT 0
2737#define SPE_HDR_CMD_ID (0xFF<<24)
2738#define SPE_HDR_CMD_ID_SHIFT 24
2739 __le16 type;
2740#define SPE_HDR_CONN_TYPE (0xFF<<0)
2741#define SPE_HDR_CONN_TYPE_SHIFT 0
2742#define SPE_HDR_FUNCTION_ID (0xFF<<8)
2743#define SPE_HDR_FUNCTION_ID_SHIFT 8
2744 __le16 reserved1;
2745};
2746
2747
2748
2749
2750union eth_specific_data {
2751 u8 protocol_data[8];
2752 struct regpair client_init_ramrod_init_data;
2753 struct eth_halt_ramrod_data halt_ramrod_data;
2754 struct regpair update_data_addr;
2755 struct eth_common_ramrod_data common_ramrod_data;
2756};
2757
2758
2759
2760
2761struct eth_spe {
2762 struct spe_hdr hdr;
2763 union eth_specific_data data;
2764};
2765
2766
2767
2768
2769
2770struct eth_tx_bds_array {
2771 union eth_tx_bd_types bds[13];
2772};
2773
2774
2775
2776
2777
2778struct tstorm_eth_function_common_config {
2779#if defined(__BIG_ENDIAN)
2780 u8 reserved1;
2781 u8 rss_result_mask;
2782 u16 config_flags;
2783#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2784#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2785#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2786#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2787#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2788#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2789#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2790#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2791#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2792#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2793#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<7)
2794#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 7
2795#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<8)
2796#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 8
2797#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x7F<<9)
2798#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 9
2799#elif defined(__LITTLE_ENDIAN)
2800 u16 config_flags;
2801#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2802#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2803#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2804#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2805#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2806#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2807#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2808#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2809#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2810#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2811#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<7)
2812#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 7
2813#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<8)
2814#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 8
2815#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x7F<<9)
2816#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 9
2817 u8 rss_result_mask;
2818 u8 reserved1;
2819#endif
2820 u16 vlan_id[2];
2821};
2822
2823
2824
2825
2826struct rss_update_config {
2827#if defined(__BIG_ENDIAN)
2828 u16 toe_rss_bitmap;
2829 u16 flags;
2830#define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0)
2831#define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0
2832#define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1)
2833#define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1
2834#define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2)
2835#define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2
2836#elif defined(__LITTLE_ENDIAN)
2837 u16 flags;
2838#define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0)
2839#define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0
2840#define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1)
2841#define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1
2842#define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2)
2843#define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2
2844 u16 toe_rss_bitmap;
2845#endif
2846 u32 reserved1;
2847};
2848
2849
2850
2851
2852struct eth_update_ramrod_data {
2853 struct tstorm_eth_function_common_config func_config;
2854 u8 indirectionTable[128];
2855 struct rss_update_config rss_config;
2856};
2857
2858
2859
2860
2861
2862struct mac_configuration_hdr {
2863 u8 length;
2864 u8 offset;
2865 u16 client_id;
2866 u16 echo;
2867 u16 reserved1;
2868};
2869
2870
2871
2872
2873struct mac_configuration_entry {
2874 __le16 lsb_mac_addr;
2875 __le16 middle_mac_addr;
2876 __le16 msb_mac_addr;
2877 __le16 vlan_id;
2878 u8 pf_id;
2879 u8 flags;
2880#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
2881#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
2882#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
2883#define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
2884#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
2885#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
2886#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
2887#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
2888#define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
2889#define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
2890#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
2891#define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
2892 u16 reserved0;
2893 u32 clients_bit_vector;
2894};
2895
2896
2897
2898
2899struct mac_configuration_cmd {
2900 struct mac_configuration_hdr hdr;
2901 struct mac_configuration_entry config_table[64];
2902};
2903
2904
2905
2906
2907
2908struct tstorm_eth_approximate_match_multicast_filtering {
2909 u32 mcast_add_hash_bit_array[8];
2910};
2911
2912
2913
2914
2915
2916struct tstorm_eth_mac_filter_config {
2917 u32 ucast_drop_all;
2918 u32 ucast_accept_all;
2919 u32 mcast_drop_all;
2920 u32 mcast_accept_all;
2921 u32 bcast_drop_all;
2922 u32 bcast_accept_all;
2923 u32 vlan_filter[2];
2924 u32 unmatched_unicast;
2925 u32 reserved;
2926};
2927
2928
2929
2930
2931
2932struct tstorm_eth_tpa_exist {
2933#if defined(__BIG_ENDIAN)
2934 u16 reserved1;
2935 u8 reserved0;
2936 u8 tpa_exist;
2937#elif defined(__LITTLE_ENDIAN)
2938 u8 tpa_exist;
2939 u8 reserved0;
2940 u16 reserved1;
2941#endif
2942 u32 reserved2;
2943};
2944
2945
2946
2947
2948
2949struct ustorm_eth_rx_producers {
2950#if defined(__BIG_ENDIAN)
2951 u16 bd_prod;
2952 u16 cqe_prod;
2953#elif defined(__LITTLE_ENDIAN)
2954 u16 cqe_prod;
2955 u16 bd_prod;
2956#endif
2957#if defined(__BIG_ENDIAN)
2958 u16 reserved;
2959 u16 sge_prod;
2960#elif defined(__LITTLE_ENDIAN)
2961 u16 sge_prod;
2962 u16 reserved;
2963#endif
2964};
2965
2966
2967
2968
2969
2970struct cfc_del_event_data {
2971 u32 cid;
2972 u8 error;
2973 u8 reserved0;
2974 u16 reserved1;
2975 u32 reserved2;
2976};
2977
2978
2979
2980
2981
2982struct cmng_flags_per_port {
2983 u8 con_number[NUM_OF_PROTOCOLS];
2984 u32 cmng_enables;
2985#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
2986#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
2987#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
2988#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
2989#define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL (0x1<<2)
2990#define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL_SHIFT 2
2991#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL (0x1<<3)
2992#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL_SHIFT 3
2993#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<4)
2994#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 4
2995#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<5)
2996#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 5
2997#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0x3FFFFFF<<6)
2998#define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 6
2999};
3000
3001
3002
3003
3004
3005struct rate_shaping_vars_per_port {
3006 u32 rs_periodic_timeout;
3007 u32 rs_threshold;
3008};
3009
3010
3011
3012
3013struct fairness_vars_per_port {
3014 u32 upper_bound;
3015 u32 fair_threshold;
3016 u32 fairness_timeout;
3017};
3018
3019
3020
3021
3022struct safc_struct_per_port {
3023#if defined(__BIG_ENDIAN)
3024 u16 __reserved1;
3025 u8 __reserved0;
3026 u8 safc_timeout_usec;
3027#elif defined(__LITTLE_ENDIAN)
3028 u8 safc_timeout_usec;
3029 u8 __reserved0;
3030 u16 __reserved1;
3031#endif
3032 u8 cos_to_traffic_types[MAX_COS_NUMBER];
3033 u32 __reserved2;
3034 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
3035};
3036
3037
3038
3039
3040struct pfc_struct_per_port {
3041 u8 priority_to_traffic_types[MAX_PFC_PRIORITIES];
3042#if defined(__BIG_ENDIAN)
3043 u16 pfc_pause_quanta_in_nanosec;
3044 u8 __reserved0;
3045 u8 priority_non_pausable_mask;
3046#elif defined(__LITTLE_ENDIAN)
3047 u8 priority_non_pausable_mask;
3048 u8 __reserved0;
3049 u16 pfc_pause_quanta_in_nanosec;
3050#endif
3051};
3052
3053
3054
3055
3056struct priority_cos {
3057#if defined(__BIG_ENDIAN)
3058 u16 reserved1;
3059 u8 cos;
3060 u8 priority;
3061#elif defined(__LITTLE_ENDIAN)
3062 u8 priority;
3063 u8 cos;
3064 u16 reserved1;
3065#endif
3066 u32 reserved2;
3067};
3068
3069
3070
3071
3072struct cmng_struct_per_port {
3073 struct rate_shaping_vars_per_port rs_vars;
3074 struct fairness_vars_per_port fair_vars;
3075 struct safc_struct_per_port safc_vars;
3076 struct pfc_struct_per_port pfc_vars;
3077#if defined(__BIG_ENDIAN)
3078 u16 __reserved1;
3079 u8 dcb_enabled;
3080 u8 llfc_mode;
3081#elif defined(__LITTLE_ENDIAN)
3082 u8 llfc_mode;
3083 u8 dcb_enabled;
3084 u16 __reserved1;
3085#endif
3086 struct priority_cos
3087 traffic_type_to_priority_cos[MAX_PFC_TRAFFIC_TYPES];
3088 struct cmng_flags_per_port flags;
3089};
3090
3091
3092
3093
3094
3095
3096struct hc_dynamic_drv_counter {
3097 u32 val[HC_SB_MAX_DYNAMIC_INDICES];
3098};
3099
3100
3101
3102
3103struct cstorm_queue_zone_data {
3104 struct hc_dynamic_drv_counter hc_dyn_drv_cnt;
3105 struct regpair reserved[2];
3106};
3107
3108
3109
3110
3111struct dynamic_hc_config {
3112 u32 threshold[3];
3113 u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];
3114 u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];
3115 u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];
3116 u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];
3117 u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];
3118};
3119
3120
3121
3122
3123
3124struct xstorm_per_client_stats {
3125 __le32 reserved0;
3126 __le32 unicast_pkts_sent;
3127 struct regpair unicast_bytes_sent;
3128 struct regpair multicast_bytes_sent;
3129 __le32 multicast_pkts_sent;
3130 __le32 broadcast_pkts_sent;
3131 struct regpair broadcast_bytes_sent;
3132 __le16 stats_counter;
3133 __le16 reserved1;
3134 __le32 reserved2;
3135};
3136
3137
3138
3139
3140struct xstorm_common_stats {
3141 struct xstorm_per_client_stats client_statistics[MAX_STAT_COUNTER_ID];
3142};
3143
3144
3145
3146
3147struct tstorm_per_port_stats {
3148 __le32 mac_filter_discard;
3149 __le32 xxoverflow_discard;
3150 __le32 brb_truncate_discard;
3151 __le32 mac_discard;
3152};
3153
3154
3155
3156
3157struct tstorm_per_client_stats {
3158 struct regpair rcv_unicast_bytes;
3159 struct regpair rcv_broadcast_bytes;
3160 struct regpair rcv_multicast_bytes;
3161 struct regpair rcv_error_bytes;
3162 __le32 checksum_discard;
3163 __le32 packets_too_big_discard;
3164 __le32 rcv_unicast_pkts;
3165 __le32 rcv_broadcast_pkts;
3166 __le32 rcv_multicast_pkts;
3167 __le32 no_buff_discard;
3168 __le32 ttl0_discard;
3169 __le16 stats_counter;
3170 __le16 reserved0;
3171};
3172
3173
3174
3175
3176struct tstorm_common_stats {
3177 struct tstorm_per_port_stats port_statistics;
3178 struct tstorm_per_client_stats client_statistics[MAX_STAT_COUNTER_ID];
3179};
3180
3181
3182
3183
3184struct ustorm_per_client_stats {
3185 struct regpair ucast_no_buff_bytes;
3186 struct regpair mcast_no_buff_bytes;
3187 struct regpair bcast_no_buff_bytes;
3188 __le32 ucast_no_buff_pkts;
3189 __le32 mcast_no_buff_pkts;
3190 __le32 bcast_no_buff_pkts;
3191 __le16 stats_counter;
3192 __le16 reserved0;
3193};
3194
3195
3196
3197
3198struct ustorm_common_stats {
3199 struct ustorm_per_client_stats client_statistics[MAX_STAT_COUNTER_ID];
3200};
3201
3202
3203
3204
3205struct eth_stats_query {
3206 struct xstorm_common_stats xstorm_common;
3207 struct tstorm_common_stats tstorm_common;
3208 struct ustorm_common_stats ustorm_common;
3209};
3210
3211
3212
3213
3214
3215struct set_mac_event_data {
3216 u16 echo;
3217 u16 reserved0;
3218 u32 reserved1;
3219 u32 reserved2;
3220};
3221
3222
3223
3224
3225union event_data {
3226 struct set_mac_event_data set_mac_event;
3227 struct cfc_del_event_data cfc_del_event;
3228};
3229
3230
3231
3232
3233
3234struct event_ring_data {
3235 struct regpair base_addr;
3236#if defined(__BIG_ENDIAN)
3237 u8 index_id;
3238 u8 sb_id;
3239 u16 producer;
3240#elif defined(__LITTLE_ENDIAN)
3241 u16 producer;
3242 u8 sb_id;
3243 u8 index_id;
3244#endif
3245 u32 reserved0;
3246};
3247
3248
3249
3250
3251
3252struct event_ring_msg {
3253 u8 opcode;
3254 u8 reserved0;
3255 u16 reserved1;
3256 union event_data data;
3257};
3258
3259
3260
3261
3262struct event_ring_next {
3263 struct regpair addr;
3264 u32 reserved[2];
3265};
3266
3267
3268
3269
3270union event_ring_elem {
3271 struct event_ring_msg message;
3272 struct event_ring_next next_page;
3273};
3274
3275
3276
3277
3278
3279struct fairness_vars_per_vn {
3280 u32 cos_credit_delta[MAX_COS_NUMBER];
3281 u32 protocol_credit_delta[NUM_OF_PROTOCOLS];
3282 u32 vn_credit_delta;
3283 u32 __reserved0;
3284};
3285
3286
3287
3288
3289
3290struct flow_control_configuration {
3291 struct priority_cos
3292 traffic_type_to_priority_cos[MAX_PFC_TRAFFIC_TYPES];
3293#if defined(__BIG_ENDIAN)
3294 u16 reserved1;
3295 u8 dcb_version;
3296 u8 dcb_enabled;
3297#elif defined(__LITTLE_ENDIAN)
3298 u8 dcb_enabled;
3299 u8 dcb_version;
3300 u16 reserved1;
3301#endif
3302 u32 reserved2;
3303};
3304
3305
3306
3307
3308
3309struct fw_version {
3310#if defined(__BIG_ENDIAN)
3311 u8 engineering;
3312 u8 revision;
3313 u8 minor;
3314 u8 major;
3315#elif defined(__LITTLE_ENDIAN)
3316 u8 major;
3317 u8 minor;
3318 u8 revision;
3319 u8 engineering;
3320#endif
3321 u32 flags;
3322#define FW_VERSION_OPTIMIZED (0x1<<0)
3323#define FW_VERSION_OPTIMIZED_SHIFT 0
3324#define FW_VERSION_BIG_ENDIEN (0x1<<1)
3325#define FW_VERSION_BIG_ENDIEN_SHIFT 1
3326#define FW_VERSION_CHIP_VERSION (0x3<<2)
3327#define FW_VERSION_CHIP_VERSION_SHIFT 2
3328#define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
3329#define __FW_VERSION_RESERVED_SHIFT 4
3330};
3331
3332
3333
3334
3335
3336struct hc_dynamic_sb_drv_counters {
3337 u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];
3338};
3339
3340
3341
3342
3343
3344struct hc_index_data {
3345#if defined(__BIG_ENDIAN)
3346 u8 flags;
3347#define HC_INDEX_DATA_SM_ID (0x1<<0)
3348#define HC_INDEX_DATA_SM_ID_SHIFT 0
3349#define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
3350#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
3351#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
3352#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
3353#define HC_INDEX_DATA_RESERVE (0x1F<<3)
3354#define HC_INDEX_DATA_RESERVE_SHIFT 3
3355 u8 timeout;
3356#elif defined(__LITTLE_ENDIAN)
3357 u8 timeout;
3358 u8 flags;
3359#define HC_INDEX_DATA_SM_ID (0x1<<0)
3360#define HC_INDEX_DATA_SM_ID_SHIFT 0
3361#define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
3362#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
3363#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
3364#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
3365#define HC_INDEX_DATA_RESERVE (0x1F<<3)
3366#define HC_INDEX_DATA_RESERVE_SHIFT 3
3367#endif
3368};
3369
3370
3371
3372
3373
3374struct hc_status_block_sm {
3375#if defined(__BIG_ENDIAN)
3376 u8 igu_seg_id;
3377 u8 igu_sb_id;
3378 u8 timer_value;
3379 u8 __flags;
3380#elif defined(__LITTLE_ENDIAN)
3381 u8 __flags;
3382 u8 timer_value;
3383 u8 igu_sb_id;
3384 u8 igu_seg_id;
3385#endif
3386 u32 time_to_expire;
3387};
3388
3389
3390
3391
3392struct pci_entity {
3393#if defined(__BIG_ENDIAN)
3394 u8 vf_valid;
3395 u8 vf_id;
3396 u8 vnic_id;
3397 u8 pf_id;
3398#elif defined(__LITTLE_ENDIAN)
3399 u8 pf_id;
3400 u8 vnic_id;
3401 u8 vf_id;
3402 u8 vf_valid;
3403#endif
3404};
3405
3406
3407
3408
3409struct hc_sb_data {
3410 struct regpair host_sb_addr;
3411 struct hc_status_block_sm state_machine[HC_SB_MAX_SM];
3412 struct pci_entity p_func;
3413#if defined(__BIG_ENDIAN)
3414 u8 rsrv0;
3415 u8 dhc_qzone_id;
3416 u8 __dynamic_hc_level;
3417 u8 same_igu_sb_1b;
3418#elif defined(__LITTLE_ENDIAN)
3419 u8 same_igu_sb_1b;
3420 u8 __dynamic_hc_level;
3421 u8 dhc_qzone_id;
3422 u8 rsrv0;
3423#endif
3424 struct regpair rsrv1[2];
3425};
3426
3427
3428
3429
3430
3431struct hc_sp_status_block_data {
3432 struct regpair host_sb_addr;
3433#if defined(__BIG_ENDIAN)
3434 u16 rsrv;
3435 u8 igu_seg_id;
3436 u8 igu_sb_id;
3437#elif defined(__LITTLE_ENDIAN)
3438 u8 igu_sb_id;
3439 u8 igu_seg_id;
3440 u16 rsrv;
3441#endif
3442 struct pci_entity p_func;
3443};
3444
3445
3446
3447
3448
3449struct hc_status_block_data_e1x {
3450 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X];
3451 struct hc_sb_data common;
3452};
3453
3454
3455
3456
3457
3458struct hc_status_block_data_e2 {
3459 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2];
3460 struct hc_sb_data common;
3461};
3462
3463
3464
3465
3466
3467struct pram_fw_version {
3468 u8 major;
3469 u8 minor;
3470 u8 revision;
3471 u8 engineering;
3472 u8 flags;
3473#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
3474#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
3475#define PRAM_FW_VERSION_STORM_ID (0x3<<1)
3476#define PRAM_FW_VERSION_STORM_ID_SHIFT 1
3477#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
3478#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
3479#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
3480#define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
3481#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
3482#define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
3483};
3484
3485
3486
3487
3488
3489union protocol_common_specific_data {
3490 u8 protocol_data[8];
3491 struct regpair phy_address;
3492 struct regpair mac_config_addr;
3493 struct common_query_ramrod_data query_ramrod_data;
3494};
3495
3496
3497
3498
3499struct protocol_common_spe {
3500 struct spe_hdr hdr;
3501 union protocol_common_specific_data data;
3502};
3503
3504
3505
3506
3507
3508struct rate_shaping_counter {
3509 u32 quota;
3510#if defined(__BIG_ENDIAN)
3511 u16 __reserved0;
3512 u16 rate;
3513#elif defined(__LITTLE_ENDIAN)
3514 u16 rate;
3515 u16 __reserved0;
3516#endif
3517};
3518
3519
3520
3521
3522
3523struct rate_shaping_vars_per_vn {
3524 struct rate_shaping_counter protocol_counters[NUM_OF_PROTOCOLS];
3525 struct rate_shaping_counter vn_counter;
3526};
3527
3528
3529
3530
3531
3532struct slow_path_element {
3533 struct spe_hdr hdr;
3534 struct regpair protocol_data;
3535};
3536
3537
3538
3539
3540
3541struct stats_indication_flags {
3542 u32 collect_eth;
3543 u32 collect_toe;
3544};
3545
3546
3547
3548
3549
3550struct storm_pfc_struct_per_port {
3551#if defined(__BIG_ENDIAN)
3552 u16 mid_mac_addr;
3553 u16 msb_mac_addr;
3554#elif defined(__LITTLE_ENDIAN)
3555 u16 msb_mac_addr;
3556 u16 mid_mac_addr;
3557#endif
3558#if defined(__BIG_ENDIAN)
3559 u16 pfc_pause_quanta_in_nanosec;
3560 u16 lsb_mac_addr;
3561#elif defined(__LITTLE_ENDIAN)
3562 u16 lsb_mac_addr;
3563 u16 pfc_pause_quanta_in_nanosec;
3564#endif
3565};
3566
3567
3568
3569
3570struct storm_cmng_struct_per_port {
3571 struct storm_pfc_struct_per_port pfc_vars;
3572};
3573
3574
3575
3576
3577
3578struct tstorm_queue_zone_data {
3579 struct regpair reserved[4];
3580};
3581
3582
3583
3584
3585
3586struct tstorm_vf_zone_data {
3587 struct regpair reserved;
3588};
3589
3590
3591
3592
3593
3594struct ustorm_queue_zone_data {
3595 struct ustorm_eth_rx_producers eth_rx_producers;
3596 struct regpair reserved[3];
3597};
3598
3599
3600
3601
3602
3603struct ustorm_vf_zone_data {
3604 struct regpair reserved;
3605};
3606
3607
3608
3609
3610
3611struct vf_pf_channel_data {
3612#if defined(__BIG_ENDIAN)
3613 u16 reserved0;
3614 u8 valid;
3615 u8 state;
3616#elif defined(__LITTLE_ENDIAN)
3617 u8 state;
3618 u8 valid;
3619 u16 reserved0;
3620#endif
3621 u32 reserved1;
3622};
3623
3624
3625
3626
3627
3628struct xstorm_queue_zone_data {
3629 struct regpair reserved[4];
3630};
3631
3632
3633
3634
3635
3636struct xstorm_vf_zone_data {
3637 struct regpair reserved;
3638};
3639
3640#endif
3641