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12#ifndef CNIC_H
13#define CNIC_H
14
15#define HC_INDEX_ISCSI_EQ_CONS 6
16
17#define HC_INDEX_FCOE_EQ_CONS 3
18
19#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
20#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
21
22#define KWQ_PAGE_CNT 4
23#define KCQ_PAGE_CNT 16
24
25#define KWQ_CID 24
26#define KCQ_CID 25
27
28
29
30
31#define L5_KRNLQ_FLAGS 0x00000000
32#define L5_KRNLQ_SIZE 0x00000000
33#define L5_KRNLQ_TYPE 0x00000000
34#define KRNLQ_FLAGS_PG_SZ (0xf<<0)
35#define KRNLQ_FLAGS_PG_SZ_256 (0<<0)
36#define KRNLQ_FLAGS_PG_SZ_512 (1<<0)
37#define KRNLQ_FLAGS_PG_SZ_1K (2<<0)
38#define KRNLQ_FLAGS_PG_SZ_2K (3<<0)
39#define KRNLQ_FLAGS_PG_SZ_4K (4<<0)
40#define KRNLQ_FLAGS_PG_SZ_8K (5<<0)
41#define KRNLQ_FLAGS_PG_SZ_16K (6<<0)
42#define KRNLQ_FLAGS_PG_SZ_32K (7<<0)
43#define KRNLQ_FLAGS_PG_SZ_64K (8<<0)
44#define KRNLQ_FLAGS_PG_SZ_128K (9<<0)
45#define KRNLQ_FLAGS_PG_SZ_256K (10<<0)
46#define KRNLQ_FLAGS_PG_SZ_512K (11<<0)
47#define KRNLQ_FLAGS_PG_SZ_1M (12<<0)
48#define KRNLQ_FLAGS_PG_SZ_2M (13<<0)
49#define KRNLQ_FLAGS_QE_SELF_SEQ (1<<15)
50#define KRNLQ_SIZE_TYPE_SIZE ((((0x28 + 0x1f) & ~0x1f) / 0x20) << 16)
51#define KRNLQ_TYPE_TYPE (0xf<<28)
52#define KRNLQ_TYPE_TYPE_EMPTY (0<<28)
53#define KRNLQ_TYPE_TYPE_KRNLQ (6<<28)
54
55#define L5_KRNLQ_HOST_QIDX 0x00000004
56#define L5_KRNLQ_HOST_FW_QIDX 0x00000008
57#define L5_KRNLQ_NX_QE_SELF_SEQ 0x0000000c
58#define L5_KRNLQ_QE_SELF_SEQ_MAX 0x0000000c
59#define L5_KRNLQ_NX_QE_HADDR_HI 0x00000010
60#define L5_KRNLQ_NX_QE_HADDR_LO 0x00000014
61#define L5_KRNLQ_PGTBL_PGIDX 0x00000018
62#define L5_KRNLQ_NX_PG_QIDX 0x00000018
63#define L5_KRNLQ_PGTBL_NPAGES 0x0000001c
64#define L5_KRNLQ_QIDX_INCR 0x0000001c
65#define L5_KRNLQ_PGTBL_HADDR_HI 0x00000020
66#define L5_KRNLQ_PGTBL_HADDR_LO 0x00000024
67
68#define BNX2_PG_CTX_MAP 0x1a0034
69#define BNX2_ISCSI_CTX_MAP 0x1a0074
70
71struct cnic_redirect_entry {
72 struct dst_entry *old_dst;
73 struct dst_entry *new_dst;
74};
75
76#define MAX_COMPLETED_KCQE 64
77
78#define MAX_CNIC_L5_CONTEXT 256
79
80#define MAX_CM_SK_TBL_SZ MAX_CNIC_L5_CONTEXT
81
82#define MAX_ISCSI_TBL_SZ 256
83
84#define CNIC_LOCAL_PORT_MIN 60000
85#define CNIC_LOCAL_PORT_MAX 61024
86#define CNIC_LOCAL_PORT_RANGE (CNIC_LOCAL_PORT_MAX - CNIC_LOCAL_PORT_MIN)
87
88#define KWQE_CNT (BCM_PAGE_SIZE / sizeof(struct kwqe))
89#define KCQE_CNT (BCM_PAGE_SIZE / sizeof(struct kcqe))
90#define MAX_KWQE_CNT (KWQE_CNT - 1)
91#define MAX_KCQE_CNT (KCQE_CNT - 1)
92
93#define MAX_KWQ_IDX ((KWQ_PAGE_CNT * KWQE_CNT) - 1)
94#define MAX_KCQ_IDX ((KCQ_PAGE_CNT * KCQE_CNT) - 1)
95
96#define KWQ_PG(x) (((x) & ~MAX_KWQE_CNT) >> (BCM_PAGE_BITS - 5))
97#define KWQ_IDX(x) ((x) & MAX_KWQE_CNT)
98
99#define KCQ_PG(x) (((x) & ~MAX_KCQE_CNT) >> (BCM_PAGE_BITS - 5))
100#define KCQ_IDX(x) ((x) & MAX_KCQE_CNT)
101
102#define BNX2X_NEXT_KCQE(x) (((x) & (MAX_KCQE_CNT - 1)) == \
103 (MAX_KCQE_CNT - 1)) ? \
104 (x) + 2 : (x) + 1
105
106#define BNX2X_KWQ_DATA_PG(cp, x) ((x) / (cp)->kwq_16_data_pp)
107#define BNX2X_KWQ_DATA_IDX(cp, x) ((x) % (cp)->kwq_16_data_pp)
108#define BNX2X_KWQ_DATA(cp, x) \
109 &(cp)->kwq_16_data[BNX2X_KWQ_DATA_PG(cp, x)][BNX2X_KWQ_DATA_IDX(cp, x)]
110
111#define DEF_IPID_START 0x8000
112
113#define DEF_KA_TIMEOUT 10000
114#define DEF_KA_INTERVAL 300000
115#define DEF_KA_MAX_PROBE_COUNT 3
116#define DEF_TOS 0
117#define DEF_TTL 0xfe
118#define DEF_SND_SEQ_SCALE 0
119#define DEF_RCV_BUF 0xffff
120#define DEF_SND_BUF 0xffff
121#define DEF_SEED 0
122#define DEF_MAX_RT_TIME 500
123#define DEF_MAX_DA_COUNT 2
124#define DEF_SWS_TIMER 1000
125#define DEF_MAX_CWND 0xffff
126
127struct cnic_ctx {
128 u32 cid;
129 void *ctx;
130 dma_addr_t mapping;
131};
132
133#define BNX2_MAX_CID 0x2000
134
135struct cnic_dma {
136 int num_pages;
137 void **pg_arr;
138 dma_addr_t *pg_map_arr;
139 int pgtbl_size;
140 u32 *pgtbl;
141 dma_addr_t pgtbl_map;
142};
143
144struct cnic_id_tbl {
145 spinlock_t lock;
146 u32 start;
147 u32 max;
148 u32 next;
149 unsigned long *table;
150};
151
152#define CNIC_KWQ16_DATA_SIZE 128
153
154struct kwqe_16_data {
155 u8 data[CNIC_KWQ16_DATA_SIZE];
156};
157
158struct cnic_iscsi {
159 struct cnic_dma task_array_info;
160 struct cnic_dma r2tq_info;
161 struct cnic_dma hq_info;
162};
163
164struct cnic_context {
165 u32 cid;
166 struct kwqe_16_data *kwqe_data;
167 dma_addr_t kwqe_data_mapping;
168 wait_queue_head_t waitq;
169 int wait_cond;
170 unsigned long timestamp;
171 unsigned long ctx_flags;
172#define CTX_FL_OFFLD_START 0
173#define CTX_FL_DELETE_WAIT 1
174 u8 ulp_proto_id;
175 union {
176 struct cnic_iscsi *iscsi;
177 } proto;
178};
179
180struct kcq_info {
181 struct cnic_dma dma;
182 struct kcqe **kcq;
183
184 u16 *hw_prod_idx_ptr;
185 u16 sw_prod_idx;
186 u16 *status_idx_ptr;
187 u32 io_addr;
188};
189
190struct iro {
191 u32 base;
192 u16 m1;
193 u16 m2;
194 u16 m3;
195 u16 size;
196};
197
198struct cnic_uio_dev {
199 struct uio_info cnic_uinfo;
200 u32 uio_dev;
201
202 int l2_ring_size;
203 void *l2_ring;
204 dma_addr_t l2_ring_map;
205
206 int l2_buf_size;
207 void *l2_buf;
208 dma_addr_t l2_buf_map;
209
210 struct cnic_dev *dev;
211 struct pci_dev *pdev;
212 struct list_head list;
213};
214
215struct cnic_local {
216
217 spinlock_t cnic_ulp_lock;
218 void *ulp_handle[MAX_CNIC_ULP_TYPE];
219 unsigned long ulp_flags[MAX_CNIC_ULP_TYPE];
220#define ULP_F_INIT 0
221#define ULP_F_START 1
222#define ULP_F_CALL_PENDING 2
223 struct cnic_ulp_ops *ulp_ops[MAX_CNIC_ULP_TYPE];
224
225 unsigned long cnic_local_flags;
226#define CNIC_LCL_FL_KWQ_INIT 0x0
227#define CNIC_LCL_FL_L2_WAIT 0x1
228#define CNIC_LCL_FL_RINGS_INITED 0x2
229
230 struct cnic_dev *dev;
231
232 struct cnic_eth_dev *ethdev;
233
234 struct cnic_uio_dev *udev;
235
236 int l2_rx_ring_size;
237 int l2_single_buf_size;
238
239 u16 *rx_cons_ptr;
240 u16 *tx_cons_ptr;
241 u16 rx_cons;
242 u16 tx_cons;
243
244 struct iro *iro_arr;
245#define IRO (((struct cnic_local *) dev->cnic_priv)->iro_arr)
246
247 struct cnic_dma kwq_info;
248 struct kwqe **kwq;
249
250 struct cnic_dma kwq_16_data_info;
251
252 u16 max_kwq_idx;
253
254 u16 kwq_prod_idx;
255 u32 kwq_io_addr;
256
257 u16 *kwq_con_idx_ptr;
258 u16 kwq_con_idx;
259
260 struct kcq_info kcq1;
261 struct kcq_info kcq2;
262
263 union {
264 void *gen;
265 struct status_block_msix *bnx2;
266 struct host_hc_status_block_e1x *bnx2x_e1x;
267
268 #define SM_RX_ID 0
269 #define SM_TX_ID 1
270 } status_blk;
271
272 struct host_sp_status_block *bnx2x_def_status_blk;
273
274 u32 status_blk_num;
275 u32 bnx2x_igu_sb_id;
276 u32 int_num;
277 u32 last_status_idx;
278 struct tasklet_struct cnic_irq_task;
279
280 struct kcqe *completed_kcq[MAX_COMPLETED_KCQE];
281
282 struct cnic_sock *csk_tbl;
283 struct cnic_id_tbl csk_port_tbl;
284
285 struct cnic_dma conn_buf_info;
286 struct cnic_dma gbl_buf_info;
287
288 struct cnic_iscsi *iscsi_tbl;
289 struct cnic_context *ctx_tbl;
290 struct cnic_id_tbl cid_tbl;
291 atomic_t iscsi_conn;
292 u32 iscsi_start_cid;
293
294 u32 fcoe_init_cid;
295 u32 fcoe_start_cid;
296 struct cnic_id_tbl fcoe_cid_tbl;
297
298 u32 max_cid_space;
299
300
301 int num_iscsi_tasks;
302 int num_ccells;
303 int task_array_size;
304 int r2tq_size;
305 int hq_size;
306 int num_cqs;
307
308 struct delayed_work delete_task;
309
310 struct cnic_ctx *ctx_arr;
311 int ctx_blks;
312 int ctx_blk_size;
313 unsigned long ctx_align;
314 int cids_per_blk;
315
316 u32 chip_id;
317 int func;
318 u32 pfid;
319 u32 shmem_base;
320
321 struct cnic_ops *cnic_ops;
322 int (*start_hw)(struct cnic_dev *);
323 void (*stop_hw)(struct cnic_dev *);
324 void (*setup_pgtbl)(struct cnic_dev *,
325 struct cnic_dma *);
326 int (*alloc_resc)(struct cnic_dev *);
327 void (*free_resc)(struct cnic_dev *);
328 int (*start_cm)(struct cnic_dev *);
329 void (*stop_cm)(struct cnic_dev *);
330 void (*enable_int)(struct cnic_dev *);
331 void (*disable_int_sync)(struct cnic_dev *);
332 void (*ack_int)(struct cnic_dev *);
333 void (*close_conn)(struct cnic_sock *, u32 opcode);
334 u16 (*next_idx)(u16);
335 u16 (*hw_idx)(u16);
336};
337
338struct bnx2x_bd_chain_next {
339 u32 addr_lo;
340 u32 addr_hi;
341 u8 reserved[8];
342};
343
344#define ISCSI_DEFAULT_MAX_OUTSTANDING_R2T (1)
345
346#define ISCSI_RAMROD_CMD_ID_UPDATE_CONN (ISCSI_KCQE_OPCODE_UPDATE_CONN)
347#define ISCSI_RAMROD_CMD_ID_INIT (ISCSI_KCQE_OPCODE_INIT)
348
349#define CDU_REGION_NUMBER_XCM_AG 2
350#define CDU_REGION_NUMBER_UCM_AG 4
351
352#define CDU_VALID_DATA(_cid, _region, _type) \
353 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
354
355#define CDU_CRC8(_cid, _region, _type) \
356 (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
357
358#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \
359 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
360
361#define BNX2X_CONTEXT_MEM_SIZE 1024
362#define BNX2X_FCOE_CID 16
363
364#define BNX2X_ISCSI_START_CID 18
365#define BNX2X_ISCSI_NUM_CONNECTIONS 128
366#define BNX2X_ISCSI_TASK_CONTEXT_SIZE 128
367#define BNX2X_ISCSI_MAX_PENDING_R2TS 4
368#define BNX2X_ISCSI_R2TQE_SIZE 8
369#define BNX2X_ISCSI_HQ_BD_SIZE 64
370#define BNX2X_ISCSI_CONN_BUF_SIZE 64
371#define BNX2X_ISCSI_GLB_BUF_SIZE 64
372#define BNX2X_ISCSI_PBL_NOT_CACHED 0xff
373#define BNX2X_ISCSI_PDU_HEADER_NOT_CACHED 0xff
374
375#define BNX2X_FCOE_NUM_CONNECTIONS 128
376
377#define BNX2X_FCOE_L5_CID_BASE MAX_ISCSI_TBL_SZ
378
379#define BNX2X_CHIP_NUM_57710 0x164e
380#define BNX2X_CHIP_NUM_57711 0x164f
381#define BNX2X_CHIP_NUM_57711E 0x1650
382#define BNX2X_CHIP_NUM_57712 0x1662
383#define BNX2X_CHIP_NUM_57712E 0x1663
384#define BNX2X_CHIP_NUM_57713 0x1651
385#define BNX2X_CHIP_NUM_57713E 0x1652
386
387#define BNX2X_CHIP_NUM(x) (x >> 16)
388#define BNX2X_CHIP_IS_57710(x) \
389 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57710)
390#define BNX2X_CHIP_IS_57711(x) \
391 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57711)
392#define BNX2X_CHIP_IS_57711E(x) \
393 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57711E)
394#define BNX2X_CHIP_IS_E1H(x) \
395 (BNX2X_CHIP_IS_57711(x) || BNX2X_CHIP_IS_57711E(x))
396#define BNX2X_CHIP_IS_57712(x) \
397 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57712)
398#define BNX2X_CHIP_IS_57712E(x) \
399 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57712E)
400#define BNX2X_CHIP_IS_57713(x) \
401 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57713)
402#define BNX2X_CHIP_IS_57713E(x) \
403 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57713E)
404#define BNX2X_CHIP_IS_E2(x) \
405 (BNX2X_CHIP_IS_57712(x) || BNX2X_CHIP_IS_57712E(x) || \
406 BNX2X_CHIP_IS_57713(x) || BNX2X_CHIP_IS_57713E(x))
407
408#define IS_E1H_OFFSET BNX2X_CHIP_IS_E1H(cp->chip_id)
409
410#define BNX2X_RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
411#define BNX2X_MAX_RX_DESC_CNT (BNX2X_RX_DESC_CNT - 2)
412#define BNX2X_RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
413#define BNX2X_MAX_RCQ_DESC_CNT (BNX2X_RCQ_DESC_CNT - 1)
414
415#define BNX2X_NEXT_RCQE(x) (((x) & BNX2X_MAX_RCQ_DESC_CNT) == \
416 (BNX2X_MAX_RCQ_DESC_CNT - 1)) ? \
417 ((x) + 2) : ((x) + 1)
418
419#define BNX2X_DEF_SB_ID HC_SP_SB_ID
420
421#define BNX2X_SHMEM_MF_BLK_OFFSET 0x7e4
422
423#define BNX2X_SHMEM_ADDR(base, field) (base + \
424 offsetof(struct shmem_region, field))
425
426#define BNX2X_SHMEM2_ADDR(base, field) (base + \
427 offsetof(struct shmem2_region, field))
428
429#define BNX2X_SHMEM2_HAS(base, field) \
430 ((base) && \
431 (CNIC_RD(dev, BNX2X_SHMEM2_ADDR(base, size)) > \
432 offsetof(struct shmem2_region, field)))
433
434#define BNX2X_MF_CFG_ADDR(base, field) \
435 ((base) + offsetof(struct mf_cfg, field))
436
437#ifndef ETH_MAX_RX_CLIENTS_E2
438#define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
439#endif
440
441#define CNIC_PORT(cp) ((cp)->pfid & 1)
442#define CNIC_FUNC(cp) ((cp)->func)
443#define CNIC_PATH(cp) (!BNX2X_CHIP_IS_E2(cp->chip_id) ? 0 :\
444 (CNIC_FUNC(cp) & 1))
445#define CNIC_E1HVN(cp) ((cp)->pfid >> 1)
446
447#define BNX2X_HW_CID(cp, x) ((CNIC_PORT(cp) << 23) | \
448 (CNIC_E1HVN(cp) << 17) | (x))
449
450#define BNX2X_SW_CID(x) (x & 0x1ffff)
451
452#define BNX2X_CL_QZONE_ID(cp, cli) \
453 (cli + (CNIC_PORT(cp) * (BNX2X_CHIP_IS_E2(cp->chip_id) ?\
454 ETH_MAX_RX_CLIENTS_E2 : \
455 ETH_MAX_RX_CLIENTS_E1H)))
456
457#define TCP_TSTORM_OOO_DROP_AND_PROC_ACK (0<<4)
458#endif
459
460
