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36#include <linux/version.h>
37#include <linux/pci.h>
38
39#include "t4vf_common.h"
40#include "t4vf_defs.h"
41
42#include "../cxgb4/t4_regs.h"
43#include "../cxgb4/t4fw_api.h"
44
45
46
47
48
49
50int __devinit t4vf_wait_dev_ready(struct adapter *adapter)
51{
52 const u32 whoami = T4VF_PL_BASE_ADDR + PL_VF_WHOAMI;
53 const u32 notready1 = 0xffffffff;
54 const u32 notready2 = 0xeeeeeeee;
55 u32 val;
56
57 val = t4_read_reg(adapter, whoami);
58 if (val != notready1 && val != notready2)
59 return 0;
60 msleep(500);
61 val = t4_read_reg(adapter, whoami);
62 if (val != notready1 && val != notready2)
63 return 0;
64 else
65 return -EIO;
66}
67
68
69
70
71
72static void get_mbox_rpl(struct adapter *adapter, __be64 *rpl, int size,
73 u32 mbox_data)
74{
75 for ( ; size; size -= 8, mbox_data += 8)
76 *rpl++ = cpu_to_be64(t4_read_reg64(adapter, mbox_data));
77}
78
79
80
81
82static void dump_mbox(struct adapter *adapter, const char *tag, u32 mbox_data)
83{
84 dev_err(adapter->pdev_dev,
85 "mbox %s: %llx %llx %llx %llx %llx %llx %llx %llx\n", tag,
86 (unsigned long long)t4_read_reg64(adapter, mbox_data + 0),
87 (unsigned long long)t4_read_reg64(adapter, mbox_data + 8),
88 (unsigned long long)t4_read_reg64(adapter, mbox_data + 16),
89 (unsigned long long)t4_read_reg64(adapter, mbox_data + 24),
90 (unsigned long long)t4_read_reg64(adapter, mbox_data + 32),
91 (unsigned long long)t4_read_reg64(adapter, mbox_data + 40),
92 (unsigned long long)t4_read_reg64(adapter, mbox_data + 48),
93 (unsigned long long)t4_read_reg64(adapter, mbox_data + 56));
94}
95
96
97
98
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103
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114
115
116int t4vf_wr_mbox_core(struct adapter *adapter, const void *cmd, int size,
117 void *rpl, bool sleep_ok)
118{
119 static const int delay[] = {
120 1, 1, 3, 5, 10, 10, 20, 50, 100
121 };
122
123 u32 v;
124 int i, ms, delay_idx;
125 const __be64 *p;
126 u32 mbox_data = T4VF_MBDATA_BASE_ADDR;
127 u32 mbox_ctl = T4VF_CIM_BASE_ADDR + CIM_VF_EXT_MAILBOX_CTRL;
128
129
130
131
132
133 if ((size % 16) != 0 ||
134 size > NUM_CIM_VF_MAILBOX_DATA_INSTANCES * 4)
135 return -EINVAL;
136
137
138
139
140
141 v = MBOWNER_GET(t4_read_reg(adapter, mbox_ctl));
142 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
143 v = MBOWNER_GET(t4_read_reg(adapter, mbox_ctl));
144 if (v != MBOX_OWNER_DRV)
145 return v == MBOX_OWNER_FW ? -EBUSY : -ETIMEDOUT;
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160 for (i = 0, p = cmd; i < size; i += 8)
161 t4_write_reg64(adapter, mbox_data + i, be64_to_cpu(*p++));
162 t4_read_reg(adapter, mbox_data);
163
164 t4_write_reg(adapter, mbox_ctl,
165 MBMSGVALID | MBOWNER(MBOX_OWNER_FW));
166 t4_read_reg(adapter, mbox_ctl);
167
168
169
170
171 delay_idx = 0;
172 ms = delay[0];
173
174 for (i = 0; i < FW_CMD_MAX_TIMEOUT; i += ms) {
175 if (sleep_ok) {
176 ms = delay[delay_idx];
177 if (delay_idx < ARRAY_SIZE(delay) - 1)
178 delay_idx++;
179 msleep(ms);
180 } else
181 mdelay(ms);
182
183
184
185
186 v = t4_read_reg(adapter, mbox_ctl);
187 if (MBOWNER_GET(v) == MBOX_OWNER_DRV) {
188
189
190
191
192 if ((v & MBMSGVALID) == 0) {
193 t4_write_reg(adapter, mbox_ctl,
194 MBOWNER(MBOX_OWNER_NONE));
195 continue;
196 }
197
198
199
200
201
202
203
204
205
206
207 v = t4_read_reg(adapter, mbox_data);
208 if (FW_CMD_RETVAL_GET(v))
209 dump_mbox(adapter, "FW Error", mbox_data);
210
211 if (rpl) {
212
213 WARN_ON((be32_to_cpu(*(const u32 *)cmd)
214 & FW_CMD_REQUEST) == 0);
215 get_mbox_rpl(adapter, rpl, size, mbox_data);
216 WARN_ON((be32_to_cpu(*(u32 *)rpl)
217 & FW_CMD_REQUEST) != 0);
218 }
219 t4_write_reg(adapter, mbox_ctl,
220 MBOWNER(MBOX_OWNER_NONE));
221 return -FW_CMD_RETVAL_GET(v);
222 }
223 }
224
225
226
227
228 dump_mbox(adapter, "FW Timeout", mbox_data);
229 return -ETIMEDOUT;
230}
231
232
233
234
235
236
237
238
239static int hash_mac_addr(const u8 *addr)
240{
241 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
242 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
243 a ^= b;
244 a ^= (a >> 12);
245 a ^= (a >> 6);
246 return a & 0x3f;
247}
248
249
250
251
252
253
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256
257static void __devinit init_link_config(struct link_config *lc,
258 unsigned int caps)
259{
260 lc->supported = caps;
261 lc->requested_speed = 0;
262 lc->speed = 0;
263 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
264 if (lc->supported & SUPPORTED_Autoneg) {
265 lc->advertising = lc->supported;
266 lc->autoneg = AUTONEG_ENABLE;
267 lc->requested_fc |= PAUSE_AUTONEG;
268 } else {
269 lc->advertising = 0;
270 lc->autoneg = AUTONEG_DISABLE;
271 }
272}
273
274
275
276
277
278
279int __devinit t4vf_port_init(struct adapter *adapter, int pidx)
280{
281 struct port_info *pi = adap2pinfo(adapter, pidx);
282 struct fw_vi_cmd vi_cmd, vi_rpl;
283 struct fw_port_cmd port_cmd, port_rpl;
284 int v;
285 u32 word;
286
287
288
289
290
291 memset(&vi_cmd, 0, sizeof(vi_cmd));
292 vi_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP(FW_VI_CMD) |
293 FW_CMD_REQUEST |
294 FW_CMD_READ);
295 vi_cmd.alloc_to_len16 = cpu_to_be32(FW_LEN16(vi_cmd));
296 vi_cmd.type_viid = cpu_to_be16(FW_VI_CMD_VIID(pi->viid));
297 v = t4vf_wr_mbox(adapter, &vi_cmd, sizeof(vi_cmd), &vi_rpl);
298 if (v)
299 return v;
300
301 BUG_ON(pi->port_id != FW_VI_CMD_PORTID_GET(vi_rpl.portid_pkd));
302 pi->rss_size = FW_VI_CMD_RSSSIZE_GET(be16_to_cpu(vi_rpl.rsssize_pkd));
303 t4_os_set_hw_addr(adapter, pidx, vi_rpl.mac);
304
305
306
307
308
309 if (!(adapter->params.vfres.r_caps & FW_CMD_CAP_PORT))
310 return 0;
311
312 memset(&port_cmd, 0, sizeof(port_cmd));
313 port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP(FW_PORT_CMD) |
314 FW_CMD_REQUEST |
315 FW_CMD_READ |
316 FW_PORT_CMD_PORTID(pi->port_id));
317 port_cmd.action_to_len16 =
318 cpu_to_be32(FW_PORT_CMD_ACTION(FW_PORT_ACTION_GET_PORT_INFO) |
319 FW_LEN16(port_cmd));
320 v = t4vf_wr_mbox(adapter, &port_cmd, sizeof(port_cmd), &port_rpl);
321 if (v)
322 return v;
323
324 v = 0;
325 word = be16_to_cpu(port_rpl.u.info.pcap);
326 if (word & FW_PORT_CAP_SPEED_100M)
327 v |= SUPPORTED_100baseT_Full;
328 if (word & FW_PORT_CAP_SPEED_1G)
329 v |= SUPPORTED_1000baseT_Full;
330 if (word & FW_PORT_CAP_SPEED_10G)
331 v |= SUPPORTED_10000baseT_Full;
332 if (word & FW_PORT_CAP_ANEG)
333 v |= SUPPORTED_Autoneg;
334 init_link_config(&pi->link_cfg, v);
335
336 return 0;
337}
338
339
340
341
342
343
344
345
346
347int t4vf_fw_reset(struct adapter *adapter)
348{
349 struct fw_reset_cmd cmd;
350
351 memset(&cmd, 0, sizeof(cmd));
352 cmd.op_to_write = cpu_to_be32(FW_CMD_OP(FW_RESET_CMD) |
353 FW_CMD_WRITE);
354 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
355 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
356}
357
358
359
360
361
362
363
364
365
366
367
368int t4vf_query_params(struct adapter *adapter, unsigned int nparams,
369 const u32 *params, u32 *vals)
370{
371 int i, ret;
372 struct fw_params_cmd cmd, rpl;
373 struct fw_params_param *p;
374 size_t len16;
375
376 if (nparams > 7)
377 return -EINVAL;
378
379 memset(&cmd, 0, sizeof(cmd));
380 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP(FW_PARAMS_CMD) |
381 FW_CMD_REQUEST |
382 FW_CMD_READ);
383 len16 = DIV_ROUND_UP(offsetof(struct fw_params_cmd,
384 param[nparams].mnem), 16);
385 cmd.retval_len16 = cpu_to_be32(FW_CMD_LEN16(len16));
386 for (i = 0, p = &cmd.param[0]; i < nparams; i++, p++)
387 p->mnem = htonl(*params++);
388
389 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
390 if (ret == 0)
391 for (i = 0, p = &rpl.param[0]; i < nparams; i++, p++)
392 *vals++ = be32_to_cpu(p->val);
393 return ret;
394}
395
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398
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401
402
403
404
405
406int t4vf_set_params(struct adapter *adapter, unsigned int nparams,
407 const u32 *params, const u32 *vals)
408{
409 int i;
410 struct fw_params_cmd cmd;
411 struct fw_params_param *p;
412 size_t len16;
413
414 if (nparams > 7)
415 return -EINVAL;
416
417 memset(&cmd, 0, sizeof(cmd));
418 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP(FW_PARAMS_CMD) |
419 FW_CMD_REQUEST |
420 FW_CMD_WRITE);
421 len16 = DIV_ROUND_UP(offsetof(struct fw_params_cmd,
422 param[nparams]), 16);
423 cmd.retval_len16 = cpu_to_be32(FW_CMD_LEN16(len16));
424 for (i = 0, p = &cmd.param[0]; i < nparams; i++, p++) {
425 p->mnem = cpu_to_be32(*params++);
426 p->val = cpu_to_be32(*vals++);
427 }
428
429 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
430}
431
432
433
434
435
436
437
438
439
440int t4vf_get_sge_params(struct adapter *adapter)
441{
442 struct sge_params *sge_params = &adapter->params.sge;
443 u32 params[7], vals[7];
444 int v;
445
446 params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
447 FW_PARAMS_PARAM_XYZ(SGE_CONTROL));
448 params[1] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
449 FW_PARAMS_PARAM_XYZ(SGE_HOST_PAGE_SIZE));
450 params[2] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
451 FW_PARAMS_PARAM_XYZ(SGE_FL_BUFFER_SIZE0));
452 params[3] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
453 FW_PARAMS_PARAM_XYZ(SGE_FL_BUFFER_SIZE1));
454 params[4] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
455 FW_PARAMS_PARAM_XYZ(SGE_TIMER_VALUE_0_AND_1));
456 params[5] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
457 FW_PARAMS_PARAM_XYZ(SGE_TIMER_VALUE_2_AND_3));
458 params[6] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
459 FW_PARAMS_PARAM_XYZ(SGE_TIMER_VALUE_4_AND_5));
460 v = t4vf_query_params(adapter, 7, params, vals);
461 if (v)
462 return v;
463 sge_params->sge_control = vals[0];
464 sge_params->sge_host_page_size = vals[1];
465 sge_params->sge_fl_buffer_size[0] = vals[2];
466 sge_params->sge_fl_buffer_size[1] = vals[3];
467 sge_params->sge_timer_value_0_and_1 = vals[4];
468 sge_params->sge_timer_value_2_and_3 = vals[5];
469 sge_params->sge_timer_value_4_and_5 = vals[6];
470
471 params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
472 FW_PARAMS_PARAM_XYZ(SGE_INGRESS_RX_THRESHOLD));
473 v = t4vf_query_params(adapter, 1, params, vals);
474 if (v)
475 return v;
476 sge_params->sge_ingress_rx_threshold = vals[0];
477
478 return 0;
479}
480
481
482
483
484
485
486
487
488int t4vf_get_vpd_params(struct adapter *adapter)
489{
490 struct vpd_params *vpd_params = &adapter->params.vpd;
491 u32 params[7], vals[7];
492 int v;
493
494 params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
495 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
496 v = t4vf_query_params(adapter, 1, params, vals);
497 if (v)
498 return v;
499 vpd_params->cclk = vals[0];
500
501 return 0;
502}
503
504
505
506
507
508
509
510
511int t4vf_get_dev_params(struct adapter *adapter)
512{
513 struct dev_params *dev_params = &adapter->params.dev;
514 u32 params[7], vals[7];
515 int v;
516
517 params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
518 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWREV));
519 params[1] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
520 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_TPREV));
521 v = t4vf_query_params(adapter, 2, params, vals);
522 if (v)
523 return v;
524 dev_params->fwrev = vals[0];
525 dev_params->tprev = vals[1];
526
527 return 0;
528}
529
530
531
532
533
534
535
536
537int t4vf_get_rss_glb_config(struct adapter *adapter)
538{
539 struct rss_params *rss = &adapter->params.rss;
540 struct fw_rss_glb_config_cmd cmd, rpl;
541 int v;
542
543
544
545
546
547 memset(&cmd, 0, sizeof(cmd));
548 cmd.op_to_write = cpu_to_be32(FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) |
549 FW_CMD_REQUEST |
550 FW_CMD_READ);
551 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
552 v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
553 if (v)
554 return v;
555
556
557
558
559
560
561
562 rss->mode = FW_RSS_GLB_CONFIG_CMD_MODE_GET(
563 be32_to_cpu(rpl.u.manual.mode_pkd));
564 switch (rss->mode) {
565 case FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL: {
566 u32 word = be32_to_cpu(
567 rpl.u.basicvirtual.synmapen_to_hashtoeplitz);
568
569 rss->u.basicvirtual.synmapen =
570 ((word & FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) != 0);
571 rss->u.basicvirtual.syn4tupenipv6 =
572 ((word & FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) != 0);
573 rss->u.basicvirtual.syn2tupenipv6 =
574 ((word & FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) != 0);
575 rss->u.basicvirtual.syn4tupenipv4 =
576 ((word & FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) != 0);
577 rss->u.basicvirtual.syn2tupenipv4 =
578 ((word & FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) != 0);
579
580 rss->u.basicvirtual.ofdmapen =
581 ((word & FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) != 0);
582
583 rss->u.basicvirtual.tnlmapen =
584 ((word & FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) != 0);
585 rss->u.basicvirtual.tnlalllookup =
586 ((word & FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) != 0);
587
588 rss->u.basicvirtual.hashtoeplitz =
589 ((word & FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) != 0);
590
591
592 if (!rss->u.basicvirtual.tnlmapen)
593 return -EINVAL;
594 break;
595 }
596
597 default:
598
599 return -EINVAL;
600 }
601
602 return 0;
603}
604
605
606
607
608
609
610
611
612int t4vf_get_vfres(struct adapter *adapter)
613{
614 struct vf_resources *vfres = &adapter->params.vfres;
615 struct fw_pfvf_cmd cmd, rpl;
616 int v;
617 u32 word;
618
619
620
621
622
623 memset(&cmd, 0, sizeof(cmd));
624 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP(FW_PFVF_CMD) |
625 FW_CMD_REQUEST |
626 FW_CMD_READ);
627 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
628 v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
629 if (v)
630 return v;
631
632
633
634
635 word = be32_to_cpu(rpl.niqflint_niq);
636 vfres->niqflint = FW_PFVF_CMD_NIQFLINT_GET(word);
637 vfres->niq = FW_PFVF_CMD_NIQ_GET(word);
638
639 word = be32_to_cpu(rpl.type_to_neq);
640 vfres->neq = FW_PFVF_CMD_NEQ_GET(word);
641 vfres->pmask = FW_PFVF_CMD_PMASK_GET(word);
642
643 word = be32_to_cpu(rpl.tc_to_nexactf);
644 vfres->tc = FW_PFVF_CMD_TC_GET(word);
645 vfres->nvi = FW_PFVF_CMD_NVI_GET(word);
646 vfres->nexactf = FW_PFVF_CMD_NEXACTF_GET(word);
647
648 word = be32_to_cpu(rpl.r_caps_to_nethctrl);
649 vfres->r_caps = FW_PFVF_CMD_R_CAPS_GET(word);
650 vfres->wx_caps = FW_PFVF_CMD_WX_CAPS_GET(word);
651 vfres->nethctrl = FW_PFVF_CMD_NETHCTRL_GET(word);
652
653 return 0;
654}
655
656
657
658
659
660
661
662
663
664
665int t4vf_read_rss_vi_config(struct adapter *adapter, unsigned int viid,
666 union rss_vi_config *config)
667{
668 struct fw_rss_vi_config_cmd cmd, rpl;
669 int v;
670
671 memset(&cmd, 0, sizeof(cmd));
672 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
673 FW_CMD_REQUEST |
674 FW_CMD_READ |
675 FW_RSS_VI_CONFIG_CMD_VIID(viid));
676 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
677 v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
678 if (v)
679 return v;
680
681 switch (adapter->params.rss.mode) {
682 case FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL: {
683 u32 word = be32_to_cpu(rpl.u.basicvirtual.defaultq_to_udpen);
684
685 config->basicvirtual.ip6fourtupen =
686 ((word & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) != 0);
687 config->basicvirtual.ip6twotupen =
688 ((word & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) != 0);
689 config->basicvirtual.ip4fourtupen =
690 ((word & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) != 0);
691 config->basicvirtual.ip4twotupen =
692 ((word & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) != 0);
693 config->basicvirtual.udpen =
694 ((word & FW_RSS_VI_CONFIG_CMD_UDPEN) != 0);
695 config->basicvirtual.defaultq =
696 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_GET(word);
697 break;
698 }
699
700 default:
701 return -EINVAL;
702 }
703
704 return 0;
705}
706
707
708
709
710
711
712
713
714
715
716int t4vf_write_rss_vi_config(struct adapter *adapter, unsigned int viid,
717 union rss_vi_config *config)
718{
719 struct fw_rss_vi_config_cmd cmd, rpl;
720
721 memset(&cmd, 0, sizeof(cmd));
722 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
723 FW_CMD_REQUEST |
724 FW_CMD_WRITE |
725 FW_RSS_VI_CONFIG_CMD_VIID(viid));
726 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
727 switch (adapter->params.rss.mode) {
728 case FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL: {
729 u32 word = 0;
730
731 if (config->basicvirtual.ip6fourtupen)
732 word |= FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
733 if (config->basicvirtual.ip6twotupen)
734 word |= FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
735 if (config->basicvirtual.ip4fourtupen)
736 word |= FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
737 if (config->basicvirtual.ip4twotupen)
738 word |= FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
739 if (config->basicvirtual.udpen)
740 word |= FW_RSS_VI_CONFIG_CMD_UDPEN;
741 word |= FW_RSS_VI_CONFIG_CMD_DEFAULTQ(
742 config->basicvirtual.defaultq);
743 cmd.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(word);
744 break;
745 }
746
747 default:
748 return -EINVAL;
749 }
750
751 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
752}
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769int t4vf_config_rss_range(struct adapter *adapter, unsigned int viid,
770 int start, int n, const u16 *rspq, int nrspq)
771{
772 const u16 *rsp = rspq;
773 const u16 *rsp_end = rspq+nrspq;
774 struct fw_rss_ind_tbl_cmd cmd;
775
776
777
778
779 memset(&cmd, 0, sizeof(cmd));
780 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
781 FW_CMD_REQUEST |
782 FW_CMD_WRITE |
783 FW_RSS_IND_TBL_CMD_VIID(viid));
784 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
785
786
787
788
789
790
791
792 while (n > 0) {
793 __be32 *qp = &cmd.iq0_to_iq2;
794 int nq = min(n, 32);
795 int ret;
796
797
798
799
800
801 cmd.niqid = cpu_to_be16(nq);
802 cmd.startidx = cpu_to_be16(start);
803
804
805
806
807 start += nq;
808 n -= nq;
809
810
811
812
813
814
815 while (nq > 0) {
816
817
818
819
820
821
822 u16 qbuf[3];
823 u16 *qbp = qbuf;
824 int nqbuf = min(3, nq);
825
826 nq -= nqbuf;
827 qbuf[0] = qbuf[1] = qbuf[2] = 0;
828 while (nqbuf) {
829 nqbuf--;
830 *qbp++ = *rsp++;
831 if (rsp >= rsp_end)
832 rsp = rspq;
833 }
834 *qp++ = cpu_to_be32(FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
835 FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
836 FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
837 }
838
839
840
841
842
843 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
844 if (ret)
845 return ret;
846 }
847 return 0;
848}
849
850
851
852
853
854
855
856
857
858
859int t4vf_alloc_vi(struct adapter *adapter, int port_id)
860{
861 struct fw_vi_cmd cmd, rpl;
862 int v;
863
864
865
866
867
868 memset(&cmd, 0, sizeof(cmd));
869 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP(FW_VI_CMD) |
870 FW_CMD_REQUEST |
871 FW_CMD_WRITE |
872 FW_CMD_EXEC);
873 cmd.alloc_to_len16 = cpu_to_be32(FW_LEN16(cmd) |
874 FW_VI_CMD_ALLOC);
875 cmd.portid_pkd = FW_VI_CMD_PORTID(port_id);
876 v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
877 if (v)
878 return v;
879
880 return FW_VI_CMD_VIID_GET(be16_to_cpu(rpl.type_viid));
881}
882
883
884
885
886
887
888
889
890
891int t4vf_free_vi(struct adapter *adapter, int viid)
892{
893 struct fw_vi_cmd cmd;
894
895
896
897
898 memset(&cmd, 0, sizeof(cmd));
899 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP(FW_VI_CMD) |
900 FW_CMD_REQUEST |
901 FW_CMD_EXEC);
902 cmd.alloc_to_len16 = cpu_to_be32(FW_LEN16(cmd) |
903 FW_VI_CMD_FREE);
904 cmd.type_viid = cpu_to_be16(FW_VI_CMD_VIID(viid));
905 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
906}
907
908
909
910
911
912
913
914
915
916
917int t4vf_enable_vi(struct adapter *adapter, unsigned int viid,
918 bool rx_en, bool tx_en)
919{
920 struct fw_vi_enable_cmd cmd;
921
922 memset(&cmd, 0, sizeof(cmd));
923 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP(FW_VI_ENABLE_CMD) |
924 FW_CMD_REQUEST |
925 FW_CMD_EXEC |
926 FW_VI_ENABLE_CMD_VIID(viid));
927 cmd.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN(rx_en) |
928 FW_VI_ENABLE_CMD_EEN(tx_en) |
929 FW_LEN16(cmd));
930 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
931}
932
933
934
935
936
937
938
939
940
941int t4vf_identify_port(struct adapter *adapter, unsigned int viid,
942 unsigned int nblinks)
943{
944 struct fw_vi_enable_cmd cmd;
945
946 memset(&cmd, 0, sizeof(cmd));
947 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP(FW_VI_ENABLE_CMD) |
948 FW_CMD_REQUEST |
949 FW_CMD_EXEC |
950 FW_VI_ENABLE_CMD_VIID(viid));
951 cmd.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED |
952 FW_LEN16(cmd));
953 cmd.blinkdur = cpu_to_be16(nblinks);
954 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
955}
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970int t4vf_set_rxmode(struct adapter *adapter, unsigned int viid,
971 int mtu, int promisc, int all_multi, int bcast, int vlanex,
972 bool sleep_ok)
973{
974 struct fw_vi_rxmode_cmd cmd;
975
976
977 if (mtu < 0)
978 mtu = FW_VI_RXMODE_CMD_MTU_MASK;
979 if (promisc < 0)
980 promisc = FW_VI_RXMODE_CMD_PROMISCEN_MASK;
981 if (all_multi < 0)
982 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_MASK;
983 if (bcast < 0)
984 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_MASK;
985 if (vlanex < 0)
986 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_MASK;
987
988 memset(&cmd, 0, sizeof(cmd));
989 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP(FW_VI_RXMODE_CMD) |
990 FW_CMD_REQUEST |
991 FW_CMD_WRITE |
992 FW_VI_RXMODE_CMD_VIID(viid));
993 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
994 cmd.mtu_to_vlanexen =
995 cpu_to_be32(FW_VI_RXMODE_CMD_MTU(mtu) |
996 FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
997 FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
998 FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
999 FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
1000 return t4vf_wr_mbox_core(adapter, &cmd, sizeof(cmd), NULL, sleep_ok);
1001}
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024int t4vf_alloc_mac_filt(struct adapter *adapter, unsigned int viid, bool free,
1025 unsigned int naddr, const u8 **addr, u16 *idx,
1026 u64 *hash, bool sleep_ok)
1027{
1028 int offset, ret = 0;
1029 unsigned nfilters = 0;
1030 unsigned int rem = naddr;
1031 struct fw_vi_mac_cmd cmd, rpl;
1032
1033 if (naddr > FW_CLS_TCAM_NUM_ENTRIES)
1034 return -EINVAL;
1035
1036 for (offset = 0; offset < naddr; ) {
1037 unsigned int fw_naddr = (rem < ARRAY_SIZE(cmd.u.exact)
1038 ? rem
1039 : ARRAY_SIZE(cmd.u.exact));
1040 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
1041 u.exact[fw_naddr]), 16);
1042 struct fw_vi_mac_exact *p;
1043 int i;
1044
1045 memset(&cmd, 0, sizeof(cmd));
1046 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP(FW_VI_MAC_CMD) |
1047 FW_CMD_REQUEST |
1048 FW_CMD_WRITE |
1049 (free ? FW_CMD_EXEC : 0) |
1050 FW_VI_MAC_CMD_VIID(viid));
1051 cmd.freemacs_to_len16 =
1052 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS(free) |
1053 FW_CMD_LEN16(len16));
1054
1055 for (i = 0, p = cmd.u.exact; i < fw_naddr; i++, p++) {
1056 p->valid_to_idx = cpu_to_be16(
1057 FW_VI_MAC_CMD_VALID |
1058 FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
1059 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
1060 }
1061
1062
1063 ret = t4vf_wr_mbox_core(adapter, &cmd, sizeof(cmd), &rpl,
1064 sleep_ok);
1065 if (ret && ret != -ENOMEM)
1066 break;
1067
1068 for (i = 0, p = rpl.u.exact; i < fw_naddr; i++, p++) {
1069 u16 index = FW_VI_MAC_CMD_IDX_GET(
1070 be16_to_cpu(p->valid_to_idx));
1071
1072 if (idx)
1073 idx[offset+i] =
1074 (index >= FW_CLS_TCAM_NUM_ENTRIES
1075 ? 0xffff
1076 : index);
1077 if (index < FW_CLS_TCAM_NUM_ENTRIES)
1078 nfilters++;
1079 else if (hash)
1080 *hash |= (1ULL << hash_mac_addr(addr[offset+i]));
1081 }
1082
1083 free = false;
1084 offset += fw_naddr;
1085 rem -= fw_naddr;
1086 }
1087
1088
1089
1090
1091
1092 if (ret == 0 || ret == -ENOMEM)
1093 ret = nfilters;
1094 return ret;
1095}
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115int t4vf_change_mac(struct adapter *adapter, unsigned int viid,
1116 int idx, const u8 *addr, bool persist)
1117{
1118 int ret;
1119 struct fw_vi_mac_cmd cmd, rpl;
1120 struct fw_vi_mac_exact *p = &cmd.u.exact[0];
1121 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
1122 u.exact[1]), 16);
1123
1124
1125
1126
1127
1128 if (idx < 0)
1129 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
1130
1131 memset(&cmd, 0, sizeof(cmd));
1132 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP(FW_VI_MAC_CMD) |
1133 FW_CMD_REQUEST |
1134 FW_CMD_WRITE |
1135 FW_VI_MAC_CMD_VIID(viid));
1136 cmd.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16(len16));
1137 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID |
1138 FW_VI_MAC_CMD_IDX(idx));
1139 memcpy(p->macaddr, addr, sizeof(p->macaddr));
1140
1141 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
1142 if (ret == 0) {
1143 p = &rpl.u.exact[0];
1144 ret = FW_VI_MAC_CMD_IDX_GET(be16_to_cpu(p->valid_to_idx));
1145 if (ret >= FW_CLS_TCAM_NUM_ENTRIES)
1146 ret = -ENOMEM;
1147 }
1148 return ret;
1149}
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161int t4vf_set_addr_hash(struct adapter *adapter, unsigned int viid,
1162 bool ucast, u64 vec, bool sleep_ok)
1163{
1164 struct fw_vi_mac_cmd cmd;
1165 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
1166 u.exact[0]), 16);
1167
1168 memset(&cmd, 0, sizeof(cmd));
1169 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP(FW_VI_MAC_CMD) |
1170 FW_CMD_REQUEST |
1171 FW_CMD_WRITE |
1172 FW_VI_ENABLE_CMD_VIID(viid));
1173 cmd.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN |
1174 FW_VI_MAC_CMD_HASHUNIEN(ucast) |
1175 FW_CMD_LEN16(len16));
1176 cmd.u.hash.hashvec = cpu_to_be64(vec);
1177 return t4vf_wr_mbox_core(adapter, &cmd, sizeof(cmd), NULL, sleep_ok);
1178}
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188int t4vf_get_port_stats(struct adapter *adapter, int pidx,
1189 struct t4vf_port_stats *s)
1190{
1191 struct port_info *pi = adap2pinfo(adapter, pidx);
1192 struct fw_vi_stats_vf fwstats;
1193 unsigned int rem = VI_VF_NUM_STATS;
1194 __be64 *fwsp = (__be64 *)&fwstats;
1195
1196
1197
1198
1199
1200
1201 while (rem) {
1202 unsigned int ix = VI_VF_NUM_STATS - rem;
1203 unsigned int nstats = min(6U, rem);
1204 struct fw_vi_stats_cmd cmd, rpl;
1205 size_t len = (offsetof(struct fw_vi_stats_cmd, u) +
1206 sizeof(struct fw_vi_stats_ctl));
1207 size_t len16 = DIV_ROUND_UP(len, 16);
1208 int ret;
1209
1210 memset(&cmd, 0, sizeof(cmd));
1211 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP(FW_VI_STATS_CMD) |
1212 FW_VI_STATS_CMD_VIID(pi->viid) |
1213 FW_CMD_REQUEST |
1214 FW_CMD_READ);
1215 cmd.retval_len16 = cpu_to_be32(FW_CMD_LEN16(len16));
1216 cmd.u.ctl.nstats_ix =
1217 cpu_to_be16(FW_VI_STATS_CMD_IX(ix) |
1218 FW_VI_STATS_CMD_NSTATS(nstats));
1219 ret = t4vf_wr_mbox_ns(adapter, &cmd, len, &rpl);
1220 if (ret)
1221 return ret;
1222
1223 memcpy(fwsp, &rpl.u.ctl.stat0, sizeof(__be64) * nstats);
1224
1225 rem -= nstats;
1226 fwsp += nstats;
1227 }
1228
1229
1230
1231
1232 s->tx_bcast_bytes = be64_to_cpu(fwstats.tx_bcast_bytes);
1233 s->tx_bcast_frames = be64_to_cpu(fwstats.tx_bcast_frames);
1234 s->tx_mcast_bytes = be64_to_cpu(fwstats.tx_mcast_bytes);
1235 s->tx_mcast_frames = be64_to_cpu(fwstats.tx_mcast_frames);
1236 s->tx_ucast_bytes = be64_to_cpu(fwstats.tx_ucast_bytes);
1237 s->tx_ucast_frames = be64_to_cpu(fwstats.tx_ucast_frames);
1238 s->tx_drop_frames = be64_to_cpu(fwstats.tx_drop_frames);
1239 s->tx_offload_bytes = be64_to_cpu(fwstats.tx_offload_bytes);
1240 s->tx_offload_frames = be64_to_cpu(fwstats.tx_offload_frames);
1241
1242 s->rx_bcast_bytes = be64_to_cpu(fwstats.rx_bcast_bytes);
1243 s->rx_bcast_frames = be64_to_cpu(fwstats.rx_bcast_frames);
1244 s->rx_mcast_bytes = be64_to_cpu(fwstats.rx_mcast_bytes);
1245 s->rx_mcast_frames = be64_to_cpu(fwstats.rx_mcast_frames);
1246 s->rx_ucast_bytes = be64_to_cpu(fwstats.rx_ucast_bytes);
1247 s->rx_ucast_frames = be64_to_cpu(fwstats.rx_ucast_frames);
1248
1249 s->rx_err_frames = be64_to_cpu(fwstats.rx_err_frames);
1250
1251 return 0;
1252}
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264int t4vf_iq_free(struct adapter *adapter, unsigned int iqtype,
1265 unsigned int iqid, unsigned int fl0id, unsigned int fl1id)
1266{
1267 struct fw_iq_cmd cmd;
1268
1269 memset(&cmd, 0, sizeof(cmd));
1270 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP(FW_IQ_CMD) |
1271 FW_CMD_REQUEST |
1272 FW_CMD_EXEC);
1273 cmd.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE |
1274 FW_LEN16(cmd));
1275 cmd.type_to_iqandstindex =
1276 cpu_to_be32(FW_IQ_CMD_TYPE(iqtype));
1277
1278 cmd.iqid = cpu_to_be16(iqid);
1279 cmd.fl0id = cpu_to_be16(fl0id);
1280 cmd.fl1id = cpu_to_be16(fl1id);
1281 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
1282}
1283
1284
1285
1286
1287
1288
1289
1290
1291int t4vf_eth_eq_free(struct adapter *adapter, unsigned int eqid)
1292{
1293 struct fw_eq_eth_cmd cmd;
1294
1295 memset(&cmd, 0, sizeof(cmd));
1296 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP(FW_EQ_ETH_CMD) |
1297 FW_CMD_REQUEST |
1298 FW_CMD_EXEC);
1299 cmd.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE |
1300 FW_LEN16(cmd));
1301 cmd.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID(eqid));
1302 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
1303}
1304
1305
1306
1307
1308
1309
1310
1311
1312int t4vf_handle_fw_rpl(struct adapter *adapter, const __be64 *rpl)
1313{
1314 const struct fw_cmd_hdr *cmd_hdr = (const struct fw_cmd_hdr *)rpl;
1315 u8 opcode = FW_CMD_OP_GET(be32_to_cpu(cmd_hdr->hi));
1316
1317 switch (opcode) {
1318 case FW_PORT_CMD: {
1319
1320
1321
1322 const struct fw_port_cmd *port_cmd =
1323 (const struct fw_port_cmd *)rpl;
1324 u32 word;
1325 int action, port_id, link_ok, speed, fc, pidx;
1326
1327
1328
1329
1330 action = FW_PORT_CMD_ACTION_GET(
1331 be32_to_cpu(port_cmd->action_to_len16));
1332 if (action != FW_PORT_ACTION_GET_PORT_INFO) {
1333 dev_err(adapter->pdev_dev,
1334 "Unknown firmware PORT reply action %x\n",
1335 action);
1336 break;
1337 }
1338
1339 port_id = FW_PORT_CMD_PORTID_GET(
1340 be32_to_cpu(port_cmd->op_to_portid));
1341
1342 word = be32_to_cpu(port_cmd->u.info.lstatus_to_modtype);
1343 link_ok = (word & FW_PORT_CMD_LSTATUS) != 0;
1344 speed = 0;
1345 fc = 0;
1346 if (word & FW_PORT_CMD_RXPAUSE)
1347 fc |= PAUSE_RX;
1348 if (word & FW_PORT_CMD_TXPAUSE)
1349 fc |= PAUSE_TX;
1350 if (word & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
1351 speed = SPEED_100;
1352 else if (word & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
1353 speed = SPEED_1000;
1354 else if (word & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
1355 speed = SPEED_10000;
1356
1357
1358
1359
1360
1361
1362
1363 for_each_port(adapter, pidx) {
1364 struct port_info *pi = adap2pinfo(adapter, pidx);
1365 struct link_config *lc;
1366
1367 if (pi->port_id != port_id)
1368 continue;
1369
1370 lc = &pi->link_cfg;
1371 if (link_ok != lc->link_ok || speed != lc->speed ||
1372 fc != lc->fc) {
1373
1374 lc->link_ok = link_ok;
1375 lc->speed = speed;
1376 lc->fc = fc;
1377 t4vf_os_link_changed(adapter, pidx, link_ok);
1378 }
1379 }
1380 break;
1381 }
1382
1383 default:
1384 dev_err(adapter->pdev_dev, "Unknown firmware reply %X\n",
1385 opcode);
1386 }
1387 return 0;
1388}
1389