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150#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
151
152#include <linux/module.h>
153#include <linux/moduleparam.h>
154#include <linux/kernel.h>
155#include <linux/types.h>
156#include <linux/sched.h>
157#include <linux/slab.h>
158#include <linux/delay.h>
159#include <linux/init.h>
160#include <linux/pci.h>
161#include <linux/dma-mapping.h>
162#include <linux/dmapool.h>
163#include <linux/netdevice.h>
164#include <linux/etherdevice.h>
165#include <linux/mii.h>
166#include <linux/if_vlan.h>
167#include <linux/skbuff.h>
168#include <linux/ethtool.h>
169#include <linux/string.h>
170#include <linux/firmware.h>
171#include <linux/rtnetlink.h>
172#include <asm/unaligned.h>
173
174
175#define DRV_NAME "e100"
176#define DRV_EXT "-NAPI"
177#define DRV_VERSION "3.5.24-k2"DRV_EXT
178#define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
179#define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation"
180
181#define E100_WATCHDOG_PERIOD (2 * HZ)
182#define E100_NAPI_WEIGHT 16
183
184#define FIRMWARE_D101M "e100/d101m_ucode.bin"
185#define FIRMWARE_D101S "e100/d101s_ucode.bin"
186#define FIRMWARE_D102E "e100/d102e_ucode.bin"
187
188MODULE_DESCRIPTION(DRV_DESCRIPTION);
189MODULE_AUTHOR(DRV_COPYRIGHT);
190MODULE_LICENSE("GPL");
191MODULE_VERSION(DRV_VERSION);
192MODULE_FIRMWARE(FIRMWARE_D101M);
193MODULE_FIRMWARE(FIRMWARE_D101S);
194MODULE_FIRMWARE(FIRMWARE_D102E);
195
196static int debug = 3;
197static int eeprom_bad_csum_allow = 0;
198static int use_io = 0;
199module_param(debug, int, 0);
200module_param(eeprom_bad_csum_allow, int, 0);
201module_param(use_io, int, 0);
202MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
203MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");
204MODULE_PARM_DESC(use_io, "Force use of i/o access mode");
205
206#define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
207 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
208 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
209static DEFINE_PCI_DEVICE_TABLE(e100_id_table) = {
210 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
211 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
212 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
213 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
214 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
215 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
216 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
217 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
218 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
219 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
220 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
221 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
222 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
223 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
224 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
225 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
226 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
227 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
228 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
229 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
230 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
231 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
232 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
233 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
234 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
235 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
236 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
237 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
238 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
239 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
240 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
241 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
242 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
243 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
244 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
245 INTEL_8255X_ETHERNET_DEVICE(0x10fe, 7),
246 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
247 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
248 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
249 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
250 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
251 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
252 { 0, }
253};
254MODULE_DEVICE_TABLE(pci, e100_id_table);
255
256enum mac {
257 mac_82557_D100_A = 0,
258 mac_82557_D100_B = 1,
259 mac_82557_D100_C = 2,
260 mac_82558_D101_A4 = 4,
261 mac_82558_D101_B0 = 5,
262 mac_82559_D101M = 8,
263 mac_82559_D101S = 9,
264 mac_82550_D102 = 12,
265 mac_82550_D102_C = 13,
266 mac_82551_E = 14,
267 mac_82551_F = 15,
268 mac_82551_10 = 16,
269 mac_unknown = 0xFF,
270};
271
272enum phy {
273 phy_100a = 0x000003E0,
274 phy_100c = 0x035002A8,
275 phy_82555_tx = 0x015002A8,
276 phy_nsc_tx = 0x5C002000,
277 phy_82562_et = 0x033002A8,
278 phy_82562_em = 0x032002A8,
279 phy_82562_ek = 0x031002A8,
280 phy_82562_eh = 0x017002A8,
281 phy_82552_v = 0xd061004d,
282 phy_unknown = 0xFFFFFFFF,
283};
284
285
286struct csr {
287 struct {
288 u8 status;
289 u8 stat_ack;
290 u8 cmd_lo;
291 u8 cmd_hi;
292 u32 gen_ptr;
293 } scb;
294 u32 port;
295 u16 flash_ctrl;
296 u8 eeprom_ctrl_lo;
297 u8 eeprom_ctrl_hi;
298 u32 mdi_ctrl;
299 u32 rx_dma_count;
300};
301
302enum scb_status {
303 rus_no_res = 0x08,
304 rus_ready = 0x10,
305 rus_mask = 0x3C,
306};
307
308enum ru_state {
309 RU_SUSPENDED = 0,
310 RU_RUNNING = 1,
311 RU_UNINITIALIZED = -1,
312};
313
314enum scb_stat_ack {
315 stat_ack_not_ours = 0x00,
316 stat_ack_sw_gen = 0x04,
317 stat_ack_rnr = 0x10,
318 stat_ack_cu_idle = 0x20,
319 stat_ack_frame_rx = 0x40,
320 stat_ack_cu_cmd_done = 0x80,
321 stat_ack_not_present = 0xFF,
322 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
323 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
324};
325
326enum scb_cmd_hi {
327 irq_mask_none = 0x00,
328 irq_mask_all = 0x01,
329 irq_sw_gen = 0x02,
330};
331
332enum scb_cmd_lo {
333 cuc_nop = 0x00,
334 ruc_start = 0x01,
335 ruc_load_base = 0x06,
336 cuc_start = 0x10,
337 cuc_resume = 0x20,
338 cuc_dump_addr = 0x40,
339 cuc_dump_stats = 0x50,
340 cuc_load_base = 0x60,
341 cuc_dump_reset = 0x70,
342};
343
344enum cuc_dump {
345 cuc_dump_complete = 0x0000A005,
346 cuc_dump_reset_complete = 0x0000A007,
347};
348
349enum port {
350 software_reset = 0x0000,
351 selftest = 0x0001,
352 selective_reset = 0x0002,
353};
354
355enum eeprom_ctrl_lo {
356 eesk = 0x01,
357 eecs = 0x02,
358 eedi = 0x04,
359 eedo = 0x08,
360};
361
362enum mdi_ctrl {
363 mdi_write = 0x04000000,
364 mdi_read = 0x08000000,
365 mdi_ready = 0x10000000,
366};
367
368enum eeprom_op {
369 op_write = 0x05,
370 op_read = 0x06,
371 op_ewds = 0x10,
372 op_ewen = 0x13,
373};
374
375enum eeprom_offsets {
376 eeprom_cnfg_mdix = 0x03,
377 eeprom_phy_iface = 0x06,
378 eeprom_id = 0x0A,
379 eeprom_config_asf = 0x0D,
380 eeprom_smbus_addr = 0x90,
381};
382
383enum eeprom_cnfg_mdix {
384 eeprom_mdix_enabled = 0x0080,
385};
386
387enum eeprom_phy_iface {
388 NoSuchPhy = 0,
389 I82553AB,
390 I82553C,
391 I82503,
392 DP83840,
393 S80C240,
394 S80C24,
395 I82555,
396 DP83840A = 10,
397};
398
399enum eeprom_id {
400 eeprom_id_wol = 0x0020,
401};
402
403enum eeprom_config_asf {
404 eeprom_asf = 0x8000,
405 eeprom_gcl = 0x4000,
406};
407
408enum cb_status {
409 cb_complete = 0x8000,
410 cb_ok = 0x2000,
411};
412
413enum cb_command {
414 cb_nop = 0x0000,
415 cb_iaaddr = 0x0001,
416 cb_config = 0x0002,
417 cb_multi = 0x0003,
418 cb_tx = 0x0004,
419 cb_ucode = 0x0005,
420 cb_dump = 0x0006,
421 cb_tx_sf = 0x0008,
422 cb_cid = 0x1f00,
423 cb_i = 0x2000,
424 cb_s = 0x4000,
425 cb_el = 0x8000,
426};
427
428struct rfd {
429 __le16 status;
430 __le16 command;
431 __le32 link;
432 __le32 rbd;
433 __le16 actual_size;
434 __le16 size;
435};
436
437struct rx {
438 struct rx *next, *prev;
439 struct sk_buff *skb;
440 dma_addr_t dma_addr;
441};
442
443#if defined(__BIG_ENDIAN_BITFIELD)
444#define X(a,b) b,a
445#else
446#define X(a,b) a,b
447#endif
448struct config {
449 u8 X(byte_count:6, pad0:2);
450 u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
451 u8 adaptive_ifs;
452 u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
453 term_write_cache_line:1), pad3:4);
454 u8 X(rx_dma_max_count:7, pad4:1);
455 u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
456 u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
457 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
458 rx_discard_overruns:1), rx_save_bad_frames:1);
459 u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
460 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
461 tx_dynamic_tbd:1);
462 u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
463 u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
464 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
465 u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
466 loopback:2);
467 u8 X(linear_priority:3, pad11:5);
468 u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
469 u8 ip_addr_lo;
470 u8 ip_addr_hi;
471 u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
472 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
473 pad15_2:1), crs_or_cdt:1);
474 u8 fc_delay_lo;
475 u8 fc_delay_hi;
476 u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
477 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
478 u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
479 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
480 full_duplex_force:1), full_duplex_pin:1);
481 u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
482 u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
483 u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
484 u8 pad_d102[9];
485};
486
487#define E100_MAX_MULTICAST_ADDRS 64
488struct multi {
489 __le16 count;
490 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2];
491};
492
493
494#define UCODE_SIZE 134
495struct cb {
496 __le16 status;
497 __le16 command;
498 __le32 link;
499 union {
500 u8 iaaddr[ETH_ALEN];
501 __le32 ucode[UCODE_SIZE];
502 struct config config;
503 struct multi multi;
504 struct {
505 u32 tbd_array;
506 u16 tcb_byte_count;
507 u8 threshold;
508 u8 tbd_count;
509 struct {
510 __le32 buf_addr;
511 __le16 size;
512 u16 eol;
513 } tbd;
514 } tcb;
515 __le32 dump_buffer_addr;
516 } u;
517 struct cb *next, *prev;
518 dma_addr_t dma_addr;
519 struct sk_buff *skb;
520};
521
522enum loopback {
523 lb_none = 0, lb_mac = 1, lb_phy = 3,
524};
525
526struct stats {
527 __le32 tx_good_frames, tx_max_collisions, tx_late_collisions,
528 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
529 tx_multiple_collisions, tx_total_collisions;
530 __le32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
531 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
532 rx_short_frame_errors;
533 __le32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
534 __le16 xmt_tco_frames, rcv_tco_frames;
535 __le32 complete;
536};
537
538struct mem {
539 struct {
540 u32 signature;
541 u32 result;
542 } selftest;
543 struct stats stats;
544 u8 dump_buf[596];
545};
546
547struct param_range {
548 u32 min;
549 u32 max;
550 u32 count;
551};
552
553struct params {
554 struct param_range rfds;
555 struct param_range cbs;
556};
557
558struct nic {
559
560 u32 msg_enable ____cacheline_aligned;
561 struct net_device *netdev;
562 struct pci_dev *pdev;
563 u16 (*mdio_ctrl)(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data);
564
565 struct rx *rxs ____cacheline_aligned;
566 struct rx *rx_to_use;
567 struct rx *rx_to_clean;
568 struct rfd blank_rfd;
569 enum ru_state ru_running;
570
571 spinlock_t cb_lock ____cacheline_aligned;
572 spinlock_t cmd_lock;
573 struct csr __iomem *csr;
574 enum scb_cmd_lo cuc_cmd;
575 unsigned int cbs_avail;
576 struct napi_struct napi;
577 struct cb *cbs;
578 struct cb *cb_to_use;
579 struct cb *cb_to_send;
580 struct cb *cb_to_clean;
581 __le16 tx_command;
582
583
584 enum {
585 ich = (1 << 0),
586 promiscuous = (1 << 1),
587 multicast_all = (1 << 2),
588 wol_magic = (1 << 3),
589 ich_10h_workaround = (1 << 4),
590 } flags ____cacheline_aligned;
591
592 enum mac mac;
593 enum phy phy;
594 struct params params;
595 struct timer_list watchdog;
596 struct timer_list blink_timer;
597 struct mii_if_info mii;
598 struct work_struct tx_timeout_task;
599 enum loopback loopback;
600
601 struct mem *mem;
602 dma_addr_t dma_addr;
603
604 struct pci_pool *cbs_pool;
605 dma_addr_t cbs_dma_addr;
606 u8 adaptive_ifs;
607 u8 tx_threshold;
608 u32 tx_frames;
609 u32 tx_collisions;
610 u32 tx_deferred;
611 u32 tx_single_collisions;
612 u32 tx_multiple_collisions;
613 u32 tx_fc_pause;
614 u32 tx_tco_frames;
615
616 u32 rx_fc_pause;
617 u32 rx_fc_unsupported;
618 u32 rx_tco_frames;
619 u32 rx_over_length_errors;
620
621 u16 leds;
622 u16 eeprom_wc;
623 __le16 eeprom[256];
624 spinlock_t mdio_lock;
625 const struct firmware *fw;
626};
627
628static inline void e100_write_flush(struct nic *nic)
629{
630
631
632 (void)ioread8(&nic->csr->scb.status);
633}
634
635static void e100_enable_irq(struct nic *nic)
636{
637 unsigned long flags;
638
639 spin_lock_irqsave(&nic->cmd_lock, flags);
640 iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi);
641 e100_write_flush(nic);
642 spin_unlock_irqrestore(&nic->cmd_lock, flags);
643}
644
645static void e100_disable_irq(struct nic *nic)
646{
647 unsigned long flags;
648
649 spin_lock_irqsave(&nic->cmd_lock, flags);
650 iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi);
651 e100_write_flush(nic);
652 spin_unlock_irqrestore(&nic->cmd_lock, flags);
653}
654
655static void e100_hw_reset(struct nic *nic)
656{
657
658
659 iowrite32(selective_reset, &nic->csr->port);
660 e100_write_flush(nic); udelay(20);
661
662
663 iowrite32(software_reset, &nic->csr->port);
664 e100_write_flush(nic); udelay(20);
665
666
667 e100_disable_irq(nic);
668}
669
670static int e100_self_test(struct nic *nic)
671{
672 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
673
674
675
676
677 nic->mem->selftest.signature = 0;
678 nic->mem->selftest.result = 0xFFFFFFFF;
679
680 iowrite32(selftest | dma_addr, &nic->csr->port);
681 e100_write_flush(nic);
682
683 msleep(10);
684
685
686 e100_disable_irq(nic);
687
688
689 if (nic->mem->selftest.result != 0) {
690 netif_err(nic, hw, nic->netdev,
691 "Self-test failed: result=0x%08X\n",
692 nic->mem->selftest.result);
693 return -ETIMEDOUT;
694 }
695 if (nic->mem->selftest.signature == 0) {
696 netif_err(nic, hw, nic->netdev, "Self-test failed: timed out\n");
697 return -ETIMEDOUT;
698 }
699
700 return 0;
701}
702
703static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, __le16 data)
704{
705 u32 cmd_addr_data[3];
706 u8 ctrl;
707 int i, j;
708
709
710 cmd_addr_data[0] = op_ewen << (addr_len - 2);
711 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
712 le16_to_cpu(data);
713 cmd_addr_data[2] = op_ewds << (addr_len - 2);
714
715
716 for (j = 0; j < 3; j++) {
717
718
719 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
720 e100_write_flush(nic); udelay(4);
721
722 for (i = 31; i >= 0; i--) {
723 ctrl = (cmd_addr_data[j] & (1 << i)) ?
724 eecs | eedi : eecs;
725 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
726 e100_write_flush(nic); udelay(4);
727
728 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
729 e100_write_flush(nic); udelay(4);
730 }
731
732 msleep(10);
733
734
735 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
736 e100_write_flush(nic); udelay(4);
737 }
738};
739
740
741static __le16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
742{
743 u32 cmd_addr_data;
744 u16 data = 0;
745 u8 ctrl;
746 int i;
747
748 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
749
750
751 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
752 e100_write_flush(nic); udelay(4);
753
754
755 for (i = 31; i >= 0; i--) {
756 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
757 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
758 e100_write_flush(nic); udelay(4);
759
760 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
761 e100_write_flush(nic); udelay(4);
762
763
764
765 ctrl = ioread8(&nic->csr->eeprom_ctrl_lo);
766 if (!(ctrl & eedo) && i > 16) {
767 *addr_len -= (i - 16);
768 i = 17;
769 }
770
771 data = (data << 1) | (ctrl & eedo ? 1 : 0);
772 }
773
774
775 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
776 e100_write_flush(nic); udelay(4);
777
778 return cpu_to_le16(data);
779};
780
781
782static int e100_eeprom_load(struct nic *nic)
783{
784 u16 addr, addr_len = 8, checksum = 0;
785
786
787 e100_eeprom_read(nic, &addr_len, 0);
788 nic->eeprom_wc = 1 << addr_len;
789
790 for (addr = 0; addr < nic->eeprom_wc; addr++) {
791 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
792 if (addr < nic->eeprom_wc - 1)
793 checksum += le16_to_cpu(nic->eeprom[addr]);
794 }
795
796
797
798 if (cpu_to_le16(0xBABA - checksum) != nic->eeprom[nic->eeprom_wc - 1]) {
799 netif_err(nic, probe, nic->netdev, "EEPROM corrupted\n");
800 if (!eeprom_bad_csum_allow)
801 return -EAGAIN;
802 }
803
804 return 0;
805}
806
807
808static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
809{
810 u16 addr, addr_len = 8, checksum = 0;
811
812
813 e100_eeprom_read(nic, &addr_len, 0);
814 nic->eeprom_wc = 1 << addr_len;
815
816 if (start + count >= nic->eeprom_wc)
817 return -EINVAL;
818
819 for (addr = start; addr < start + count; addr++)
820 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
821
822
823
824 for (addr = 0; addr < nic->eeprom_wc - 1; addr++)
825 checksum += le16_to_cpu(nic->eeprom[addr]);
826 nic->eeprom[nic->eeprom_wc - 1] = cpu_to_le16(0xBABA - checksum);
827 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
828 nic->eeprom[nic->eeprom_wc - 1]);
829
830 return 0;
831}
832
833#define E100_WAIT_SCB_TIMEOUT 20000
834#define E100_WAIT_SCB_FAST 20
835static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
836{
837 unsigned long flags;
838 unsigned int i;
839 int err = 0;
840
841 spin_lock_irqsave(&nic->cmd_lock, flags);
842
843
844 for (i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
845 if (likely(!ioread8(&nic->csr->scb.cmd_lo)))
846 break;
847 cpu_relax();
848 if (unlikely(i > E100_WAIT_SCB_FAST))
849 udelay(5);
850 }
851 if (unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
852 err = -EAGAIN;
853 goto err_unlock;
854 }
855
856 if (unlikely(cmd != cuc_resume))
857 iowrite32(dma_addr, &nic->csr->scb.gen_ptr);
858 iowrite8(cmd, &nic->csr->scb.cmd_lo);
859
860err_unlock:
861 spin_unlock_irqrestore(&nic->cmd_lock, flags);
862
863 return err;
864}
865
866static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
867 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
868{
869 struct cb *cb;
870 unsigned long flags;
871 int err = 0;
872
873 spin_lock_irqsave(&nic->cb_lock, flags);
874
875 if (unlikely(!nic->cbs_avail)) {
876 err = -ENOMEM;
877 goto err_unlock;
878 }
879
880 cb = nic->cb_to_use;
881 nic->cb_to_use = cb->next;
882 nic->cbs_avail--;
883 cb->skb = skb;
884
885 if (unlikely(!nic->cbs_avail))
886 err = -ENOSPC;
887
888 cb_prepare(nic, cb, skb);
889
890
891
892 cb->command |= cpu_to_le16(cb_s);
893 wmb();
894 cb->prev->command &= cpu_to_le16(~cb_s);
895
896 while (nic->cb_to_send != nic->cb_to_use) {
897 if (unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
898 nic->cb_to_send->dma_addr))) {
899
900
901
902
903
904 if (err == -ENOSPC) {
905
906 schedule_work(&nic->tx_timeout_task);
907 }
908 break;
909 } else {
910 nic->cuc_cmd = cuc_resume;
911 nic->cb_to_send = nic->cb_to_send->next;
912 }
913 }
914
915err_unlock:
916 spin_unlock_irqrestore(&nic->cb_lock, flags);
917
918 return err;
919}
920
921static int mdio_read(struct net_device *netdev, int addr, int reg)
922{
923 struct nic *nic = netdev_priv(netdev);
924 return nic->mdio_ctrl(nic, addr, mdi_read, reg, 0);
925}
926
927static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
928{
929 struct nic *nic = netdev_priv(netdev);
930
931 nic->mdio_ctrl(nic, addr, mdi_write, reg, data);
932}
933
934
935static u16 mdio_ctrl_hw(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
936{
937 u32 data_out = 0;
938 unsigned int i;
939 unsigned long flags;
940
941
942
943
944
945
946
947
948 spin_lock_irqsave(&nic->mdio_lock, flags);
949 for (i = 100; i; --i) {
950 if (ioread32(&nic->csr->mdi_ctrl) & mdi_ready)
951 break;
952 udelay(20);
953 }
954 if (unlikely(!i)) {
955 netdev_err(nic->netdev, "e100.mdio_ctrl won't go Ready\n");
956 spin_unlock_irqrestore(&nic->mdio_lock, flags);
957 return 0;
958 }
959 iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
960
961 for (i = 0; i < 100; i++) {
962 udelay(20);
963 if ((data_out = ioread32(&nic->csr->mdi_ctrl)) & mdi_ready)
964 break;
965 }
966 spin_unlock_irqrestore(&nic->mdio_lock, flags);
967 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
968 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
969 dir == mdi_read ? "READ" : "WRITE",
970 addr, reg, data, data_out);
971 return (u16)data_out;
972}
973
974
975static u16 mdio_ctrl_phy_82552_v(struct nic *nic,
976 u32 addr,
977 u32 dir,
978 u32 reg,
979 u16 data)
980{
981 if ((reg == MII_BMCR) && (dir == mdi_write)) {
982 if (data & (BMCR_ANRESTART | BMCR_ANENABLE)) {
983 u16 advert = mdio_read(nic->netdev, nic->mii.phy_id,
984 MII_ADVERTISE);
985
986
987
988
989
990 if (advert & ADVERTISE_100FULL)
991 data |= BMCR_SPEED100 | BMCR_FULLDPLX;
992 else if (advert & ADVERTISE_100HALF)
993 data |= BMCR_SPEED100;
994 }
995 }
996 return mdio_ctrl_hw(nic, addr, dir, reg, data);
997}
998
999
1000
1001
1002
1003
1004
1005static u16 mdio_ctrl_phy_mii_emulated(struct nic *nic,
1006 u32 addr,
1007 u32 dir,
1008 u32 reg,
1009 u16 data)
1010{
1011
1012
1013
1014
1015 if (dir == mdi_read) {
1016 switch (reg) {
1017 case MII_BMCR:
1018
1019 return BMCR_ANENABLE |
1020 BMCR_FULLDPLX;
1021 case MII_BMSR:
1022 return BMSR_LSTATUS |
1023 BMSR_ANEGCAPABLE |
1024 BMSR_10FULL;
1025 case MII_ADVERTISE:
1026
1027 return ADVERTISE_10HALF |
1028 ADVERTISE_10FULL;
1029 default:
1030 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1031 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1032 dir == mdi_read ? "READ" : "WRITE",
1033 addr, reg, data);
1034 return 0xFFFF;
1035 }
1036 } else {
1037 switch (reg) {
1038 default:
1039 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1040 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1041 dir == mdi_read ? "READ" : "WRITE",
1042 addr, reg, data);
1043 return 0xFFFF;
1044 }
1045 }
1046}
1047static inline int e100_phy_supports_mii(struct nic *nic)
1048{
1049
1050
1051
1052 return (nic->mdio_ctrl != mdio_ctrl_phy_mii_emulated);
1053}
1054
1055static void e100_get_defaults(struct nic *nic)
1056{
1057 struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
1058 struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
1059
1060
1061 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->pdev->revision;
1062 if (nic->mac == mac_unknown)
1063 nic->mac = mac_82557_D100_A;
1064
1065 nic->params.rfds = rfds;
1066 nic->params.cbs = cbs;
1067
1068
1069 nic->tx_threshold = 0xE0;
1070
1071
1072 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |
1073 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));
1074
1075
1076 nic->blank_rfd.command = 0;
1077 nic->blank_rfd.rbd = cpu_to_le32(0xFFFFFFFF);
1078 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
1079
1080
1081 nic->mii.phy_id_mask = 0x1F;
1082 nic->mii.reg_num_mask = 0x1F;
1083 nic->mii.dev = nic->netdev;
1084 nic->mii.mdio_read = mdio_read;
1085 nic->mii.mdio_write = mdio_write;
1086}
1087
1088static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1089{
1090 struct config *config = &cb->u.config;
1091 u8 *c = (u8 *)config;
1092
1093 cb->command = cpu_to_le16(cb_config);
1094
1095 memset(config, 0, sizeof(struct config));
1096
1097 config->byte_count = 0x16;
1098 config->rx_fifo_limit = 0x8;
1099 config->direct_rx_dma = 0x1;
1100 config->standard_tcb = 0x1;
1101 config->standard_stat_counter = 0x1;
1102 config->rx_discard_short_frames = 0x1;
1103 config->tx_underrun_retry = 0x3;
1104 if (e100_phy_supports_mii(nic))
1105 config->mii_mode = 1;
1106 config->pad10 = 0x6;
1107 config->no_source_addr_insertion = 0x1;
1108 config->preamble_length = 0x2;
1109 config->ifs = 0x6;
1110 config->ip_addr_hi = 0xF2;
1111 config->pad15_1 = 0x1;
1112 config->pad15_2 = 0x1;
1113 config->crs_or_cdt = 0x0;
1114 config->fc_delay_hi = 0x40;
1115 config->tx_padding = 0x1;
1116 config->fc_priority_threshold = 0x7;
1117 config->pad18 = 0x1;
1118 config->full_duplex_pin = 0x1;
1119 config->pad20_1 = 0x1F;
1120 config->fc_priority_location = 0x1;
1121 config->pad21_1 = 0x5;
1122
1123 config->adaptive_ifs = nic->adaptive_ifs;
1124 config->loopback = nic->loopback;
1125
1126 if (nic->mii.force_media && nic->mii.full_duplex)
1127 config->full_duplex_force = 0x1;
1128
1129 if (nic->flags & promiscuous || nic->loopback) {
1130 config->rx_save_bad_frames = 0x1;
1131 config->rx_discard_short_frames = 0x0;
1132 config->promiscuous_mode = 0x1;
1133 }
1134
1135 if (nic->flags & multicast_all)
1136 config->multicast_all = 0x1;
1137
1138
1139 if (netif_running(nic->netdev) || !(nic->flags & wol_magic))
1140 config->magic_packet_disable = 0x1;
1141
1142 if (nic->mac >= mac_82558_D101_A4) {
1143 config->fc_disable = 0x1;
1144 config->mwi_enable = 0x1;
1145 config->standard_tcb = 0x0;
1146 config->rx_long_ok = 0x1;
1147 if (nic->mac >= mac_82559_D101M) {
1148 config->tno_intr = 0x1;
1149
1150 if (nic->mac >= mac_82551_10) {
1151 config->byte_count = 0x20;
1152 config->rx_d102_mode = 0x1;
1153 }
1154 } else {
1155 config->standard_stat_counter = 0x0;
1156 }
1157 }
1158
1159 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1160 "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1161 c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
1162 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1163 "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1164 c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
1165 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1166 "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1167 c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
1168}
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225#define BUNDLESMALL 1
1226#define BUNDLEMAX (u16)6
1227#define INTDELAY (u16)1536
1228
1229
1230static const struct firmware *e100_request_firmware(struct nic *nic)
1231{
1232 const char *fw_name;
1233 const struct firmware *fw = nic->fw;
1234 u8 timer, bundle, min_size;
1235 int err = 0;
1236
1237
1238 if (nic->flags & ich)
1239 return NULL;
1240
1241
1242 if (nic->mac == mac_82559_D101M)
1243 fw_name = FIRMWARE_D101M;
1244 else if (nic->mac == mac_82559_D101S)
1245 fw_name = FIRMWARE_D101S;
1246 else if (nic->mac == mac_82551_F || nic->mac == mac_82551_10)
1247 fw_name = FIRMWARE_D102E;
1248 else
1249 return NULL;
1250
1251
1252
1253
1254
1255
1256 if (!fw)
1257 err = request_firmware(&fw, fw_name, &nic->pdev->dev);
1258
1259 if (err) {
1260 netif_err(nic, probe, nic->netdev,
1261 "Failed to load firmware \"%s\": %d\n",
1262 fw_name, err);
1263 return ERR_PTR(err);
1264 }
1265
1266
1267
1268 if (fw->size != UCODE_SIZE * 4 + 3) {
1269 netif_err(nic, probe, nic->netdev,
1270 "Firmware \"%s\" has wrong size %zu\n",
1271 fw_name, fw->size);
1272 release_firmware(fw);
1273 return ERR_PTR(-EINVAL);
1274 }
1275
1276
1277 timer = fw->data[UCODE_SIZE * 4];
1278 bundle = fw->data[UCODE_SIZE * 4 + 1];
1279 min_size = fw->data[UCODE_SIZE * 4 + 2];
1280
1281 if (timer >= UCODE_SIZE || bundle >= UCODE_SIZE ||
1282 min_size >= UCODE_SIZE) {
1283 netif_err(nic, probe, nic->netdev,
1284 "\"%s\" has bogus offset values (0x%x,0x%x,0x%x)\n",
1285 fw_name, timer, bundle, min_size);
1286 release_firmware(fw);
1287 return ERR_PTR(-EINVAL);
1288 }
1289
1290
1291
1292 nic->fw = fw;
1293 return fw;
1294}
1295
1296static void e100_setup_ucode(struct nic *nic, struct cb *cb,
1297 struct sk_buff *skb)
1298{
1299 const struct firmware *fw = (void *)skb;
1300 u8 timer, bundle, min_size;
1301
1302
1303
1304 cb->skb = NULL;
1305
1306
1307 memcpy(cb->u.ucode, fw->data, UCODE_SIZE * 4);
1308
1309
1310 timer = fw->data[UCODE_SIZE * 4];
1311 bundle = fw->data[UCODE_SIZE * 4 + 1];
1312 min_size = fw->data[UCODE_SIZE * 4 + 2];
1313
1314
1315 cb->u.ucode[timer] &= cpu_to_le32(0xFFFF0000);
1316 cb->u.ucode[timer] |= cpu_to_le32(INTDELAY);
1317 cb->u.ucode[bundle] &= cpu_to_le32(0xFFFF0000);
1318 cb->u.ucode[bundle] |= cpu_to_le32(BUNDLEMAX);
1319 cb->u.ucode[min_size] &= cpu_to_le32(0xFFFF0000);
1320 cb->u.ucode[min_size] |= cpu_to_le32((BUNDLESMALL) ? 0xFFFF : 0xFF80);
1321
1322 cb->command = cpu_to_le16(cb_ucode | cb_el);
1323}
1324
1325static inline int e100_load_ucode_wait(struct nic *nic)
1326{
1327 const struct firmware *fw;
1328 int err = 0, counter = 50;
1329 struct cb *cb = nic->cb_to_clean;
1330
1331 fw = e100_request_firmware(nic);
1332
1333 if (!fw || IS_ERR(fw))
1334 return PTR_ERR(fw);
1335
1336 if ((err = e100_exec_cb(nic, (void *)fw, e100_setup_ucode)))
1337 netif_err(nic, probe, nic->netdev,
1338 "ucode cmd failed with error %d\n", err);
1339
1340
1341 nic->cuc_cmd = cuc_start;
1342
1343
1344 e100_write_flush(nic);
1345 udelay(10);
1346
1347
1348 while (!(cb->status & cpu_to_le16(cb_complete))) {
1349 msleep(10);
1350 if (!--counter) break;
1351 }
1352
1353
1354 iowrite8(~0, &nic->csr->scb.stat_ack);
1355
1356
1357 if (!counter || !(cb->status & cpu_to_le16(cb_ok))) {
1358 netif_err(nic, probe, nic->netdev, "ucode load failed\n");
1359 err = -EPERM;
1360 }
1361
1362 return err;
1363}
1364
1365static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1366 struct sk_buff *skb)
1367{
1368 cb->command = cpu_to_le16(cb_iaaddr);
1369 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1370}
1371
1372static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1373{
1374 cb->command = cpu_to_le16(cb_dump);
1375 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1376 offsetof(struct mem, dump_buf));
1377}
1378
1379static int e100_phy_check_without_mii(struct nic *nic)
1380{
1381 u8 phy_type;
1382 int without_mii;
1383
1384 phy_type = (nic->eeprom[eeprom_phy_iface] >> 8) & 0x0f;
1385
1386 switch (phy_type) {
1387 case NoSuchPhy:
1388 case I82503:
1389 case S80C24:
1390
1391
1392
1393
1394
1395
1396 netif_info(nic, probe, nic->netdev,
1397 "found MII-less i82503 or 80c24 or other PHY\n");
1398
1399 nic->mdio_ctrl = mdio_ctrl_phy_mii_emulated;
1400 nic->mii.phy_id = 0;
1401
1402
1403
1404
1405
1406 without_mii = 1;
1407 break;
1408 default:
1409 without_mii = 0;
1410 break;
1411 }
1412 return without_mii;
1413}
1414
1415#define NCONFIG_AUTO_SWITCH 0x0080
1416#define MII_NSC_CONG MII_RESV1
1417#define NSC_CONG_ENABLE 0x0100
1418#define NSC_CONG_TXREADY 0x0400
1419#define ADVERTISE_FC_SUPPORTED 0x0400
1420static int e100_phy_init(struct nic *nic)
1421{
1422 struct net_device *netdev = nic->netdev;
1423 u32 addr;
1424 u16 bmcr, stat, id_lo, id_hi, cong;
1425
1426
1427 for (addr = 0; addr < 32; addr++) {
1428 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1429 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1430 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1431 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1432 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1433 break;
1434 }
1435 if (addr == 32) {
1436
1437
1438
1439
1440 if (e100_phy_check_without_mii(nic))
1441 return 0;
1442 else {
1443
1444 netif_err(nic, hw, nic->netdev,
1445 "Failed to locate any known PHY, aborting\n");
1446 return -EAGAIN;
1447 }
1448 } else
1449 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1450 "phy_addr = %d\n", nic->mii.phy_id);
1451
1452
1453 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1454 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1455 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1456 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1457 "phy ID = 0x%08X\n", nic->phy);
1458
1459
1460 for (addr = 0; addr < 32; addr++) {
1461 if (addr != nic->mii.phy_id) {
1462 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1463 } else if (nic->phy != phy_82552_v) {
1464 bmcr = mdio_read(netdev, addr, MII_BMCR);
1465 mdio_write(netdev, addr, MII_BMCR,
1466 bmcr & ~BMCR_ISOLATE);
1467 }
1468 }
1469
1470
1471
1472
1473
1474 if (nic->phy == phy_82552_v)
1475 mdio_write(netdev, nic->mii.phy_id, MII_BMCR,
1476 bmcr & ~BMCR_ISOLATE);
1477
1478
1479#define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1480 if ((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1481
1482 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1483 cong |= NSC_CONG_TXREADY;
1484 cong &= ~NSC_CONG_ENABLE;
1485 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1486 }
1487
1488 if (nic->phy == phy_82552_v) {
1489 u16 advert = mdio_read(netdev, nic->mii.phy_id, MII_ADVERTISE);
1490
1491
1492 nic->mdio_ctrl = mdio_ctrl_phy_82552_v;
1493
1494
1495 advert |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1496 mdio_write(netdev, nic->mii.phy_id, MII_ADVERTISE, advert);
1497
1498
1499 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1500 bmcr |= BMCR_RESET;
1501 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, bmcr);
1502 } else if ((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
1503 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) &&
1504 !(nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))) {
1505
1506 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1507 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
1508 }
1509
1510 return 0;
1511}
1512
1513static int e100_hw_init(struct nic *nic)
1514{
1515 int err;
1516
1517 e100_hw_reset(nic);
1518
1519 netif_err(nic, hw, nic->netdev, "e100_hw_init\n");
1520 if (!in_interrupt() && (err = e100_self_test(nic)))
1521 return err;
1522
1523 if ((err = e100_phy_init(nic)))
1524 return err;
1525 if ((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1526 return err;
1527 if ((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1528 return err;
1529 if ((err = e100_load_ucode_wait(nic)))
1530 return err;
1531 if ((err = e100_exec_cb(nic, NULL, e100_configure)))
1532 return err;
1533 if ((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1534 return err;
1535 if ((err = e100_exec_cmd(nic, cuc_dump_addr,
1536 nic->dma_addr + offsetof(struct mem, stats))))
1537 return err;
1538 if ((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1539 return err;
1540
1541 e100_disable_irq(nic);
1542
1543 return 0;
1544}
1545
1546static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1547{
1548 struct net_device *netdev = nic->netdev;
1549 struct netdev_hw_addr *ha;
1550 u16 i, count = min(netdev_mc_count(netdev), E100_MAX_MULTICAST_ADDRS);
1551
1552 cb->command = cpu_to_le16(cb_multi);
1553 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1554 i = 0;
1555 netdev_for_each_mc_addr(ha, netdev) {
1556 if (i == count)
1557 break;
1558 memcpy(&cb->u.multi.addr[i++ * ETH_ALEN], &ha->addr,
1559 ETH_ALEN);
1560 }
1561}
1562
1563static void e100_set_multicast_list(struct net_device *netdev)
1564{
1565 struct nic *nic = netdev_priv(netdev);
1566
1567 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1568 "mc_count=%d, flags=0x%04X\n",
1569 netdev_mc_count(netdev), netdev->flags);
1570
1571 if (netdev->flags & IFF_PROMISC)
1572 nic->flags |= promiscuous;
1573 else
1574 nic->flags &= ~promiscuous;
1575
1576 if (netdev->flags & IFF_ALLMULTI ||
1577 netdev_mc_count(netdev) > E100_MAX_MULTICAST_ADDRS)
1578 nic->flags |= multicast_all;
1579 else
1580 nic->flags &= ~multicast_all;
1581
1582 e100_exec_cb(nic, NULL, e100_configure);
1583 e100_exec_cb(nic, NULL, e100_multi);
1584}
1585
1586static void e100_update_stats(struct nic *nic)
1587{
1588 struct net_device *dev = nic->netdev;
1589 struct net_device_stats *ns = &dev->stats;
1590 struct stats *s = &nic->mem->stats;
1591 __le32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1592 (nic->mac < mac_82559_D101M) ? (__le32 *)&s->xmt_tco_frames :
1593 &s->complete;
1594
1595
1596
1597
1598
1599 if (*complete == cpu_to_le32(cuc_dump_reset_complete)) {
1600 *complete = 0;
1601 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1602 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1603 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1604 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1605 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1606 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1607 ns->collisions += nic->tx_collisions;
1608 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1609 le32_to_cpu(s->tx_lost_crs);
1610 ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors) +
1611 nic->rx_over_length_errors;
1612 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1613 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1614 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1615 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
1616 ns->rx_missed_errors += le32_to_cpu(s->rx_resource_errors);
1617 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1618 le32_to_cpu(s->rx_alignment_errors) +
1619 le32_to_cpu(s->rx_short_frame_errors) +
1620 le32_to_cpu(s->rx_cdt_errors);
1621 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1622 nic->tx_single_collisions +=
1623 le32_to_cpu(s->tx_single_collisions);
1624 nic->tx_multiple_collisions +=
1625 le32_to_cpu(s->tx_multiple_collisions);
1626 if (nic->mac >= mac_82558_D101_A4) {
1627 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1628 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1629 nic->rx_fc_unsupported +=
1630 le32_to_cpu(s->fc_rcv_unsupported);
1631 if (nic->mac >= mac_82559_D101M) {
1632 nic->tx_tco_frames +=
1633 le16_to_cpu(s->xmt_tco_frames);
1634 nic->rx_tco_frames +=
1635 le16_to_cpu(s->rcv_tco_frames);
1636 }
1637 }
1638 }
1639
1640
1641 if (e100_exec_cmd(nic, cuc_dump_reset, 0))
1642 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1643 "exec cuc_dump_reset failed\n");
1644}
1645
1646static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1647{
1648
1649
1650
1651 if (duplex == DUPLEX_HALF) {
1652 u32 prev = nic->adaptive_ifs;
1653 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1654
1655 if ((nic->tx_frames / 32 < nic->tx_collisions) &&
1656 (nic->tx_frames > min_frames)) {
1657 if (nic->adaptive_ifs < 60)
1658 nic->adaptive_ifs += 5;
1659 } else if (nic->tx_frames < min_frames) {
1660 if (nic->adaptive_ifs >= 5)
1661 nic->adaptive_ifs -= 5;
1662 }
1663 if (nic->adaptive_ifs != prev)
1664 e100_exec_cb(nic, NULL, e100_configure);
1665 }
1666}
1667
1668static void e100_watchdog(unsigned long data)
1669{
1670 struct nic *nic = (struct nic *)data;
1671 struct ethtool_cmd cmd;
1672
1673 netif_printk(nic, timer, KERN_DEBUG, nic->netdev,
1674 "right now = %ld\n", jiffies);
1675
1676
1677
1678 mii_ethtool_gset(&nic->mii, &cmd);
1679
1680 if (mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1681 netdev_info(nic->netdev, "NIC Link is Up %u Mbps %s Duplex\n",
1682 cmd.speed == SPEED_100 ? 100 : 10,
1683 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1684 } else if (!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1685 netdev_info(nic->netdev, "NIC Link is Down\n");
1686 }
1687
1688 mii_check_link(&nic->mii);
1689
1690
1691
1692
1693
1694
1695 spin_lock_irq(&nic->cmd_lock);
1696 iowrite8(ioread8(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1697 e100_write_flush(nic);
1698 spin_unlock_irq(&nic->cmd_lock);
1699
1700 e100_update_stats(nic);
1701 e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);
1702
1703 if (nic->mac <= mac_82557_D100_C)
1704
1705 e100_set_multicast_list(nic->netdev);
1706
1707 if (nic->flags & ich && cmd.speed==SPEED_10 && cmd.duplex==DUPLEX_HALF)
1708
1709 nic->flags |= ich_10h_workaround;
1710 else
1711 nic->flags &= ~ich_10h_workaround;
1712
1713 mod_timer(&nic->watchdog,
1714 round_jiffies(jiffies + E100_WATCHDOG_PERIOD));
1715}
1716
1717static void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1718 struct sk_buff *skb)
1719{
1720 cb->command = nic->tx_command;
1721
1722 if ((nic->cbs_avail & ~15) == nic->cbs_avail)
1723 cb->command |= cpu_to_le16(cb_i);
1724 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1725 cb->u.tcb.tcb_byte_count = 0;
1726 cb->u.tcb.threshold = nic->tx_threshold;
1727 cb->u.tcb.tbd_count = 1;
1728 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1729 skb->data, skb->len, PCI_DMA_TODEVICE));
1730
1731 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1732}
1733
1734static netdev_tx_t e100_xmit_frame(struct sk_buff *skb,
1735 struct net_device *netdev)
1736{
1737 struct nic *nic = netdev_priv(netdev);
1738 int err;
1739
1740 if (nic->flags & ich_10h_workaround) {
1741
1742
1743
1744 if (e100_exec_cmd(nic, cuc_nop, 0))
1745 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1746 "exec cuc_nop failed\n");
1747 udelay(1);
1748 }
1749
1750 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1751
1752 switch (err) {
1753 case -ENOSPC:
1754
1755 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1756 "No space for CB\n");
1757 netif_stop_queue(netdev);
1758 break;
1759 case -ENOMEM:
1760
1761 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1762 "Out of Tx resources, returning skb\n");
1763 netif_stop_queue(netdev);
1764 return NETDEV_TX_BUSY;
1765 }
1766
1767 return NETDEV_TX_OK;
1768}
1769
1770static int e100_tx_clean(struct nic *nic)
1771{
1772 struct net_device *dev = nic->netdev;
1773 struct cb *cb;
1774 int tx_cleaned = 0;
1775
1776 spin_lock(&nic->cb_lock);
1777
1778
1779 for (cb = nic->cb_to_clean;
1780 cb->status & cpu_to_le16(cb_complete);
1781 cb = nic->cb_to_clean = cb->next) {
1782 rmb();
1783 netif_printk(nic, tx_done, KERN_DEBUG, nic->netdev,
1784 "cb[%d]->status = 0x%04X\n",
1785 (int)(((void*)cb - (void*)nic->cbs)/sizeof(struct cb)),
1786 cb->status);
1787
1788 if (likely(cb->skb != NULL)) {
1789 dev->stats.tx_packets++;
1790 dev->stats.tx_bytes += cb->skb->len;
1791
1792 pci_unmap_single(nic->pdev,
1793 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1794 le16_to_cpu(cb->u.tcb.tbd.size),
1795 PCI_DMA_TODEVICE);
1796 dev_kfree_skb_any(cb->skb);
1797 cb->skb = NULL;
1798 tx_cleaned = 1;
1799 }
1800 cb->status = 0;
1801 nic->cbs_avail++;
1802 }
1803
1804 spin_unlock(&nic->cb_lock);
1805
1806
1807 if (unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1808 netif_wake_queue(nic->netdev);
1809
1810 return tx_cleaned;
1811}
1812
1813static void e100_clean_cbs(struct nic *nic)
1814{
1815 if (nic->cbs) {
1816 while (nic->cbs_avail != nic->params.cbs.count) {
1817 struct cb *cb = nic->cb_to_clean;
1818 if (cb->skb) {
1819 pci_unmap_single(nic->pdev,
1820 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1821 le16_to_cpu(cb->u.tcb.tbd.size),
1822 PCI_DMA_TODEVICE);
1823 dev_kfree_skb(cb->skb);
1824 }
1825 nic->cb_to_clean = nic->cb_to_clean->next;
1826 nic->cbs_avail++;
1827 }
1828 pci_pool_free(nic->cbs_pool, nic->cbs, nic->cbs_dma_addr);
1829 nic->cbs = NULL;
1830 nic->cbs_avail = 0;
1831 }
1832 nic->cuc_cmd = cuc_start;
1833 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1834 nic->cbs;
1835}
1836
1837static int e100_alloc_cbs(struct nic *nic)
1838{
1839 struct cb *cb;
1840 unsigned int i, count = nic->params.cbs.count;
1841
1842 nic->cuc_cmd = cuc_start;
1843 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1844 nic->cbs_avail = 0;
1845
1846 nic->cbs = pci_pool_alloc(nic->cbs_pool, GFP_KERNEL,
1847 &nic->cbs_dma_addr);
1848 if (!nic->cbs)
1849 return -ENOMEM;
1850 memset(nic->cbs, 0, count * sizeof(struct cb));
1851
1852 for (cb = nic->cbs, i = 0; i < count; cb++, i++) {
1853 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1854 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1855
1856 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1857 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1858 ((i+1) % count) * sizeof(struct cb));
1859 }
1860
1861 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1862 nic->cbs_avail = count;
1863
1864 return 0;
1865}
1866
1867static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1868{
1869 if (!nic->rxs) return;
1870 if (RU_SUSPENDED != nic->ru_running) return;
1871
1872
1873 if (!rx) rx = nic->rxs;
1874
1875
1876 if (rx->skb) {
1877 e100_exec_cmd(nic, ruc_start, rx->dma_addr);
1878 nic->ru_running = RU_RUNNING;
1879 }
1880}
1881
1882#define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
1883static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1884{
1885 if (!(rx->skb = netdev_alloc_skb_ip_align(nic->netdev, RFD_BUF_LEN)))
1886 return -ENOMEM;
1887
1888
1889 skb_copy_to_linear_data(rx->skb, &nic->blank_rfd, sizeof(struct rfd));
1890 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1891 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1892
1893 if (pci_dma_mapping_error(nic->pdev, rx->dma_addr)) {
1894 dev_kfree_skb_any(rx->skb);
1895 rx->skb = NULL;
1896 rx->dma_addr = 0;
1897 return -ENOMEM;
1898 }
1899
1900
1901
1902
1903 if (rx->prev->skb) {
1904 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1905 put_unaligned_le32(rx->dma_addr, &prev_rfd->link);
1906 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
1907 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1908 }
1909
1910 return 0;
1911}
1912
1913static int e100_rx_indicate(struct nic *nic, struct rx *rx,
1914 unsigned int *work_done, unsigned int work_to_do)
1915{
1916 struct net_device *dev = nic->netdev;
1917 struct sk_buff *skb = rx->skb;
1918 struct rfd *rfd = (struct rfd *)skb->data;
1919 u16 rfd_status, actual_size;
1920
1921 if (unlikely(work_done && *work_done >= work_to_do))
1922 return -EAGAIN;
1923
1924
1925 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
1926 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1927 rfd_status = le16_to_cpu(rfd->status);
1928
1929 netif_printk(nic, rx_status, KERN_DEBUG, nic->netdev,
1930 "status=0x%04X\n", rfd_status);
1931 rmb();
1932
1933
1934 if (unlikely(!(rfd_status & cb_complete))) {
1935
1936
1937
1938
1939
1940 if ((le16_to_cpu(rfd->command) & cb_el) &&
1941 (RU_RUNNING == nic->ru_running))
1942
1943 if (ioread8(&nic->csr->scb.status) & rus_no_res)
1944 nic->ru_running = RU_SUSPENDED;
1945 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
1946 sizeof(struct rfd),
1947 PCI_DMA_FROMDEVICE);
1948 return -ENODATA;
1949 }
1950
1951
1952 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1953 if (unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1954 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1955
1956
1957 pci_unmap_single(nic->pdev, rx->dma_addr,
1958 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1959
1960
1961
1962
1963
1964
1965
1966 if ((le16_to_cpu(rfd->command) & cb_el) &&
1967 (RU_RUNNING == nic->ru_running)) {
1968
1969 if (ioread8(&nic->csr->scb.status) & rus_no_res)
1970 nic->ru_running = RU_SUSPENDED;
1971 }
1972
1973
1974 skb_reserve(skb, sizeof(struct rfd));
1975 skb_put(skb, actual_size);
1976 skb->protocol = eth_type_trans(skb, nic->netdev);
1977
1978 if (unlikely(!(rfd_status & cb_ok))) {
1979
1980 dev_kfree_skb_any(skb);
1981 } else if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN) {
1982
1983 nic->rx_over_length_errors++;
1984 dev_kfree_skb_any(skb);
1985 } else {
1986 dev->stats.rx_packets++;
1987 dev->stats.rx_bytes += actual_size;
1988 netif_receive_skb(skb);
1989 if (work_done)
1990 (*work_done)++;
1991 }
1992
1993 rx->skb = NULL;
1994
1995 return 0;
1996}
1997
1998static void e100_rx_clean(struct nic *nic, unsigned int *work_done,
1999 unsigned int work_to_do)
2000{
2001 struct rx *rx;
2002 int restart_required = 0, err = 0;
2003 struct rx *old_before_last_rx, *new_before_last_rx;
2004 struct rfd *old_before_last_rfd, *new_before_last_rfd;
2005
2006
2007 for (rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
2008 err = e100_rx_indicate(nic, rx, work_done, work_to_do);
2009
2010 if (-EAGAIN == err || -ENODATA == err)
2011 break;
2012 }
2013
2014
2015
2016
2017
2018
2019
2020
2021 if (-EAGAIN != err && RU_SUSPENDED == nic->ru_running)
2022 restart_required = 1;
2023
2024 old_before_last_rx = nic->rx_to_use->prev->prev;
2025 old_before_last_rfd = (struct rfd *)old_before_last_rx->skb->data;
2026
2027
2028 for (rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
2029 if (unlikely(e100_rx_alloc_skb(nic, rx)))
2030 break;
2031 }
2032
2033 new_before_last_rx = nic->rx_to_use->prev->prev;
2034 if (new_before_last_rx != old_before_last_rx) {
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044 new_before_last_rfd =
2045 (struct rfd *)new_before_last_rx->skb->data;
2046 new_before_last_rfd->size = 0;
2047 new_before_last_rfd->command |= cpu_to_le16(cb_el);
2048 pci_dma_sync_single_for_device(nic->pdev,
2049 new_before_last_rx->dma_addr, sizeof(struct rfd),
2050 PCI_DMA_BIDIRECTIONAL);
2051
2052
2053
2054
2055 old_before_last_rfd->command &= ~cpu_to_le16(cb_el);
2056 pci_dma_sync_single_for_device(nic->pdev,
2057 old_before_last_rx->dma_addr, sizeof(struct rfd),
2058 PCI_DMA_BIDIRECTIONAL);
2059 old_before_last_rfd->size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
2060 pci_dma_sync_single_for_device(nic->pdev,
2061 old_before_last_rx->dma_addr, sizeof(struct rfd),
2062 PCI_DMA_BIDIRECTIONAL);
2063 }
2064
2065 if (restart_required) {
2066
2067 iowrite8(stat_ack_rnr, &nic->csr->scb.stat_ack);
2068 e100_start_receiver(nic, nic->rx_to_clean);
2069 if (work_done)
2070 (*work_done)++;
2071 }
2072}
2073
2074static void e100_rx_clean_list(struct nic *nic)
2075{
2076 struct rx *rx;
2077 unsigned int i, count = nic->params.rfds.count;
2078
2079 nic->ru_running = RU_UNINITIALIZED;
2080
2081 if (nic->rxs) {
2082 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2083 if (rx->skb) {
2084 pci_unmap_single(nic->pdev, rx->dma_addr,
2085 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
2086 dev_kfree_skb(rx->skb);
2087 }
2088 }
2089 kfree(nic->rxs);
2090 nic->rxs = NULL;
2091 }
2092
2093 nic->rx_to_use = nic->rx_to_clean = NULL;
2094}
2095
2096static int e100_rx_alloc_list(struct nic *nic)
2097{
2098 struct rx *rx;
2099 unsigned int i, count = nic->params.rfds.count;
2100 struct rfd *before_last;
2101
2102 nic->rx_to_use = nic->rx_to_clean = NULL;
2103 nic->ru_running = RU_UNINITIALIZED;
2104
2105 if (!(nic->rxs = kcalloc(count, sizeof(struct rx), GFP_ATOMIC)))
2106 return -ENOMEM;
2107
2108 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2109 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
2110 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
2111 if (e100_rx_alloc_skb(nic, rx)) {
2112 e100_rx_clean_list(nic);
2113 return -ENOMEM;
2114 }
2115 }
2116
2117
2118
2119
2120
2121
2122
2123 rx = nic->rxs->prev->prev;
2124 before_last = (struct rfd *)rx->skb->data;
2125 before_last->command |= cpu_to_le16(cb_el);
2126 before_last->size = 0;
2127 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
2128 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
2129
2130 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
2131 nic->ru_running = RU_SUSPENDED;
2132
2133 return 0;
2134}
2135
2136static irqreturn_t e100_intr(int irq, void *dev_id)
2137{
2138 struct net_device *netdev = dev_id;
2139 struct nic *nic = netdev_priv(netdev);
2140 u8 stat_ack = ioread8(&nic->csr->scb.stat_ack);
2141
2142 netif_printk(nic, intr, KERN_DEBUG, nic->netdev,
2143 "stat_ack = 0x%02X\n", stat_ack);
2144
2145 if (stat_ack == stat_ack_not_ours ||
2146 stat_ack == stat_ack_not_present)
2147 return IRQ_NONE;
2148
2149
2150 iowrite8(stat_ack, &nic->csr->scb.stat_ack);
2151
2152
2153 if (stat_ack & stat_ack_rnr)
2154 nic->ru_running = RU_SUSPENDED;
2155
2156 if (likely(napi_schedule_prep(&nic->napi))) {
2157 e100_disable_irq(nic);
2158 __napi_schedule(&nic->napi);
2159 }
2160
2161 return IRQ_HANDLED;
2162}
2163
2164static int e100_poll(struct napi_struct *napi, int budget)
2165{
2166 struct nic *nic = container_of(napi, struct nic, napi);
2167 unsigned int work_done = 0;
2168
2169 e100_rx_clean(nic, &work_done, budget);
2170 e100_tx_clean(nic);
2171
2172
2173 if (work_done < budget) {
2174 napi_complete(napi);
2175 e100_enable_irq(nic);
2176 }
2177
2178 return work_done;
2179}
2180
2181#ifdef CONFIG_NET_POLL_CONTROLLER
2182static void e100_netpoll(struct net_device *netdev)
2183{
2184 struct nic *nic = netdev_priv(netdev);
2185
2186 e100_disable_irq(nic);
2187 e100_intr(nic->pdev->irq, netdev);
2188 e100_tx_clean(nic);
2189 e100_enable_irq(nic);
2190}
2191#endif
2192
2193static int e100_set_mac_address(struct net_device *netdev, void *p)
2194{
2195 struct nic *nic = netdev_priv(netdev);
2196 struct sockaddr *addr = p;
2197
2198 if (!is_valid_ether_addr(addr->sa_data))
2199 return -EADDRNOTAVAIL;
2200
2201 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2202 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
2203
2204 return 0;
2205}
2206
2207static int e100_change_mtu(struct net_device *netdev, int new_mtu)
2208{
2209 if (new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
2210 return -EINVAL;
2211 netdev->mtu = new_mtu;
2212 return 0;
2213}
2214
2215static int e100_asf(struct nic *nic)
2216{
2217
2218 return (nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
2219 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
2220 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
2221 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE);
2222}
2223
2224static int e100_up(struct nic *nic)
2225{
2226 int err;
2227
2228 if ((err = e100_rx_alloc_list(nic)))
2229 return err;
2230 if ((err = e100_alloc_cbs(nic)))
2231 goto err_rx_clean_list;
2232 if ((err = e100_hw_init(nic)))
2233 goto err_clean_cbs;
2234 e100_set_multicast_list(nic->netdev);
2235 e100_start_receiver(nic, NULL);
2236 mod_timer(&nic->watchdog, jiffies);
2237 if ((err = request_irq(nic->pdev->irq, e100_intr, IRQF_SHARED,
2238 nic->netdev->name, nic->netdev)))
2239 goto err_no_irq;
2240 netif_wake_queue(nic->netdev);
2241 napi_enable(&nic->napi);
2242
2243
2244 e100_enable_irq(nic);
2245 return 0;
2246
2247err_no_irq:
2248 del_timer_sync(&nic->watchdog);
2249err_clean_cbs:
2250 e100_clean_cbs(nic);
2251err_rx_clean_list:
2252 e100_rx_clean_list(nic);
2253 return err;
2254}
2255
2256static void e100_down(struct nic *nic)
2257{
2258
2259 napi_disable(&nic->napi);
2260 netif_stop_queue(nic->netdev);
2261 e100_hw_reset(nic);
2262 free_irq(nic->pdev->irq, nic->netdev);
2263 del_timer_sync(&nic->watchdog);
2264 netif_carrier_off(nic->netdev);
2265 e100_clean_cbs(nic);
2266 e100_rx_clean_list(nic);
2267}
2268
2269static void e100_tx_timeout(struct net_device *netdev)
2270{
2271 struct nic *nic = netdev_priv(netdev);
2272
2273
2274
2275 schedule_work(&nic->tx_timeout_task);
2276}
2277
2278static void e100_tx_timeout_task(struct work_struct *work)
2279{
2280 struct nic *nic = container_of(work, struct nic, tx_timeout_task);
2281 struct net_device *netdev = nic->netdev;
2282
2283 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
2284 "scb.status=0x%02X\n", ioread8(&nic->csr->scb.status));
2285
2286 rtnl_lock();
2287 if (netif_running(netdev)) {
2288 e100_down(netdev_priv(netdev));
2289 e100_up(netdev_priv(netdev));
2290 }
2291 rtnl_unlock();
2292}
2293
2294static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
2295{
2296 int err;
2297 struct sk_buff *skb;
2298
2299
2300
2301
2302
2303
2304 if ((err = e100_rx_alloc_list(nic)))
2305 return err;
2306 if ((err = e100_alloc_cbs(nic)))
2307 goto err_clean_rx;
2308
2309
2310 if (nic->flags & ich && loopback_mode == lb_phy)
2311 loopback_mode = lb_mac;
2312
2313 nic->loopback = loopback_mode;
2314 if ((err = e100_hw_init(nic)))
2315 goto err_loopback_none;
2316
2317 if (loopback_mode == lb_phy)
2318 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
2319 BMCR_LOOPBACK);
2320
2321 e100_start_receiver(nic, NULL);
2322
2323 if (!(skb = netdev_alloc_skb(nic->netdev, ETH_DATA_LEN))) {
2324 err = -ENOMEM;
2325 goto err_loopback_none;
2326 }
2327 skb_put(skb, ETH_DATA_LEN);
2328 memset(skb->data, 0xFF, ETH_DATA_LEN);
2329 e100_xmit_frame(skb, nic->netdev);
2330
2331 msleep(10);
2332
2333 pci_dma_sync_single_for_cpu(nic->pdev, nic->rx_to_clean->dma_addr,
2334 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
2335
2336 if (memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
2337 skb->data, ETH_DATA_LEN))
2338 err = -EAGAIN;
2339
2340err_loopback_none:
2341 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
2342 nic->loopback = lb_none;
2343 e100_clean_cbs(nic);
2344 e100_hw_reset(nic);
2345err_clean_rx:
2346 e100_rx_clean_list(nic);
2347 return err;
2348}
2349
2350#define MII_LED_CONTROL 0x1B
2351#define E100_82552_LED_OVERRIDE 0x19
2352#define E100_82552_LED_ON 0x000F
2353#define E100_82552_LED_OFF 0x000A
2354static void e100_blink_led(unsigned long data)
2355{
2356 struct nic *nic = (struct nic *)data;
2357 enum led_state {
2358 led_on = 0x01,
2359 led_off = 0x04,
2360 led_on_559 = 0x05,
2361 led_on_557 = 0x07,
2362 };
2363 u16 led_reg = MII_LED_CONTROL;
2364
2365 if (nic->phy == phy_82552_v) {
2366 led_reg = E100_82552_LED_OVERRIDE;
2367
2368 nic->leds = (nic->leds == E100_82552_LED_ON) ?
2369 E100_82552_LED_OFF : E100_82552_LED_ON;
2370 } else {
2371 nic->leds = (nic->leds & led_on) ? led_off :
2372 (nic->mac < mac_82559_D101M) ? led_on_557 :
2373 led_on_559;
2374 }
2375 mdio_write(nic->netdev, nic->mii.phy_id, led_reg, nic->leds);
2376 mod_timer(&nic->blink_timer, jiffies + HZ / 4);
2377}
2378
2379static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2380{
2381 struct nic *nic = netdev_priv(netdev);
2382 return mii_ethtool_gset(&nic->mii, cmd);
2383}
2384
2385static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2386{
2387 struct nic *nic = netdev_priv(netdev);
2388 int err;
2389
2390 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
2391 err = mii_ethtool_sset(&nic->mii, cmd);
2392 e100_exec_cb(nic, NULL, e100_configure);
2393
2394 return err;
2395}
2396
2397static void e100_get_drvinfo(struct net_device *netdev,
2398 struct ethtool_drvinfo *info)
2399{
2400 struct nic *nic = netdev_priv(netdev);
2401 strcpy(info->driver, DRV_NAME);
2402 strcpy(info->version, DRV_VERSION);
2403 strcpy(info->fw_version, "N/A");
2404 strcpy(info->bus_info, pci_name(nic->pdev));
2405}
2406
2407#define E100_PHY_REGS 0x1C
2408static int e100_get_regs_len(struct net_device *netdev)
2409{
2410 struct nic *nic = netdev_priv(netdev);
2411 return 1 + E100_PHY_REGS + sizeof(nic->mem->dump_buf);
2412}
2413
2414static void e100_get_regs(struct net_device *netdev,
2415 struct ethtool_regs *regs, void *p)
2416{
2417 struct nic *nic = netdev_priv(netdev);
2418 u32 *buff = p;
2419 int i;
2420
2421 regs->version = (1 << 24) | nic->pdev->revision;
2422 buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 |
2423 ioread8(&nic->csr->scb.cmd_lo) << 16 |
2424 ioread16(&nic->csr->scb.status);
2425 for (i = E100_PHY_REGS; i >= 0; i--)
2426 buff[1 + E100_PHY_REGS - i] =
2427 mdio_read(netdev, nic->mii.phy_id, i);
2428 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
2429 e100_exec_cb(nic, NULL, e100_dump);
2430 msleep(10);
2431 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
2432 sizeof(nic->mem->dump_buf));
2433}
2434
2435static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2436{
2437 struct nic *nic = netdev_priv(netdev);
2438 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
2439 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
2440}
2441
2442static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2443{
2444 struct nic *nic = netdev_priv(netdev);
2445
2446 if ((wol->wolopts && wol->wolopts != WAKE_MAGIC) ||
2447 !device_can_wakeup(&nic->pdev->dev))
2448 return -EOPNOTSUPP;
2449
2450 if (wol->wolopts)
2451 nic->flags |= wol_magic;
2452 else
2453 nic->flags &= ~wol_magic;
2454
2455 device_set_wakeup_enable(&nic->pdev->dev, wol->wolopts);
2456
2457 e100_exec_cb(nic, NULL, e100_configure);
2458
2459 return 0;
2460}
2461
2462static u32 e100_get_msglevel(struct net_device *netdev)
2463{
2464 struct nic *nic = netdev_priv(netdev);
2465 return nic->msg_enable;
2466}
2467
2468static void e100_set_msglevel(struct net_device *netdev, u32 value)
2469{
2470 struct nic *nic = netdev_priv(netdev);
2471 nic->msg_enable = value;
2472}
2473
2474static int e100_nway_reset(struct net_device *netdev)
2475{
2476 struct nic *nic = netdev_priv(netdev);
2477 return mii_nway_restart(&nic->mii);
2478}
2479
2480static u32 e100_get_link(struct net_device *netdev)
2481{
2482 struct nic *nic = netdev_priv(netdev);
2483 return mii_link_ok(&nic->mii);
2484}
2485
2486static int e100_get_eeprom_len(struct net_device *netdev)
2487{
2488 struct nic *nic = netdev_priv(netdev);
2489 return nic->eeprom_wc << 1;
2490}
2491
2492#define E100_EEPROM_MAGIC 0x1234
2493static int e100_get_eeprom(struct net_device *netdev,
2494 struct ethtool_eeprom *eeprom, u8 *bytes)
2495{
2496 struct nic *nic = netdev_priv(netdev);
2497
2498 eeprom->magic = E100_EEPROM_MAGIC;
2499 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
2500
2501 return 0;
2502}
2503
2504static int e100_set_eeprom(struct net_device *netdev,
2505 struct ethtool_eeprom *eeprom, u8 *bytes)
2506{
2507 struct nic *nic = netdev_priv(netdev);
2508
2509 if (eeprom->magic != E100_EEPROM_MAGIC)
2510 return -EINVAL;
2511
2512 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
2513
2514 return e100_eeprom_save(nic, eeprom->offset >> 1,
2515 (eeprom->len >> 1) + 1);
2516}
2517
2518static void e100_get_ringparam(struct net_device *netdev,
2519 struct ethtool_ringparam *ring)
2520{
2521 struct nic *nic = netdev_priv(netdev);
2522 struct param_range *rfds = &nic->params.rfds;
2523 struct param_range *cbs = &nic->params.cbs;
2524
2525 ring->rx_max_pending = rfds->max;
2526 ring->tx_max_pending = cbs->max;
2527 ring->rx_mini_max_pending = 0;
2528 ring->rx_jumbo_max_pending = 0;
2529 ring->rx_pending = rfds->count;
2530 ring->tx_pending = cbs->count;
2531 ring->rx_mini_pending = 0;
2532 ring->rx_jumbo_pending = 0;
2533}
2534
2535static int e100_set_ringparam(struct net_device *netdev,
2536 struct ethtool_ringparam *ring)
2537{
2538 struct nic *nic = netdev_priv(netdev);
2539 struct param_range *rfds = &nic->params.rfds;
2540 struct param_range *cbs = &nic->params.cbs;
2541
2542 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2543 return -EINVAL;
2544
2545 if (netif_running(netdev))
2546 e100_down(nic);
2547 rfds->count = max(ring->rx_pending, rfds->min);
2548 rfds->count = min(rfds->count, rfds->max);
2549 cbs->count = max(ring->tx_pending, cbs->min);
2550 cbs->count = min(cbs->count, cbs->max);
2551 netif_info(nic, drv, nic->netdev, "Ring Param settings: rx: %d, tx %d\n",
2552 rfds->count, cbs->count);
2553 if (netif_running(netdev))
2554 e100_up(nic);
2555
2556 return 0;
2557}
2558
2559static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
2560 "Link test (on/offline)",
2561 "Eeprom test (on/offline)",
2562 "Self test (offline)",
2563 "Mac loopback (offline)",
2564 "Phy loopback (offline)",
2565};
2566#define E100_TEST_LEN ARRAY_SIZE(e100_gstrings_test)
2567
2568static void e100_diag_test(struct net_device *netdev,
2569 struct ethtool_test *test, u64 *data)
2570{
2571 struct ethtool_cmd cmd;
2572 struct nic *nic = netdev_priv(netdev);
2573 int i, err;
2574
2575 memset(data, 0, E100_TEST_LEN * sizeof(u64));
2576 data[0] = !mii_link_ok(&nic->mii);
2577 data[1] = e100_eeprom_load(nic);
2578 if (test->flags & ETH_TEST_FL_OFFLINE) {
2579
2580
2581 err = mii_ethtool_gset(&nic->mii, &cmd);
2582
2583 if (netif_running(netdev))
2584 e100_down(nic);
2585 data[2] = e100_self_test(nic);
2586 data[3] = e100_loopback_test(nic, lb_mac);
2587 data[4] = e100_loopback_test(nic, lb_phy);
2588
2589
2590 err = mii_ethtool_sset(&nic->mii, &cmd);
2591
2592 if (netif_running(netdev))
2593 e100_up(nic);
2594 }
2595 for (i = 0; i < E100_TEST_LEN; i++)
2596 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
2597
2598 msleep_interruptible(4 * 1000);
2599}
2600
2601static int e100_phys_id(struct net_device *netdev, u32 data)
2602{
2603 struct nic *nic = netdev_priv(netdev);
2604 u16 led_reg = (nic->phy == phy_82552_v) ? E100_82552_LED_OVERRIDE :
2605 MII_LED_CONTROL;
2606
2607 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
2608 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
2609 mod_timer(&nic->blink_timer, jiffies);
2610 msleep_interruptible(data * 1000);
2611 del_timer_sync(&nic->blink_timer);
2612 mdio_write(netdev, nic->mii.phy_id, led_reg, 0);
2613
2614 return 0;
2615}
2616
2617static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2618 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2619 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2620 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2621 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2622 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2623 "tx_heartbeat_errors", "tx_window_errors",
2624
2625 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2626 "tx_flow_control_pause", "rx_flow_control_pause",
2627 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2628};
2629#define E100_NET_STATS_LEN 21
2630#define E100_STATS_LEN ARRAY_SIZE(e100_gstrings_stats)
2631
2632static int e100_get_sset_count(struct net_device *netdev, int sset)
2633{
2634 switch (sset) {
2635 case ETH_SS_TEST:
2636 return E100_TEST_LEN;
2637 case ETH_SS_STATS:
2638 return E100_STATS_LEN;
2639 default:
2640 return -EOPNOTSUPP;
2641 }
2642}
2643
2644static void e100_get_ethtool_stats(struct net_device *netdev,
2645 struct ethtool_stats *stats, u64 *data)
2646{
2647 struct nic *nic = netdev_priv(netdev);
2648 int i;
2649
2650 for (i = 0; i < E100_NET_STATS_LEN; i++)
2651 data[i] = ((unsigned long *)&netdev->stats)[i];
2652
2653 data[i++] = nic->tx_deferred;
2654 data[i++] = nic->tx_single_collisions;
2655 data[i++] = nic->tx_multiple_collisions;
2656 data[i++] = nic->tx_fc_pause;
2657 data[i++] = nic->rx_fc_pause;
2658 data[i++] = nic->rx_fc_unsupported;
2659 data[i++] = nic->tx_tco_frames;
2660 data[i++] = nic->rx_tco_frames;
2661}
2662
2663static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2664{
2665 switch (stringset) {
2666 case ETH_SS_TEST:
2667 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2668 break;
2669 case ETH_SS_STATS:
2670 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2671 break;
2672 }
2673}
2674
2675static const struct ethtool_ops e100_ethtool_ops = {
2676 .get_settings = e100_get_settings,
2677 .set_settings = e100_set_settings,
2678 .get_drvinfo = e100_get_drvinfo,
2679 .get_regs_len = e100_get_regs_len,
2680 .get_regs = e100_get_regs,
2681 .get_wol = e100_get_wol,
2682 .set_wol = e100_set_wol,
2683 .get_msglevel = e100_get_msglevel,
2684 .set_msglevel = e100_set_msglevel,
2685 .nway_reset = e100_nway_reset,
2686 .get_link = e100_get_link,
2687 .get_eeprom_len = e100_get_eeprom_len,
2688 .get_eeprom = e100_get_eeprom,
2689 .set_eeprom = e100_set_eeprom,
2690 .get_ringparam = e100_get_ringparam,
2691 .set_ringparam = e100_set_ringparam,
2692 .self_test = e100_diag_test,
2693 .get_strings = e100_get_strings,
2694 .phys_id = e100_phys_id,
2695 .get_ethtool_stats = e100_get_ethtool_stats,
2696 .get_sset_count = e100_get_sset_count,
2697};
2698
2699static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2700{
2701 struct nic *nic = netdev_priv(netdev);
2702
2703 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2704}
2705
2706static int e100_alloc(struct nic *nic)
2707{
2708 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2709 &nic->dma_addr);
2710 return nic->mem ? 0 : -ENOMEM;
2711}
2712
2713static void e100_free(struct nic *nic)
2714{
2715 if (nic->mem) {
2716 pci_free_consistent(nic->pdev, sizeof(struct mem),
2717 nic->mem, nic->dma_addr);
2718 nic->mem = NULL;
2719 }
2720}
2721
2722static int e100_open(struct net_device *netdev)
2723{
2724 struct nic *nic = netdev_priv(netdev);
2725 int err = 0;
2726
2727 netif_carrier_off(netdev);
2728 if ((err = e100_up(nic)))
2729 netif_err(nic, ifup, nic->netdev, "Cannot open interface, aborting\n");
2730 return err;
2731}
2732
2733static int e100_close(struct net_device *netdev)
2734{
2735 e100_down(netdev_priv(netdev));
2736 return 0;
2737}
2738
2739static const struct net_device_ops e100_netdev_ops = {
2740 .ndo_open = e100_open,
2741 .ndo_stop = e100_close,
2742 .ndo_start_xmit = e100_xmit_frame,
2743 .ndo_validate_addr = eth_validate_addr,
2744 .ndo_set_multicast_list = e100_set_multicast_list,
2745 .ndo_set_mac_address = e100_set_mac_address,
2746 .ndo_change_mtu = e100_change_mtu,
2747 .ndo_do_ioctl = e100_do_ioctl,
2748 .ndo_tx_timeout = e100_tx_timeout,
2749#ifdef CONFIG_NET_POLL_CONTROLLER
2750 .ndo_poll_controller = e100_netpoll,
2751#endif
2752};
2753
2754static int __devinit e100_probe(struct pci_dev *pdev,
2755 const struct pci_device_id *ent)
2756{
2757 struct net_device *netdev;
2758 struct nic *nic;
2759 int err;
2760
2761 if (!(netdev = alloc_etherdev(sizeof(struct nic)))) {
2762 if (((1 << debug) - 1) & NETIF_MSG_PROBE)
2763 pr_err("Etherdev alloc failed, aborting\n");
2764 return -ENOMEM;
2765 }
2766
2767 netdev->netdev_ops = &e100_netdev_ops;
2768 SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
2769 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2770 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2771
2772 nic = netdev_priv(netdev);
2773 netif_napi_add(netdev, &nic->napi, e100_poll, E100_NAPI_WEIGHT);
2774 nic->netdev = netdev;
2775 nic->pdev = pdev;
2776 nic->msg_enable = (1 << debug) - 1;
2777 nic->mdio_ctrl = mdio_ctrl_hw;
2778 pci_set_drvdata(pdev, netdev);
2779
2780 if ((err = pci_enable_device(pdev))) {
2781 netif_err(nic, probe, nic->netdev, "Cannot enable PCI device, aborting\n");
2782 goto err_out_free_dev;
2783 }
2784
2785 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2786 netif_err(nic, probe, nic->netdev, "Cannot find proper PCI device base address, aborting\n");
2787 err = -ENODEV;
2788 goto err_out_disable_pdev;
2789 }
2790
2791 if ((err = pci_request_regions(pdev, DRV_NAME))) {
2792 netif_err(nic, probe, nic->netdev, "Cannot obtain PCI resources, aborting\n");
2793 goto err_out_disable_pdev;
2794 }
2795
2796 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
2797 netif_err(nic, probe, nic->netdev, "No usable DMA configuration, aborting\n");
2798 goto err_out_free_res;
2799 }
2800
2801 SET_NETDEV_DEV(netdev, &pdev->dev);
2802
2803 if (use_io)
2804 netif_info(nic, probe, nic->netdev, "using i/o access mode\n");
2805
2806 nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr));
2807 if (!nic->csr) {
2808 netif_err(nic, probe, nic->netdev, "Cannot map device registers, aborting\n");
2809 err = -ENOMEM;
2810 goto err_out_free_res;
2811 }
2812
2813 if (ent->driver_data)
2814 nic->flags |= ich;
2815 else
2816 nic->flags &= ~ich;
2817
2818 e100_get_defaults(nic);
2819
2820
2821 spin_lock_init(&nic->cb_lock);
2822 spin_lock_init(&nic->cmd_lock);
2823 spin_lock_init(&nic->mdio_lock);
2824
2825
2826
2827
2828 e100_hw_reset(nic);
2829
2830 pci_set_master(pdev);
2831
2832 init_timer(&nic->watchdog);
2833 nic->watchdog.function = e100_watchdog;
2834 nic->watchdog.data = (unsigned long)nic;
2835 init_timer(&nic->blink_timer);
2836 nic->blink_timer.function = e100_blink_led;
2837 nic->blink_timer.data = (unsigned long)nic;
2838
2839 INIT_WORK(&nic->tx_timeout_task, e100_tx_timeout_task);
2840
2841 if ((err = e100_alloc(nic))) {
2842 netif_err(nic, probe, nic->netdev, "Cannot alloc driver memory, aborting\n");
2843 goto err_out_iounmap;
2844 }
2845
2846 if ((err = e100_eeprom_load(nic)))
2847 goto err_out_free;
2848
2849 e100_phy_init(nic);
2850
2851 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
2852 memcpy(netdev->perm_addr, nic->eeprom, ETH_ALEN);
2853 if (!is_valid_ether_addr(netdev->perm_addr)) {
2854 if (!eeprom_bad_csum_allow) {
2855 netif_err(nic, probe, nic->netdev, "Invalid MAC address from EEPROM, aborting\n");
2856 err = -EAGAIN;
2857 goto err_out_free;
2858 } else {
2859 netif_err(nic, probe, nic->netdev, "Invalid MAC address from EEPROM, you MUST configure one.\n");
2860 }
2861 }
2862
2863
2864 if ((nic->mac >= mac_82558_D101_A4) &&
2865 (nic->eeprom[eeprom_id] & eeprom_id_wol)) {
2866 nic->flags |= wol_magic;
2867 device_set_wakeup_enable(&pdev->dev, true);
2868 }
2869
2870
2871 pci_pme_active(pdev, false);
2872
2873 strcpy(netdev->name, "eth%d");
2874 if ((err = register_netdev(netdev))) {
2875 netif_err(nic, probe, nic->netdev, "Cannot register net device, aborting\n");
2876 goto err_out_free;
2877 }
2878 nic->cbs_pool = pci_pool_create(netdev->name,
2879 nic->pdev,
2880 nic->params.cbs.max * sizeof(struct cb),
2881 sizeof(u32),
2882 0);
2883 netif_info(nic, probe, nic->netdev,
2884 "addr 0x%llx, irq %d, MAC addr %pM\n",
2885 (unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0),
2886 pdev->irq, netdev->dev_addr);
2887
2888 return 0;
2889
2890err_out_free:
2891 e100_free(nic);
2892err_out_iounmap:
2893 pci_iounmap(pdev, nic->csr);
2894err_out_free_res:
2895 pci_release_regions(pdev);
2896err_out_disable_pdev:
2897 pci_disable_device(pdev);
2898err_out_free_dev:
2899 pci_set_drvdata(pdev, NULL);
2900 free_netdev(netdev);
2901 return err;
2902}
2903
2904static void __devexit e100_remove(struct pci_dev *pdev)
2905{
2906 struct net_device *netdev = pci_get_drvdata(pdev);
2907
2908 if (netdev) {
2909 struct nic *nic = netdev_priv(netdev);
2910 unregister_netdev(netdev);
2911 e100_free(nic);
2912 pci_iounmap(pdev, nic->csr);
2913 pci_pool_destroy(nic->cbs_pool);
2914 free_netdev(netdev);
2915 pci_release_regions(pdev);
2916 pci_disable_device(pdev);
2917 pci_set_drvdata(pdev, NULL);
2918 }
2919}
2920
2921#define E100_82552_SMARTSPEED 0x14
2922#define E100_82552_REV_ANEG 0x0200
2923#define E100_82552_ANEG_NOW 0x0400
2924static void __e100_shutdown(struct pci_dev *pdev, bool *enable_wake)
2925{
2926 struct net_device *netdev = pci_get_drvdata(pdev);
2927 struct nic *nic = netdev_priv(netdev);
2928
2929 if (netif_running(netdev))
2930 e100_down(nic);
2931 netif_device_detach(netdev);
2932
2933 pci_save_state(pdev);
2934
2935 if ((nic->flags & wol_magic) | e100_asf(nic)) {
2936
2937 if (nic->phy == phy_82552_v) {
2938 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
2939 E100_82552_SMARTSPEED);
2940
2941 mdio_write(netdev, nic->mii.phy_id,
2942 E100_82552_SMARTSPEED, smartspeed |
2943 E100_82552_REV_ANEG | E100_82552_ANEG_NOW);
2944 }
2945 *enable_wake = true;
2946 } else {
2947 *enable_wake = false;
2948 }
2949
2950 pci_disable_device(pdev);
2951}
2952
2953static int __e100_power_off(struct pci_dev *pdev, bool wake)
2954{
2955 if (wake)
2956 return pci_prepare_to_sleep(pdev);
2957
2958 pci_wake_from_d3(pdev, false);
2959 pci_set_power_state(pdev, PCI_D3hot);
2960
2961 return 0;
2962}
2963
2964#ifdef CONFIG_PM
2965static int e100_suspend(struct pci_dev *pdev, pm_message_t state)
2966{
2967 bool wake;
2968 __e100_shutdown(pdev, &wake);
2969 return __e100_power_off(pdev, wake);
2970}
2971
2972static int e100_resume(struct pci_dev *pdev)
2973{
2974 struct net_device *netdev = pci_get_drvdata(pdev);
2975 struct nic *nic = netdev_priv(netdev);
2976
2977 pci_set_power_state(pdev, PCI_D0);
2978 pci_restore_state(pdev);
2979
2980 pci_enable_wake(pdev, 0, 0);
2981
2982
2983 if (nic->phy == phy_82552_v) {
2984 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
2985 E100_82552_SMARTSPEED);
2986
2987 mdio_write(netdev, nic->mii.phy_id,
2988 E100_82552_SMARTSPEED,
2989 smartspeed & ~(E100_82552_REV_ANEG));
2990 }
2991
2992 netif_device_attach(netdev);
2993 if (netif_running(netdev))
2994 e100_up(nic);
2995
2996 return 0;
2997}
2998#endif
2999
3000static void e100_shutdown(struct pci_dev *pdev)
3001{
3002 bool wake;
3003 __e100_shutdown(pdev, &wake);
3004 if (system_state == SYSTEM_POWER_OFF)
3005 __e100_power_off(pdev, wake);
3006}
3007
3008
3009
3010
3011
3012
3013
3014static pci_ers_result_t e100_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
3015{
3016 struct net_device *netdev = pci_get_drvdata(pdev);
3017 struct nic *nic = netdev_priv(netdev);
3018
3019 netif_device_detach(netdev);
3020
3021 if (state == pci_channel_io_perm_failure)
3022 return PCI_ERS_RESULT_DISCONNECT;
3023
3024 if (netif_running(netdev))
3025 e100_down(nic);
3026 pci_disable_device(pdev);
3027
3028
3029 return PCI_ERS_RESULT_NEED_RESET;
3030}
3031
3032
3033
3034
3035
3036
3037
3038static pci_ers_result_t e100_io_slot_reset(struct pci_dev *pdev)
3039{
3040 struct net_device *netdev = pci_get_drvdata(pdev);
3041 struct nic *nic = netdev_priv(netdev);
3042
3043 if (pci_enable_device(pdev)) {
3044 pr_err("Cannot re-enable PCI device after reset\n");
3045 return PCI_ERS_RESULT_DISCONNECT;
3046 }
3047 pci_set_master(pdev);
3048
3049
3050 if (0 != PCI_FUNC(pdev->devfn))
3051 return PCI_ERS_RESULT_RECOVERED;
3052 e100_hw_reset(nic);
3053 e100_phy_init(nic);
3054
3055 return PCI_ERS_RESULT_RECOVERED;
3056}
3057
3058
3059
3060
3061
3062
3063
3064
3065static void e100_io_resume(struct pci_dev *pdev)
3066{
3067 struct net_device *netdev = pci_get_drvdata(pdev);
3068 struct nic *nic = netdev_priv(netdev);
3069
3070
3071 pci_enable_wake(pdev, 0, 0);
3072
3073 netif_device_attach(netdev);
3074 if (netif_running(netdev)) {
3075 e100_open(netdev);
3076 mod_timer(&nic->watchdog, jiffies);
3077 }
3078}
3079
3080static struct pci_error_handlers e100_err_handler = {
3081 .error_detected = e100_io_error_detected,
3082 .slot_reset = e100_io_slot_reset,
3083 .resume = e100_io_resume,
3084};
3085
3086static struct pci_driver e100_driver = {
3087 .name = DRV_NAME,
3088 .id_table = e100_id_table,
3089 .probe = e100_probe,
3090 .remove = __devexit_p(e100_remove),
3091#ifdef CONFIG_PM
3092
3093 .suspend = e100_suspend,
3094 .resume = e100_resume,
3095#endif
3096 .shutdown = e100_shutdown,
3097 .err_handler = &e100_err_handler,
3098};
3099
3100static int __init e100_init_module(void)
3101{
3102 if (((1 << debug) - 1) & NETIF_MSG_DRV) {
3103 pr_info("%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
3104 pr_info("%s\n", DRV_COPYRIGHT);
3105 }
3106 return pci_register_driver(&e100_driver);
3107}
3108
3109static void __exit e100_cleanup_module(void)
3110{
3111 pci_unregister_driver(&e100_driver);
3112}
3113
3114module_init(e100_init_module);
3115module_exit(e100_cleanup_module);
3116