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28
29#include <linux/delay.h>
30
31#include "e1000.h"
32
33static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
34static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
35static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
36static s32 e1000_wait_autoneg(struct e1000_hw *hw);
37static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
38static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
39 u16 *data, bool read);
40static u32 e1000_get_phy_addr_for_hv_page(u32 page);
41static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
42 u16 *data, bool read);
43
44
45static const u16 e1000_m88_cable_length_table[] = {
46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
47#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
48 ARRAY_SIZE(e1000_m88_cable_length_table)
49
50static const u16 e1000_igp_2_cable_length_table[] = {
51 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
52 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
53 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
54 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
55 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
56 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
57 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
58 124};
59#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
60 ARRAY_SIZE(e1000_igp_2_cable_length_table)
61
62#define BM_PHY_REG_PAGE(offset) \
63 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
64#define BM_PHY_REG_NUM(offset) \
65 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
66 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
67 ~MAX_PHY_REG_ADDRESS)))
68
69#define HV_INTC_FC_PAGE_START 768
70#define I82578_ADDR_REG 29
71#define I82577_ADDR_REG 16
72#define I82577_CFG_REG 22
73#define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
74#define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10)
75#define I82577_CTRL_REG 23
76
77
78#define I82577_PHY_CTRL_2 18
79#define I82577_PHY_STATUS_2 26
80#define I82577_PHY_DIAG_STATUS 31
81
82
83#define I82577_PHY_STATUS2_REV_POLARITY 0x0400
84#define I82577_PHY_STATUS2_MDIX 0x0800
85#define I82577_PHY_STATUS2_SPEED_MASK 0x0300
86#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
87
88
89#define I82577_PHY_CTRL2_AUTO_MDIX 0x0400
90#define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200
91
92
93#define I82577_DSTATUS_CABLE_LENGTH 0x03FC
94#define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
95
96
97#define BM_CS_CTRL1 16
98
99#define HV_MUX_DATA_CTRL PHY_REG(776, 16)
100#define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
101#define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
102
103
104
105
106
107
108
109
110
111s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
112{
113 u32 manc;
114
115 manc = er32(MANC);
116
117 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
118 E1000_BLK_PHY_RESET : 0;
119}
120
121
122
123
124
125
126
127
128s32 e1000e_get_phy_id(struct e1000_hw *hw)
129{
130 struct e1000_phy_info *phy = &hw->phy;
131 s32 ret_val = 0;
132 u16 phy_id;
133 u16 retry_count = 0;
134
135 if (!(phy->ops.read_reg))
136 goto out;
137
138 while (retry_count < 2) {
139 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
140 if (ret_val)
141 goto out;
142
143 phy->id = (u32)(phy_id << 16);
144 udelay(20);
145 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
146 if (ret_val)
147 goto out;
148
149 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
150 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
151
152 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
153 goto out;
154
155 retry_count++;
156 }
157out:
158 return ret_val;
159}
160
161
162
163
164
165
166
167s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
168{
169 s32 ret_val;
170
171 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
172 if (ret_val)
173 return ret_val;
174
175 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
176}
177
178
179
180
181
182
183
184
185
186
187s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
188{
189 struct e1000_phy_info *phy = &hw->phy;
190 u32 i, mdic = 0;
191
192 if (offset > MAX_PHY_REG_ADDRESS) {
193 e_dbg("PHY Address %d is out of range\n", offset);
194 return -E1000_ERR_PARAM;
195 }
196
197
198
199
200
201
202 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
203 (phy->addr << E1000_MDIC_PHY_SHIFT) |
204 (E1000_MDIC_OP_READ));
205
206 ew32(MDIC, mdic);
207
208
209
210
211
212
213 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
214 udelay(50);
215 mdic = er32(MDIC);
216 if (mdic & E1000_MDIC_READY)
217 break;
218 }
219 if (!(mdic & E1000_MDIC_READY)) {
220 e_dbg("MDI Read did not complete\n");
221 return -E1000_ERR_PHY;
222 }
223 if (mdic & E1000_MDIC_ERROR) {
224 e_dbg("MDI Error\n");
225 return -E1000_ERR_PHY;
226 }
227 *data = (u16) mdic;
228
229
230
231
232
233 if (hw->mac.type == e1000_pch2lan)
234 udelay(100);
235
236 return 0;
237}
238
239
240
241
242
243
244
245
246
247s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
248{
249 struct e1000_phy_info *phy = &hw->phy;
250 u32 i, mdic = 0;
251
252 if (offset > MAX_PHY_REG_ADDRESS) {
253 e_dbg("PHY Address %d is out of range\n", offset);
254 return -E1000_ERR_PARAM;
255 }
256
257
258
259
260
261
262 mdic = (((u32)data) |
263 (offset << E1000_MDIC_REG_SHIFT) |
264 (phy->addr << E1000_MDIC_PHY_SHIFT) |
265 (E1000_MDIC_OP_WRITE));
266
267 ew32(MDIC, mdic);
268
269
270
271
272
273
274 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
275 udelay(50);
276 mdic = er32(MDIC);
277 if (mdic & E1000_MDIC_READY)
278 break;
279 }
280 if (!(mdic & E1000_MDIC_READY)) {
281 e_dbg("MDI Write did not complete\n");
282 return -E1000_ERR_PHY;
283 }
284 if (mdic & E1000_MDIC_ERROR) {
285 e_dbg("MDI Error\n");
286 return -E1000_ERR_PHY;
287 }
288
289
290
291
292
293 if (hw->mac.type == e1000_pch2lan)
294 udelay(100);
295
296 return 0;
297}
298
299
300
301
302
303
304
305
306
307
308
309s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
310{
311 s32 ret_val;
312
313 ret_val = hw->phy.ops.acquire(hw);
314 if (ret_val)
315 return ret_val;
316
317 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
318 data);
319
320 hw->phy.ops.release(hw);
321
322 return ret_val;
323}
324
325
326
327
328
329
330
331
332
333
334s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
335{
336 s32 ret_val;
337
338 ret_val = hw->phy.ops.acquire(hw);
339 if (ret_val)
340 return ret_val;
341
342 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
343 data);
344
345 hw->phy.ops.release(hw);
346
347 return ret_val;
348}
349
350
351
352
353
354
355
356
357
358
359
360
361static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
362 bool locked)
363{
364 s32 ret_val = 0;
365
366 if (!locked) {
367 if (!(hw->phy.ops.acquire))
368 goto out;
369
370 ret_val = hw->phy.ops.acquire(hw);
371 if (ret_val)
372 goto out;
373 }
374
375 if (offset > MAX_PHY_MULTI_PAGE_REG) {
376 ret_val = e1000e_write_phy_reg_mdic(hw,
377 IGP01E1000_PHY_PAGE_SELECT,
378 (u16)offset);
379 if (ret_val)
380 goto release;
381 }
382
383 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
384 data);
385
386release:
387 if (!locked)
388 hw->phy.ops.release(hw);
389out:
390 return ret_val;
391}
392
393
394
395
396
397
398
399
400
401
402
403s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
404{
405 return __e1000e_read_phy_reg_igp(hw, offset, data, false);
406}
407
408
409
410
411
412
413
414
415
416
417s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
418{
419 return __e1000e_read_phy_reg_igp(hw, offset, data, true);
420}
421
422
423
424
425
426
427
428
429
430
431
432static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
433 bool locked)
434{
435 s32 ret_val = 0;
436
437 if (!locked) {
438 if (!(hw->phy.ops.acquire))
439 goto out;
440
441 ret_val = hw->phy.ops.acquire(hw);
442 if (ret_val)
443 goto out;
444 }
445
446 if (offset > MAX_PHY_MULTI_PAGE_REG) {
447 ret_val = e1000e_write_phy_reg_mdic(hw,
448 IGP01E1000_PHY_PAGE_SELECT,
449 (u16)offset);
450 if (ret_val)
451 goto release;
452 }
453
454 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
455 data);
456
457release:
458 if (!locked)
459 hw->phy.ops.release(hw);
460
461out:
462 return ret_val;
463}
464
465
466
467
468
469
470
471
472
473
474s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
475{
476 return __e1000e_write_phy_reg_igp(hw, offset, data, false);
477}
478
479
480
481
482
483
484
485
486
487
488s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
489{
490 return __e1000e_write_phy_reg_igp(hw, offset, data, true);
491}
492
493
494
495
496
497
498
499
500
501
502
503
504static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
505 bool locked)
506{
507 u32 kmrnctrlsta;
508 s32 ret_val = 0;
509
510 if (!locked) {
511 if (!(hw->phy.ops.acquire))
512 goto out;
513
514 ret_val = hw->phy.ops.acquire(hw);
515 if (ret_val)
516 goto out;
517 }
518
519 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
520 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
521 ew32(KMRNCTRLSTA, kmrnctrlsta);
522
523 udelay(2);
524
525 kmrnctrlsta = er32(KMRNCTRLSTA);
526 *data = (u16)kmrnctrlsta;
527
528 if (!locked)
529 hw->phy.ops.release(hw);
530
531out:
532 return ret_val;
533}
534
535
536
537
538
539
540
541
542
543
544
545s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
546{
547 return __e1000_read_kmrn_reg(hw, offset, data, false);
548}
549
550
551
552
553
554
555
556
557
558
559
560s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
561{
562 return __e1000_read_kmrn_reg(hw, offset, data, true);
563}
564
565
566
567
568
569
570
571
572
573
574
575
576static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
577 bool locked)
578{
579 u32 kmrnctrlsta;
580 s32 ret_val = 0;
581
582 if (!locked) {
583 if (!(hw->phy.ops.acquire))
584 goto out;
585
586 ret_val = hw->phy.ops.acquire(hw);
587 if (ret_val)
588 goto out;
589 }
590
591 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
592 E1000_KMRNCTRLSTA_OFFSET) | data;
593 ew32(KMRNCTRLSTA, kmrnctrlsta);
594
595 udelay(2);
596
597 if (!locked)
598 hw->phy.ops.release(hw);
599
600out:
601 return ret_val;
602}
603
604
605
606
607
608
609
610
611
612
613s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
614{
615 return __e1000_write_kmrn_reg(hw, offset, data, false);
616}
617
618
619
620
621
622
623
624
625
626
627s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
628{
629 return __e1000_write_kmrn_reg(hw, offset, data, true);
630}
631
632
633
634
635
636
637
638s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
639{
640 s32 ret_val;
641 u16 phy_data;
642
643
644 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
645 if (ret_val)
646 goto out;
647
648 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
649
650
651 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
652
653 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
654
655out:
656 return ret_val;
657}
658
659
660
661
662
663
664
665
666s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
667{
668 struct e1000_phy_info *phy = &hw->phy;
669 s32 ret_val;
670 u16 phy_data;
671
672
673 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
674 if (ret_val)
675 return ret_val;
676
677
678 if (phy->type != e1000_phy_bm)
679 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
680
681
682
683
684
685
686
687
688
689 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
690
691 switch (phy->mdix) {
692 case 1:
693 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
694 break;
695 case 2:
696 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
697 break;
698 case 3:
699 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
700 break;
701 case 0:
702 default:
703 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
704 break;
705 }
706
707
708
709
710
711
712
713
714 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
715 if (phy->disable_polarity_correction == 1)
716 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
717
718
719 if (phy->type == e1000_phy_bm)
720 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
721
722 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
723 if (ret_val)
724 return ret_val;
725
726 if ((phy->type == e1000_phy_m88) &&
727 (phy->revision < E1000_REVISION_4) &&
728 (phy->id != BME1000_E_PHY_ID_R2)) {
729
730
731
732
733 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
734 if (ret_val)
735 return ret_val;
736
737 phy_data |= M88E1000_EPSCR_TX_CLK_25;
738
739 if ((phy->revision == 2) &&
740 (phy->id == M88E1111_I_PHY_ID)) {
741
742 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
743 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
744 } else {
745
746 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
747 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
748 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
749 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
750 }
751 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
752 if (ret_val)
753 return ret_val;
754 }
755
756 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
757
758 ret_val = e1e_wphy(hw, 29, 0x0003);
759 if (ret_val)
760 return ret_val;
761
762
763 ret_val = e1e_wphy(hw, 30, 0x0000);
764 if (ret_val)
765 return ret_val;
766 }
767
768
769 ret_val = e1000e_commit_phy(hw);
770 if (ret_val) {
771 e_dbg("Error committing the PHY changes\n");
772 return ret_val;
773 }
774
775 if (phy->type == e1000_phy_82578) {
776 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
777 if (ret_val)
778 return ret_val;
779
780
781 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
782 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
783 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
784 if (ret_val)
785 return ret_val;
786 }
787
788 return 0;
789}
790
791
792
793
794
795
796
797
798s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
799{
800 struct e1000_phy_info *phy = &hw->phy;
801 s32 ret_val;
802 u16 data;
803
804 ret_val = e1000_phy_hw_reset(hw);
805 if (ret_val) {
806 e_dbg("Error resetting the PHY.\n");
807 return ret_val;
808 }
809
810
811
812
813
814 msleep(100);
815
816
817 ret_val = e1000_set_d0_lplu_state(hw, false);
818 if (ret_val) {
819 e_dbg("Error Disabling LPLU D0\n");
820 return ret_val;
821 }
822
823 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
824 if (ret_val)
825 return ret_val;
826
827 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
828
829 switch (phy->mdix) {
830 case 1:
831 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
832 break;
833 case 2:
834 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
835 break;
836 case 0:
837 default:
838 data |= IGP01E1000_PSCR_AUTO_MDIX;
839 break;
840 }
841 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
842 if (ret_val)
843 return ret_val;
844
845
846 if (hw->mac.autoneg) {
847
848
849
850
851
852 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
853
854 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
855 &data);
856 if (ret_val)
857 return ret_val;
858
859 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
860 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
861 data);
862 if (ret_val)
863 return ret_val;
864
865
866 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
867 if (ret_val)
868 return ret_val;
869
870 data &= ~CR_1000T_MS_ENABLE;
871 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
872 if (ret_val)
873 return ret_val;
874 }
875
876 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
877 if (ret_val)
878 return ret_val;
879
880
881 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
882 ((data & CR_1000T_MS_VALUE) ?
883 e1000_ms_force_master :
884 e1000_ms_force_slave) :
885 e1000_ms_auto;
886
887 switch (phy->ms_type) {
888 case e1000_ms_force_master:
889 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
890 break;
891 case e1000_ms_force_slave:
892 data |= CR_1000T_MS_ENABLE;
893 data &= ~(CR_1000T_MS_VALUE);
894 break;
895 case e1000_ms_auto:
896 data &= ~CR_1000T_MS_ENABLE;
897 default:
898 break;
899 }
900 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
901 }
902
903 return ret_val;
904}
905
906
907
908
909
910
911
912
913
914
915static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
916{
917 struct e1000_phy_info *phy = &hw->phy;
918 s32 ret_val;
919 u16 mii_autoneg_adv_reg;
920 u16 mii_1000t_ctrl_reg = 0;
921
922 phy->autoneg_advertised &= phy->autoneg_mask;
923
924
925 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
926 if (ret_val)
927 return ret_val;
928
929 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
930
931 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
932 if (ret_val)
933 return ret_val;
934 }
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
950 NWAY_AR_100TX_HD_CAPS |
951 NWAY_AR_10T_FD_CAPS |
952 NWAY_AR_10T_HD_CAPS);
953 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
954
955 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
956
957
958 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
959 e_dbg("Advertise 10mb Half duplex\n");
960 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
961 }
962
963
964 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
965 e_dbg("Advertise 10mb Full duplex\n");
966 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
967 }
968
969
970 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
971 e_dbg("Advertise 100mb Half duplex\n");
972 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
973 }
974
975
976 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
977 e_dbg("Advertise 100mb Full duplex\n");
978 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
979 }
980
981
982 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
983 e_dbg("Advertise 1000mb Half duplex request denied!\n");
984
985
986 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
987 e_dbg("Advertise 1000mb Full duplex\n");
988 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
989 }
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009 switch (hw->fc.current_mode) {
1010 case e1000_fc_none:
1011
1012
1013
1014
1015 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1016 break;
1017 case e1000_fc_rx_pause:
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1029 break;
1030 case e1000_fc_tx_pause:
1031
1032
1033
1034
1035 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1036 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1037 break;
1038 case e1000_fc_full:
1039
1040
1041
1042
1043 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1044 break;
1045 default:
1046 e_dbg("Flow control param set incorrectly\n");
1047 ret_val = -E1000_ERR_CONFIG;
1048 return ret_val;
1049 }
1050
1051 ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1052 if (ret_val)
1053 return ret_val;
1054
1055 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1056
1057 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1058 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1059
1060 return ret_val;
1061}
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1073{
1074 struct e1000_phy_info *phy = &hw->phy;
1075 s32 ret_val;
1076 u16 phy_ctrl;
1077
1078
1079
1080
1081
1082 phy->autoneg_advertised &= phy->autoneg_mask;
1083
1084
1085
1086
1087
1088 if (phy->autoneg_advertised == 0)
1089 phy->autoneg_advertised = phy->autoneg_mask;
1090
1091 e_dbg("Reconfiguring auto-neg advertisement params\n");
1092 ret_val = e1000_phy_setup_autoneg(hw);
1093 if (ret_val) {
1094 e_dbg("Error Setting up Auto-Negotiation\n");
1095 return ret_val;
1096 }
1097 e_dbg("Restarting Auto-Neg\n");
1098
1099
1100
1101
1102
1103 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
1104 if (ret_val)
1105 return ret_val;
1106
1107 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1108 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
1109 if (ret_val)
1110 return ret_val;
1111
1112
1113
1114
1115
1116 if (phy->autoneg_wait_to_complete) {
1117 ret_val = e1000_wait_autoneg(hw);
1118 if (ret_val) {
1119 e_dbg("Error while waiting for "
1120 "autoneg to complete\n");
1121 return ret_val;
1122 }
1123 }
1124
1125 hw->mac.get_link_status = 1;
1126
1127 return ret_val;
1128}
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1140{
1141 s32 ret_val;
1142 bool link;
1143
1144 if (hw->mac.autoneg) {
1145
1146
1147
1148
1149 ret_val = e1000_copper_link_autoneg(hw);
1150 if (ret_val)
1151 return ret_val;
1152 } else {
1153
1154
1155
1156
1157 e_dbg("Forcing Speed and Duplex\n");
1158 ret_val = e1000_phy_force_speed_duplex(hw);
1159 if (ret_val) {
1160 e_dbg("Error Forcing Speed and Duplex\n");
1161 return ret_val;
1162 }
1163 }
1164
1165
1166
1167
1168
1169 ret_val = e1000e_phy_has_link_generic(hw,
1170 COPPER_LINK_UP_LIMIT,
1171 10,
1172 &link);
1173 if (ret_val)
1174 return ret_val;
1175
1176 if (link) {
1177 e_dbg("Valid link established!!!\n");
1178 e1000e_config_collision_dist(hw);
1179 ret_val = e1000e_config_fc_after_link_up(hw);
1180 } else {
1181 e_dbg("Unable to establish link!!!\n");
1182 }
1183
1184 return ret_val;
1185}
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1196{
1197 struct e1000_phy_info *phy = &hw->phy;
1198 s32 ret_val;
1199 u16 phy_data;
1200 bool link;
1201
1202 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1203 if (ret_val)
1204 return ret_val;
1205
1206 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1207
1208 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1209 if (ret_val)
1210 return ret_val;
1211
1212
1213
1214
1215
1216 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1217 if (ret_val)
1218 return ret_val;
1219
1220 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1221 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1222
1223 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1224 if (ret_val)
1225 return ret_val;
1226
1227 e_dbg("IGP PSCR: %X\n", phy_data);
1228
1229 udelay(1);
1230
1231 if (phy->autoneg_wait_to_complete) {
1232 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1233
1234 ret_val = e1000e_phy_has_link_generic(hw,
1235 PHY_FORCE_LIMIT,
1236 100000,
1237 &link);
1238 if (ret_val)
1239 return ret_val;
1240
1241 if (!link)
1242 e_dbg("Link taking longer than expected.\n");
1243
1244
1245 ret_val = e1000e_phy_has_link_generic(hw,
1246 PHY_FORCE_LIMIT,
1247 100000,
1248 &link);
1249 if (ret_val)
1250 return ret_val;
1251 }
1252
1253 return ret_val;
1254}
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1267{
1268 struct e1000_phy_info *phy = &hw->phy;
1269 s32 ret_val;
1270 u16 phy_data;
1271 bool link;
1272
1273
1274
1275
1276
1277 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1278 if (ret_val)
1279 return ret_val;
1280
1281 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1282 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1283 if (ret_val)
1284 return ret_val;
1285
1286 e_dbg("M88E1000 PSCR: %X\n", phy_data);
1287
1288 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1289 if (ret_val)
1290 return ret_val;
1291
1292 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1293
1294 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1295 if (ret_val)
1296 return ret_val;
1297
1298
1299 ret_val = e1000e_commit_phy(hw);
1300 if (ret_val)
1301 return ret_val;
1302
1303 if (phy->autoneg_wait_to_complete) {
1304 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1305
1306 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1307 100000, &link);
1308 if (ret_val)
1309 return ret_val;
1310
1311 if (!link) {
1312 if (hw->phy.type != e1000_phy_m88) {
1313 e_dbg("Link taking longer than expected.\n");
1314 } else {
1315
1316
1317
1318
1319 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1320 0x001d);
1321 if (ret_val)
1322 return ret_val;
1323 ret_val = e1000e_phy_reset_dsp(hw);
1324 if (ret_val)
1325 return ret_val;
1326 }
1327 }
1328
1329
1330 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1331 100000, &link);
1332 if (ret_val)
1333 return ret_val;
1334 }
1335
1336 if (hw->phy.type != e1000_phy_m88)
1337 return 0;
1338
1339 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1340 if (ret_val)
1341 return ret_val;
1342
1343
1344
1345
1346
1347
1348 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1349 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1350 if (ret_val)
1351 return ret_val;
1352
1353
1354
1355
1356
1357 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1358 if (ret_val)
1359 return ret_val;
1360
1361 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1362 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1363
1364 return ret_val;
1365}
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1376{
1377 struct e1000_phy_info *phy = &hw->phy;
1378 s32 ret_val;
1379 u16 data;
1380 bool link;
1381
1382 ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
1383 if (ret_val)
1384 goto out;
1385
1386 e1000e_phy_force_speed_duplex_setup(hw, &data);
1387
1388 ret_val = e1e_wphy(hw, PHY_CONTROL, data);
1389 if (ret_val)
1390 goto out;
1391
1392
1393 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1394 if (ret_val)
1395 goto out;
1396
1397 data &= ~IFE_PMC_AUTO_MDIX;
1398 data &= ~IFE_PMC_FORCE_MDIX;
1399
1400 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1401 if (ret_val)
1402 goto out;
1403
1404 e_dbg("IFE PMC: %X\n", data);
1405
1406 udelay(1);
1407
1408 if (phy->autoneg_wait_to_complete) {
1409 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1410
1411 ret_val = e1000e_phy_has_link_generic(hw,
1412 PHY_FORCE_LIMIT,
1413 100000,
1414 &link);
1415 if (ret_val)
1416 goto out;
1417
1418 if (!link)
1419 e_dbg("Link taking longer than expected.\n");
1420
1421
1422 ret_val = e1000e_phy_has_link_generic(hw,
1423 PHY_FORCE_LIMIT,
1424 100000,
1425 &link);
1426 if (ret_val)
1427 goto out;
1428 }
1429
1430out:
1431 return ret_val;
1432}
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1447{
1448 struct e1000_mac_info *mac = &hw->mac;
1449 u32 ctrl;
1450
1451
1452 hw->fc.current_mode = e1000_fc_none;
1453
1454
1455 ctrl = er32(CTRL);
1456 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1457 ctrl &= ~E1000_CTRL_SPD_SEL;
1458
1459
1460 ctrl &= ~E1000_CTRL_ASDE;
1461
1462
1463 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1464
1465
1466 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1467 ctrl &= ~E1000_CTRL_FD;
1468 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1469 e_dbg("Half Duplex\n");
1470 } else {
1471 ctrl |= E1000_CTRL_FD;
1472 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1473 e_dbg("Full Duplex\n");
1474 }
1475
1476
1477 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1478 ctrl |= E1000_CTRL_SPD_100;
1479 *phy_ctrl |= MII_CR_SPEED_100;
1480 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1481 e_dbg("Forcing 100mb\n");
1482 } else {
1483 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1484 *phy_ctrl |= MII_CR_SPEED_10;
1485 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1486 e_dbg("Forcing 10mb\n");
1487 }
1488
1489 e1000e_config_collision_dist(hw);
1490
1491 ew32(CTRL, ctrl);
1492}
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1509{
1510 struct e1000_phy_info *phy = &hw->phy;
1511 s32 ret_val;
1512 u16 data;
1513
1514 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1515 if (ret_val)
1516 return ret_val;
1517
1518 if (!active) {
1519 data &= ~IGP02E1000_PM_D3_LPLU;
1520 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1521 if (ret_val)
1522 return ret_val;
1523
1524
1525
1526
1527
1528
1529 if (phy->smart_speed == e1000_smart_speed_on) {
1530 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1531 &data);
1532 if (ret_val)
1533 return ret_val;
1534
1535 data |= IGP01E1000_PSCFR_SMART_SPEED;
1536 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1537 data);
1538 if (ret_val)
1539 return ret_val;
1540 } else if (phy->smart_speed == e1000_smart_speed_off) {
1541 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1542 &data);
1543 if (ret_val)
1544 return ret_val;
1545
1546 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1547 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1548 data);
1549 if (ret_val)
1550 return ret_val;
1551 }
1552 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1553 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1554 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1555 data |= IGP02E1000_PM_D3_LPLU;
1556 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1557 if (ret_val)
1558 return ret_val;
1559
1560
1561 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1562 if (ret_val)
1563 return ret_val;
1564
1565 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1566 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1567 }
1568
1569 return ret_val;
1570}
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580s32 e1000e_check_downshift(struct e1000_hw *hw)
1581{
1582 struct e1000_phy_info *phy = &hw->phy;
1583 s32 ret_val;
1584 u16 phy_data, offset, mask;
1585
1586 switch (phy->type) {
1587 case e1000_phy_m88:
1588 case e1000_phy_gg82563:
1589 case e1000_phy_bm:
1590 case e1000_phy_82578:
1591 offset = M88E1000_PHY_SPEC_STATUS;
1592 mask = M88E1000_PSSR_DOWNSHIFT;
1593 break;
1594 case e1000_phy_igp_2:
1595 case e1000_phy_igp_3:
1596 offset = IGP01E1000_PHY_LINK_HEALTH;
1597 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1598 break;
1599 default:
1600
1601 phy->speed_downgraded = false;
1602 return 0;
1603 }
1604
1605 ret_val = e1e_rphy(hw, offset, &phy_data);
1606
1607 if (!ret_val)
1608 phy->speed_downgraded = (phy_data & mask);
1609
1610 return ret_val;
1611}
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1622{
1623 struct e1000_phy_info *phy = &hw->phy;
1624 s32 ret_val;
1625 u16 data;
1626
1627 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1628
1629 if (!ret_val)
1630 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1631 ? e1000_rev_polarity_reversed
1632 : e1000_rev_polarity_normal;
1633
1634 return ret_val;
1635}
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1647{
1648 struct e1000_phy_info *phy = &hw->phy;
1649 s32 ret_val;
1650 u16 data, offset, mask;
1651
1652
1653
1654
1655
1656 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1657 if (ret_val)
1658 return ret_val;
1659
1660 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1661 IGP01E1000_PSSR_SPEED_1000MBPS) {
1662 offset = IGP01E1000_PHY_PCS_INIT_REG;
1663 mask = IGP01E1000_PHY_POLARITY_MASK;
1664 } else {
1665
1666
1667
1668
1669 offset = IGP01E1000_PHY_PORT_STATUS;
1670 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1671 }
1672
1673 ret_val = e1e_rphy(hw, offset, &data);
1674
1675 if (!ret_val)
1676 phy->cable_polarity = (data & mask)
1677 ? e1000_rev_polarity_reversed
1678 : e1000_rev_polarity_normal;
1679
1680 return ret_val;
1681}
1682
1683
1684
1685
1686
1687
1688
1689s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1690{
1691 struct e1000_phy_info *phy = &hw->phy;
1692 s32 ret_val;
1693 u16 phy_data, offset, mask;
1694
1695
1696
1697
1698 if (phy->polarity_correction) {
1699 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1700 mask = IFE_PESC_POLARITY_REVERSED;
1701 } else {
1702 offset = IFE_PHY_SPECIAL_CONTROL;
1703 mask = IFE_PSC_FORCE_POLARITY;
1704 }
1705
1706 ret_val = e1e_rphy(hw, offset, &phy_data);
1707
1708 if (!ret_val)
1709 phy->cable_polarity = (phy_data & mask)
1710 ? e1000_rev_polarity_reversed
1711 : e1000_rev_polarity_normal;
1712
1713 return ret_val;
1714}
1715
1716
1717
1718
1719
1720
1721
1722
1723static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1724{
1725 s32 ret_val = 0;
1726 u16 i, phy_status;
1727
1728
1729 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1730 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1731 if (ret_val)
1732 break;
1733 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1734 if (ret_val)
1735 break;
1736 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1737 break;
1738 msleep(100);
1739 }
1740
1741
1742
1743
1744
1745 return ret_val;
1746}
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1758 u32 usec_interval, bool *success)
1759{
1760 s32 ret_val = 0;
1761 u16 i, phy_status;
1762
1763 for (i = 0; i < iterations; i++) {
1764
1765
1766
1767
1768
1769 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1770 if (ret_val)
1771
1772
1773
1774
1775
1776 udelay(usec_interval);
1777 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1778 if (ret_val)
1779 break;
1780 if (phy_status & MII_SR_LINK_STATUS)
1781 break;
1782 if (usec_interval >= 1000)
1783 mdelay(usec_interval/1000);
1784 else
1785 udelay(usec_interval);
1786 }
1787
1788 *success = (i < iterations);
1789
1790 return ret_val;
1791}
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1809{
1810 struct e1000_phy_info *phy = &hw->phy;
1811 s32 ret_val;
1812 u16 phy_data, index;
1813
1814 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1815 if (ret_val)
1816 goto out;
1817
1818 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1819 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1820 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
1821 ret_val = -E1000_ERR_PHY;
1822 goto out;
1823 }
1824
1825 phy->min_cable_length = e1000_m88_cable_length_table[index];
1826 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1827
1828 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1829
1830out:
1831 return ret_val;
1832}
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1846{
1847 struct e1000_phy_info *phy = &hw->phy;
1848 s32 ret_val;
1849 u16 phy_data, i, agc_value = 0;
1850 u16 cur_agc_index, max_agc_index = 0;
1851 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1852 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1853 IGP02E1000_PHY_AGC_A,
1854 IGP02E1000_PHY_AGC_B,
1855 IGP02E1000_PHY_AGC_C,
1856 IGP02E1000_PHY_AGC_D
1857 };
1858
1859
1860 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1861 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1862 if (ret_val)
1863 return ret_val;
1864
1865
1866
1867
1868
1869
1870
1871 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1872 IGP02E1000_AGC_LENGTH_MASK;
1873
1874
1875 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1876 (cur_agc_index == 0))
1877 return -E1000_ERR_PHY;
1878
1879
1880 if (e1000_igp_2_cable_length_table[min_agc_index] >
1881 e1000_igp_2_cable_length_table[cur_agc_index])
1882 min_agc_index = cur_agc_index;
1883 if (e1000_igp_2_cable_length_table[max_agc_index] <
1884 e1000_igp_2_cable_length_table[cur_agc_index])
1885 max_agc_index = cur_agc_index;
1886
1887 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1888 }
1889
1890 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1891 e1000_igp_2_cable_length_table[max_agc_index]);
1892 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1893
1894
1895 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1896 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1897 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1898
1899 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1900
1901 return ret_val;
1902}
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1915{
1916 struct e1000_phy_info *phy = &hw->phy;
1917 s32 ret_val;
1918 u16 phy_data;
1919 bool link;
1920
1921 if (phy->media_type != e1000_media_type_copper) {
1922 e_dbg("Phy info is only valid for copper media\n");
1923 return -E1000_ERR_CONFIG;
1924 }
1925
1926 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1927 if (ret_val)
1928 return ret_val;
1929
1930 if (!link) {
1931 e_dbg("Phy info is only valid if link is up\n");
1932 return -E1000_ERR_CONFIG;
1933 }
1934
1935 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1936 if (ret_val)
1937 return ret_val;
1938
1939 phy->polarity_correction = (phy_data &
1940 M88E1000_PSCR_POLARITY_REVERSAL);
1941
1942 ret_val = e1000_check_polarity_m88(hw);
1943 if (ret_val)
1944 return ret_val;
1945
1946 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1947 if (ret_val)
1948 return ret_val;
1949
1950 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX);
1951
1952 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1953 ret_val = e1000_get_cable_length(hw);
1954 if (ret_val)
1955 return ret_val;
1956
1957 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
1958 if (ret_val)
1959 return ret_val;
1960
1961 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1962 ? e1000_1000t_rx_status_ok
1963 : e1000_1000t_rx_status_not_ok;
1964
1965 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1966 ? e1000_1000t_rx_status_ok
1967 : e1000_1000t_rx_status_not_ok;
1968 } else {
1969
1970 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1971 phy->local_rx = e1000_1000t_rx_status_undefined;
1972 phy->remote_rx = e1000_1000t_rx_status_undefined;
1973 }
1974
1975 return ret_val;
1976}
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1988{
1989 struct e1000_phy_info *phy = &hw->phy;
1990 s32 ret_val;
1991 u16 data;
1992 bool link;
1993
1994 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1995 if (ret_val)
1996 return ret_val;
1997
1998 if (!link) {
1999 e_dbg("Phy info is only valid if link is up\n");
2000 return -E1000_ERR_CONFIG;
2001 }
2002
2003 phy->polarity_correction = true;
2004
2005 ret_val = e1000_check_polarity_igp(hw);
2006 if (ret_val)
2007 return ret_val;
2008
2009 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2010 if (ret_val)
2011 return ret_val;
2012
2013 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX);
2014
2015 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2016 IGP01E1000_PSSR_SPEED_1000MBPS) {
2017 ret_val = e1000_get_cable_length(hw);
2018 if (ret_val)
2019 return ret_val;
2020
2021 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
2022 if (ret_val)
2023 return ret_val;
2024
2025 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2026 ? e1000_1000t_rx_status_ok
2027 : e1000_1000t_rx_status_not_ok;
2028
2029 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2030 ? e1000_1000t_rx_status_ok
2031 : e1000_1000t_rx_status_not_ok;
2032 } else {
2033 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2034 phy->local_rx = e1000_1000t_rx_status_undefined;
2035 phy->remote_rx = e1000_1000t_rx_status_undefined;
2036 }
2037
2038 return ret_val;
2039}
2040
2041
2042
2043
2044
2045
2046
2047s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2048{
2049 struct e1000_phy_info *phy = &hw->phy;
2050 s32 ret_val;
2051 u16 data;
2052 bool link;
2053
2054 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2055 if (ret_val)
2056 goto out;
2057
2058 if (!link) {
2059 e_dbg("Phy info is only valid if link is up\n");
2060 ret_val = -E1000_ERR_CONFIG;
2061 goto out;
2062 }
2063
2064 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2065 if (ret_val)
2066 goto out;
2067 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
2068 ? false : true;
2069
2070 if (phy->polarity_correction) {
2071 ret_val = e1000_check_polarity_ife(hw);
2072 if (ret_val)
2073 goto out;
2074 } else {
2075
2076 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2077 ? e1000_rev_polarity_reversed
2078 : e1000_rev_polarity_normal;
2079 }
2080
2081 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2082 if (ret_val)
2083 goto out;
2084
2085 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? true : false;
2086
2087
2088 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2089 phy->local_rx = e1000_1000t_rx_status_undefined;
2090 phy->remote_rx = e1000_1000t_rx_status_undefined;
2091
2092out:
2093 return ret_val;
2094}
2095
2096
2097
2098
2099
2100
2101
2102
2103s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2104{
2105 s32 ret_val;
2106 u16 phy_ctrl;
2107
2108 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
2109 if (ret_val)
2110 return ret_val;
2111
2112 phy_ctrl |= MII_CR_RESET;
2113 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
2114 if (ret_val)
2115 return ret_val;
2116
2117 udelay(1);
2118
2119 return ret_val;
2120}
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2132{
2133 struct e1000_phy_info *phy = &hw->phy;
2134 s32 ret_val;
2135 u32 ctrl;
2136
2137 ret_val = e1000_check_reset_block(hw);
2138 if (ret_val)
2139 return 0;
2140
2141 ret_val = phy->ops.acquire(hw);
2142 if (ret_val)
2143 return ret_val;
2144
2145 ctrl = er32(CTRL);
2146 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2147 e1e_flush();
2148
2149 udelay(phy->reset_delay_us);
2150
2151 ew32(CTRL, ctrl);
2152 e1e_flush();
2153
2154 udelay(150);
2155
2156 phy->ops.release(hw);
2157
2158 return e1000_get_phy_cfg_done(hw);
2159}
2160
2161
2162
2163
2164
2165
2166
2167
2168s32 e1000e_get_cfg_done(struct e1000_hw *hw)
2169{
2170 mdelay(10);
2171 return 0;
2172}
2173
2174
2175
2176
2177
2178
2179
2180s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2181{
2182 e_dbg("Running IGP 3 PHY init script\n");
2183
2184
2185
2186 e1e_wphy(hw, 0x2F5B, 0x9018);
2187
2188 e1e_wphy(hw, 0x2F52, 0x0000);
2189
2190 e1e_wphy(hw, 0x2FB1, 0x8B24);
2191
2192 e1e_wphy(hw, 0x2FB2, 0xF8F0);
2193
2194 e1e_wphy(hw, 0x2010, 0x10B0);
2195
2196 e1e_wphy(hw, 0x2011, 0x0000);
2197
2198 e1e_wphy(hw, 0x20DD, 0x249A);
2199
2200 e1e_wphy(hw, 0x20DE, 0x00D3);
2201
2202 e1e_wphy(hw, 0x28B4, 0x04CE);
2203
2204 e1e_wphy(hw, 0x2F70, 0x29E4);
2205
2206 e1e_wphy(hw, 0x0000, 0x0140);
2207
2208 e1e_wphy(hw, 0x1F30, 0x1606);
2209
2210 e1e_wphy(hw, 0x1F31, 0xB814);
2211
2212 e1e_wphy(hw, 0x1F35, 0x002A);
2213
2214 e1e_wphy(hw, 0x1F3E, 0x0067);
2215
2216 e1e_wphy(hw, 0x1F54, 0x0065);
2217
2218 e1e_wphy(hw, 0x1F55, 0x002A);
2219
2220 e1e_wphy(hw, 0x1F56, 0x002A);
2221
2222 e1e_wphy(hw, 0x1F72, 0x3FB0);
2223
2224 e1e_wphy(hw, 0x1F76, 0xC0FF);
2225
2226 e1e_wphy(hw, 0x1F77, 0x1DEC);
2227
2228 e1e_wphy(hw, 0x1F78, 0xF9EF);
2229
2230 e1e_wphy(hw, 0x1F79, 0x0210);
2231
2232 e1e_wphy(hw, 0x1895, 0x0003);
2233
2234 e1e_wphy(hw, 0x1796, 0x0008);
2235
2236 e1e_wphy(hw, 0x1798, 0xD008);
2237
2238
2239
2240
2241 e1e_wphy(hw, 0x1898, 0xD918);
2242
2243 e1e_wphy(hw, 0x187A, 0x0800);
2244
2245
2246
2247
2248 e1e_wphy(hw, 0x0019, 0x008D);
2249
2250 e1e_wphy(hw, 0x001B, 0x2080);
2251
2252 e1e_wphy(hw, 0x0014, 0x0045);
2253
2254 e1e_wphy(hw, 0x0000, 0x1340);
2255
2256 return 0;
2257}
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
2269{
2270 if (hw->phy.ops.get_cfg_done)
2271 return hw->phy.ops.get_cfg_done(hw);
2272
2273 return 0;
2274}
2275
2276
2277
2278
2279
2280
2281
2282
2283static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2284{
2285 if (hw->phy.ops.force_speed_duplex)
2286 return hw->phy.ops.force_speed_duplex(hw);
2287
2288 return 0;
2289}
2290
2291
2292
2293
2294
2295
2296
2297enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2298{
2299 enum e1000_phy_type phy_type = e1000_phy_unknown;
2300
2301 switch (phy_id) {
2302 case M88E1000_I_PHY_ID:
2303 case M88E1000_E_PHY_ID:
2304 case M88E1111_I_PHY_ID:
2305 case M88E1011_I_PHY_ID:
2306 phy_type = e1000_phy_m88;
2307 break;
2308 case IGP01E1000_I_PHY_ID:
2309 phy_type = e1000_phy_igp_2;
2310 break;
2311 case GG82563_E_PHY_ID:
2312 phy_type = e1000_phy_gg82563;
2313 break;
2314 case IGP03E1000_E_PHY_ID:
2315 phy_type = e1000_phy_igp_3;
2316 break;
2317 case IFE_E_PHY_ID:
2318 case IFE_PLUS_E_PHY_ID:
2319 case IFE_C_E_PHY_ID:
2320 phy_type = e1000_phy_ife;
2321 break;
2322 case BME1000_E_PHY_ID:
2323 case BME1000_E_PHY_ID_R2:
2324 phy_type = e1000_phy_bm;
2325 break;
2326 case I82578_E_PHY_ID:
2327 phy_type = e1000_phy_82578;
2328 break;
2329 case I82577_E_PHY_ID:
2330 phy_type = e1000_phy_82577;
2331 break;
2332 case I82579_E_PHY_ID:
2333 phy_type = e1000_phy_82579;
2334 break;
2335 default:
2336 phy_type = e1000_phy_unknown;
2337 break;
2338 }
2339 return phy_type;
2340}
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2351{
2352 s32 ret_val = -E1000_ERR_PHY_TYPE;
2353 u32 phy_addr = 0;
2354 u32 i;
2355 enum e1000_phy_type phy_type = e1000_phy_unknown;
2356
2357 hw->phy.id = phy_type;
2358
2359 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2360 hw->phy.addr = phy_addr;
2361 i = 0;
2362
2363 do {
2364 e1000e_get_phy_id(hw);
2365 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2366
2367
2368
2369
2370
2371 if (phy_type != e1000_phy_unknown) {
2372 ret_val = 0;
2373 goto out;
2374 }
2375 msleep(1);
2376 i++;
2377 } while (i < 10);
2378 }
2379
2380out:
2381 return ret_val;
2382}
2383
2384
2385
2386
2387
2388
2389
2390static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2391{
2392 u32 phy_addr = 2;
2393
2394 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2395 phy_addr = 1;
2396
2397 return phy_addr;
2398}
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2410{
2411 s32 ret_val;
2412 u32 page_select = 0;
2413 u32 page = offset >> IGP_PAGE_SHIFT;
2414 u32 page_shift = 0;
2415
2416 ret_val = hw->phy.ops.acquire(hw);
2417 if (ret_val)
2418 return ret_val;
2419
2420
2421 if (page == BM_WUC_PAGE) {
2422 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2423 false);
2424 goto out;
2425 }
2426
2427 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2428
2429 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2430
2431
2432
2433
2434
2435 if (hw->phy.addr == 1) {
2436 page_shift = IGP_PAGE_SHIFT;
2437 page_select = IGP01E1000_PHY_PAGE_SELECT;
2438 } else {
2439 page_shift = 0;
2440 page_select = BM_PHY_PAGE_SELECT;
2441 }
2442
2443
2444 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2445 (page << page_shift));
2446 if (ret_val)
2447 goto out;
2448 }
2449
2450 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2451 data);
2452
2453out:
2454 hw->phy.ops.release(hw);
2455 return ret_val;
2456}
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2469{
2470 s32 ret_val;
2471 u32 page_select = 0;
2472 u32 page = offset >> IGP_PAGE_SHIFT;
2473 u32 page_shift = 0;
2474
2475 ret_val = hw->phy.ops.acquire(hw);
2476 if (ret_val)
2477 return ret_val;
2478
2479
2480 if (page == BM_WUC_PAGE) {
2481 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2482 true);
2483 goto out;
2484 }
2485
2486 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2487
2488 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2489
2490
2491
2492
2493
2494 if (hw->phy.addr == 1) {
2495 page_shift = IGP_PAGE_SHIFT;
2496 page_select = IGP01E1000_PHY_PAGE_SELECT;
2497 } else {
2498 page_shift = 0;
2499 page_select = BM_PHY_PAGE_SELECT;
2500 }
2501
2502
2503 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2504 (page << page_shift));
2505 if (ret_val)
2506 goto out;
2507 }
2508
2509 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2510 data);
2511out:
2512 hw->phy.ops.release(hw);
2513 return ret_val;
2514}
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2527{
2528 s32 ret_val;
2529 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2530
2531 ret_val = hw->phy.ops.acquire(hw);
2532 if (ret_val)
2533 return ret_val;
2534
2535
2536 if (page == BM_WUC_PAGE) {
2537 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2538 true);
2539 goto out;
2540 }
2541
2542 hw->phy.addr = 1;
2543
2544 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2545
2546
2547 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2548 page);
2549
2550 if (ret_val)
2551 goto out;
2552 }
2553
2554 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2555 data);
2556out:
2557 hw->phy.ops.release(hw);
2558 return ret_val;
2559}
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2571{
2572 s32 ret_val;
2573 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2574
2575 ret_val = hw->phy.ops.acquire(hw);
2576 if (ret_val)
2577 return ret_val;
2578
2579
2580 if (page == BM_WUC_PAGE) {
2581 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2582 false);
2583 goto out;
2584 }
2585
2586 hw->phy.addr = 1;
2587
2588 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2589
2590 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2591 page);
2592
2593 if (ret_val)
2594 goto out;
2595 }
2596
2597 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2598 data);
2599
2600out:
2601 hw->phy.ops.release(hw);
2602 return ret_val;
2603}
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2625 u16 *data, bool read)
2626{
2627 s32 ret_val;
2628 u16 reg = BM_PHY_REG_NUM(offset);
2629 u16 phy_reg = 0;
2630
2631
2632 if ((hw->mac.type == e1000_pchlan) &&
2633 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2634 e_dbg("Attempting to access page 800 while gig enabled.\n");
2635
2636
2637 hw->phy.addr = 1;
2638
2639
2640 e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2641 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
2642
2643 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg);
2644 if (ret_val) {
2645 e_dbg("Could not read PHY page 769\n");
2646 goto out;
2647 }
2648
2649
2650 phy_reg &= ~(BM_WUC_HOST_WU_BIT);
2651 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2652 if (ret_val) {
2653 e_dbg("Could not clear PHY page 769 bit 4\n");
2654 goto out;
2655 }
2656
2657
2658 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG,
2659 phy_reg | BM_WUC_ENABLE_BIT);
2660 if (ret_val) {
2661 e_dbg("Could not write PHY page 769 bit 2\n");
2662 goto out;
2663 }
2664
2665
2666 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2667 (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2668
2669
2670 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2671 if (ret_val) {
2672 e_dbg("Could not write address opcode to page 800\n");
2673 goto out;
2674 }
2675
2676 if (read) {
2677
2678 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2679 data);
2680 } else {
2681
2682 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2683 *data);
2684 }
2685
2686 if (ret_val) {
2687 e_dbg("Could not access data value from page 800\n");
2688 goto out;
2689 }
2690
2691
2692
2693
2694
2695 e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2696 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
2697
2698
2699 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2700 if (ret_val) {
2701 e_dbg("Could not clear PHY page 769 bit 2\n");
2702 goto out;
2703 }
2704
2705out:
2706 return ret_val;
2707}
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717void e1000_power_up_phy_copper(struct e1000_hw *hw)
2718{
2719 u16 mii_reg = 0;
2720
2721
2722 e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2723 mii_reg &= ~MII_CR_POWER_DOWN;
2724 e1e_wphy(hw, PHY_CONTROL, mii_reg);
2725}
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735void e1000_power_down_phy_copper(struct e1000_hw *hw)
2736{
2737 u16 mii_reg = 0;
2738
2739
2740 e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2741 mii_reg |= MII_CR_POWER_DOWN;
2742 e1e_wphy(hw, PHY_CONTROL, mii_reg);
2743 msleep(1);
2744}
2745
2746
2747
2748
2749
2750
2751
2752
2753s32 e1000e_commit_phy(struct e1000_hw *hw)
2754{
2755 if (hw->phy.ops.commit)
2756 return hw->phy.ops.commit(hw);
2757
2758 return 0;
2759}
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2776{
2777 if (hw->phy.ops.set_d0_lplu_state)
2778 return hw->phy.ops.set_d0_lplu_state(hw, active);
2779
2780 return 0;
2781}
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2795 bool locked)
2796{
2797 s32 ret_val;
2798 u16 page = BM_PHY_REG_PAGE(offset);
2799 u16 reg = BM_PHY_REG_NUM(offset);
2800
2801 if (!locked) {
2802 ret_val = hw->phy.ops.acquire(hw);
2803 if (ret_val)
2804 return ret_val;
2805 }
2806
2807
2808 if (page == BM_WUC_PAGE) {
2809 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
2810 data, true);
2811 goto out;
2812 }
2813
2814 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2815 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2816 data, true);
2817 goto out;
2818 }
2819
2820 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2821
2822 if (page == HV_INTC_FC_PAGE_START)
2823 page = 0;
2824
2825 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2826 u32 phy_addr = hw->phy.addr;
2827
2828 hw->phy.addr = 1;
2829
2830
2831 ret_val = e1000e_write_phy_reg_mdic(hw,
2832 IGP01E1000_PHY_PAGE_SELECT,
2833 (page << IGP_PAGE_SHIFT));
2834 hw->phy.addr = phy_addr;
2835
2836 if (ret_val)
2837 goto out;
2838 }
2839
2840 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2841 data);
2842out:
2843 if (!locked)
2844 hw->phy.ops.release(hw);
2845
2846 return ret_val;
2847}
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2860{
2861 return __e1000_read_phy_reg_hv(hw, offset, data, false);
2862}
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2874{
2875 return __e1000_read_phy_reg_hv(hw, offset, data, true);
2876}
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2889 bool locked)
2890{
2891 s32 ret_val;
2892 u16 page = BM_PHY_REG_PAGE(offset);
2893 u16 reg = BM_PHY_REG_NUM(offset);
2894
2895 if (!locked) {
2896 ret_val = hw->phy.ops.acquire(hw);
2897 if (ret_val)
2898 return ret_val;
2899 }
2900
2901
2902 if (page == BM_WUC_PAGE) {
2903 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
2904 &data, false);
2905 goto out;
2906 }
2907
2908 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2909 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2910 &data, false);
2911 goto out;
2912 }
2913
2914 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2915
2916 if (page == HV_INTC_FC_PAGE_START)
2917 page = 0;
2918
2919
2920
2921
2922
2923 if ((hw->phy.type == e1000_phy_82578) &&
2924 (hw->phy.revision >= 1) &&
2925 (hw->phy.addr == 2) &&
2926 ((MAX_PHY_REG_ADDRESS & reg) == 0) &&
2927 (data & (1 << 11))) {
2928 u16 data2 = 0x7EFF;
2929 ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3,
2930 &data2, false);
2931 if (ret_val)
2932 goto out;
2933 }
2934
2935 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2936 u32 phy_addr = hw->phy.addr;
2937
2938 hw->phy.addr = 1;
2939
2940
2941 ret_val = e1000e_write_phy_reg_mdic(hw,
2942 IGP01E1000_PHY_PAGE_SELECT,
2943 (page << IGP_PAGE_SHIFT));
2944 hw->phy.addr = phy_addr;
2945
2946 if (ret_val)
2947 goto out;
2948 }
2949
2950 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2951 data);
2952
2953out:
2954 if (!locked)
2955 hw->phy.ops.release(hw);
2956
2957 return ret_val;
2958}
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
2970{
2971 return __e1000_write_phy_reg_hv(hw, offset, data, false);
2972}
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
2984{
2985 return __e1000_write_phy_reg_hv(hw, offset, data, true);
2986}
2987
2988
2989
2990
2991
2992static u32 e1000_get_phy_addr_for_hv_page(u32 page)
2993{
2994 u32 phy_addr = 2;
2995
2996 if (page >= HV_INTC_FC_PAGE_START)
2997 phy_addr = 1;
2998
2999 return phy_addr;
3000}
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3014 u16 *data, bool read)
3015{
3016 s32 ret_val;
3017 u32 addr_reg = 0;
3018 u32 data_reg = 0;
3019
3020
3021 addr_reg = (hw->phy.type == e1000_phy_82578) ?
3022 I82578_ADDR_REG : I82577_ADDR_REG;
3023 data_reg = addr_reg + 1;
3024
3025
3026 hw->phy.addr = 2;
3027
3028
3029 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3030 if (ret_val) {
3031 e_dbg("Could not write PHY the HV address register\n");
3032 goto out;
3033 }
3034
3035
3036 if (read)
3037 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3038 else
3039 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3040
3041 if (ret_val) {
3042 e_dbg("Could not read data value from HV data register\n");
3043 goto out;
3044 }
3045
3046out:
3047 return ret_val;
3048}
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3062{
3063 s32 ret_val = 0;
3064 u16 data;
3065
3066 if (hw->phy.type != e1000_phy_82578)
3067 goto out;
3068
3069
3070 e1e_rphy(hw, PHY_CONTROL, &data);
3071 if (data & PHY_CONTROL_LB)
3072 goto out;
3073
3074
3075 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
3076 if (ret_val)
3077 goto out;
3078
3079 data &= BM_CS_STATUS_LINK_UP |
3080 BM_CS_STATUS_RESOLVED |
3081 BM_CS_STATUS_SPEED_MASK;
3082
3083 if (data != (BM_CS_STATUS_LINK_UP |
3084 BM_CS_STATUS_RESOLVED |
3085 BM_CS_STATUS_SPEED_1000))
3086 goto out;
3087
3088 mdelay(200);
3089
3090
3091 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC |
3092 HV_MUX_DATA_CTRL_FORCE_SPEED);
3093 if (ret_val)
3094 goto out;
3095
3096 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
3097
3098out:
3099 return ret_val;
3100}
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3111{
3112 struct e1000_phy_info *phy = &hw->phy;
3113 s32 ret_val;
3114 u16 data;
3115
3116 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3117
3118 if (!ret_val)
3119 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
3120 ? e1000_rev_polarity_reversed
3121 : e1000_rev_polarity_normal;
3122
3123 return ret_val;
3124}
3125
3126
3127
3128
3129
3130
3131
3132s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3133{
3134 struct e1000_phy_info *phy = &hw->phy;
3135 s32 ret_val;
3136 u16 phy_data;
3137 bool link;
3138
3139 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
3140 if (ret_val)
3141 goto out;
3142
3143 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3144
3145 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
3146 if (ret_val)
3147 goto out;
3148
3149 udelay(1);
3150
3151 if (phy->autoneg_wait_to_complete) {
3152 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3153
3154 ret_val = e1000e_phy_has_link_generic(hw,
3155 PHY_FORCE_LIMIT,
3156 100000,
3157 &link);
3158 if (ret_val)
3159 goto out;
3160
3161 if (!link)
3162 e_dbg("Link taking longer than expected.\n");
3163
3164
3165 ret_val = e1000e_phy_has_link_generic(hw,
3166 PHY_FORCE_LIMIT,
3167 100000,
3168 &link);
3169 if (ret_val)
3170 goto out;
3171 }
3172
3173out:
3174 return ret_val;
3175}
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3187{
3188 struct e1000_phy_info *phy = &hw->phy;
3189 s32 ret_val;
3190 u16 data;
3191 bool link;
3192
3193 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3194 if (ret_val)
3195 goto out;
3196
3197 if (!link) {
3198 e_dbg("Phy info is only valid if link is up\n");
3199 ret_val = -E1000_ERR_CONFIG;
3200 goto out;
3201 }
3202
3203 phy->polarity_correction = true;
3204
3205 ret_val = e1000_check_polarity_82577(hw);
3206 if (ret_val)
3207 goto out;
3208
3209 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3210 if (ret_val)
3211 goto out;
3212
3213 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false;
3214
3215 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3216 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3217 ret_val = hw->phy.ops.get_cable_length(hw);
3218 if (ret_val)
3219 goto out;
3220
3221 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
3222 if (ret_val)
3223 goto out;
3224
3225 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3226 ? e1000_1000t_rx_status_ok
3227 : e1000_1000t_rx_status_not_ok;
3228
3229 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3230 ? e1000_1000t_rx_status_ok
3231 : e1000_1000t_rx_status_not_ok;
3232 } else {
3233 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3234 phy->local_rx = e1000_1000t_rx_status_undefined;
3235 phy->remote_rx = e1000_1000t_rx_status_undefined;
3236 }
3237
3238out:
3239 return ret_val;
3240}
3241
3242
3243
3244
3245
3246
3247
3248
3249s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3250{
3251 struct e1000_phy_info *phy = &hw->phy;
3252 s32 ret_val;
3253 u16 phy_data, length;
3254
3255 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3256 if (ret_val)
3257 goto out;
3258
3259 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3260 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
3261
3262 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3263 ret_val = -E1000_ERR_PHY;
3264
3265 phy->cable_length = length;
3266
3267out:
3268 return ret_val;
3269}
3270