1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32#include <linux/types.h>
33#include <linux/if_ether.h>
34
35#include "e1000_mac.h"
36#include "e1000_82575.h"
37
38static s32 igb_get_invariants_82575(struct e1000_hw *);
39static s32 igb_acquire_phy_82575(struct e1000_hw *);
40static void igb_release_phy_82575(struct e1000_hw *);
41static s32 igb_acquire_nvm_82575(struct e1000_hw *);
42static void igb_release_nvm_82575(struct e1000_hw *);
43static s32 igb_check_for_link_82575(struct e1000_hw *);
44static s32 igb_get_cfg_done_82575(struct e1000_hw *);
45static s32 igb_init_hw_82575(struct e1000_hw *);
46static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
47static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
48static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
49static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
50static s32 igb_reset_hw_82575(struct e1000_hw *);
51static s32 igb_reset_hw_82580(struct e1000_hw *);
52static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
53static s32 igb_setup_copper_link_82575(struct e1000_hw *);
54static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
55static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
56static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
57static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
58static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
59 u16 *);
60static s32 igb_get_phy_id_82575(struct e1000_hw *);
61static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
62static bool igb_sgmii_active_82575(struct e1000_hw *);
63static s32 igb_reset_init_script_82575(struct e1000_hw *);
64static s32 igb_read_mac_addr_82575(struct e1000_hw *);
65static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
66static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
67
68static const u16 e1000_82580_rxpbs_table[] =
69 { 36, 72, 144, 1, 2, 4, 8, 16,
70 35, 70, 140 };
71#define E1000_82580_RXPBS_TABLE_SIZE \
72 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
73
74
75
76
77
78
79
80
81static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
82{
83 u32 reg = 0;
84 bool ext_mdio = false;
85
86 switch (hw->mac.type) {
87 case e1000_82575:
88 case e1000_82576:
89 reg = rd32(E1000_MDIC);
90 ext_mdio = !!(reg & E1000_MDIC_DEST);
91 break;
92 case e1000_82580:
93 case e1000_i350:
94 reg = rd32(E1000_MDICNFG);
95 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
96 break;
97 default:
98 break;
99 }
100 return ext_mdio;
101}
102
103static s32 igb_get_invariants_82575(struct e1000_hw *hw)
104{
105 struct e1000_phy_info *phy = &hw->phy;
106 struct e1000_nvm_info *nvm = &hw->nvm;
107 struct e1000_mac_info *mac = &hw->mac;
108 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
109 u32 eecd;
110 s32 ret_val;
111 u16 size;
112 u32 ctrl_ext = 0;
113
114 switch (hw->device_id) {
115 case E1000_DEV_ID_82575EB_COPPER:
116 case E1000_DEV_ID_82575EB_FIBER_SERDES:
117 case E1000_DEV_ID_82575GB_QUAD_COPPER:
118 mac->type = e1000_82575;
119 break;
120 case E1000_DEV_ID_82576:
121 case E1000_DEV_ID_82576_NS:
122 case E1000_DEV_ID_82576_NS_SERDES:
123 case E1000_DEV_ID_82576_FIBER:
124 case E1000_DEV_ID_82576_SERDES:
125 case E1000_DEV_ID_82576_QUAD_COPPER:
126 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
127 case E1000_DEV_ID_82576_SERDES_QUAD:
128 mac->type = e1000_82576;
129 break;
130 case E1000_DEV_ID_82580_COPPER:
131 case E1000_DEV_ID_82580_FIBER:
132 case E1000_DEV_ID_82580_SERDES:
133 case E1000_DEV_ID_82580_SGMII:
134 case E1000_DEV_ID_82580_COPPER_DUAL:
135 case E1000_DEV_ID_DH89XXCC_SGMII:
136 case E1000_DEV_ID_DH89XXCC_SERDES:
137 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
138 case E1000_DEV_ID_DH89XXCC_SFP:
139 mac->type = e1000_82580;
140 break;
141 case E1000_DEV_ID_I350_COPPER:
142 case E1000_DEV_ID_I350_FIBER:
143 case E1000_DEV_ID_I350_SERDES:
144 case E1000_DEV_ID_I350_SGMII:
145 mac->type = e1000_i350;
146 break;
147 default:
148 return -E1000_ERR_MAC_INIT;
149 break;
150 }
151
152
153
154
155
156
157
158
159
160 phy->media_type = e1000_media_type_copper;
161 dev_spec->sgmii_active = false;
162
163 ctrl_ext = rd32(E1000_CTRL_EXT);
164 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
165 case E1000_CTRL_EXT_LINK_MODE_SGMII:
166 dev_spec->sgmii_active = true;
167 break;
168 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
169 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
170 hw->phy.media_type = e1000_media_type_internal_serdes;
171 break;
172 default:
173 break;
174 }
175
176
177 mac->mta_reg_count = 128;
178
179 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
180 if (mac->type == e1000_82576)
181 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
182 if (mac->type == e1000_82580)
183 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
184 if (mac->type == e1000_i350)
185 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
186
187 if (mac->type >= e1000_82580)
188 mac->ops.reset_hw = igb_reset_hw_82580;
189 else
190 mac->ops.reset_hw = igb_reset_hw_82575;
191
192 mac->asf_firmware_present = true;
193
194 mac->arc_subsystem_valid =
195 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
196 ? true : false;
197
198
199 mac->ops.setup_physical_interface =
200 (hw->phy.media_type == e1000_media_type_copper)
201 ? igb_setup_copper_link_82575
202 : igb_setup_serdes_link_82575;
203
204
205 eecd = rd32(E1000_EECD);
206
207 nvm->opcode_bits = 8;
208 nvm->delay_usec = 1;
209 switch (nvm->override) {
210 case e1000_nvm_override_spi_large:
211 nvm->page_size = 32;
212 nvm->address_bits = 16;
213 break;
214 case e1000_nvm_override_spi_small:
215 nvm->page_size = 8;
216 nvm->address_bits = 8;
217 break;
218 default:
219 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
220 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
221 break;
222 }
223
224 nvm->type = e1000_nvm_eeprom_spi;
225
226 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
227 E1000_EECD_SIZE_EX_SHIFT);
228
229
230
231
232
233 size += NVM_WORD_SIZE_BASE_SHIFT;
234
235
236 if (size > 14)
237 size = 14;
238 nvm->word_size = 1 << size;
239
240
241 if (mac->type == e1000_82576)
242 igb_init_mbx_params_pf(hw);
243
244
245 if (phy->media_type != e1000_media_type_copper) {
246 phy->type = e1000_phy_none;
247 return 0;
248 }
249
250 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
251 phy->reset_delay_us = 100;
252
253 ctrl_ext = rd32(E1000_CTRL_EXT);
254
255
256 if (igb_sgmii_active_82575(hw)) {
257 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
258 ctrl_ext |= E1000_CTRL_I2C_ENA;
259 } else {
260 phy->ops.reset = igb_phy_hw_reset;
261 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
262 }
263
264 wr32(E1000_CTRL_EXT, ctrl_ext);
265 igb_reset_mdicnfg_82580(hw);
266
267 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
268 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
269 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
270 } else if (hw->mac.type >= e1000_82580) {
271 phy->ops.read_reg = igb_read_phy_reg_82580;
272 phy->ops.write_reg = igb_write_phy_reg_82580;
273 } else {
274 phy->ops.read_reg = igb_read_phy_reg_igp;
275 phy->ops.write_reg = igb_write_phy_reg_igp;
276 }
277
278
279 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
280 E1000_STATUS_FUNC_SHIFT;
281
282
283 ret_val = igb_get_phy_id_82575(hw);
284 if (ret_val)
285 return ret_val;
286
287
288 switch (phy->id) {
289 case I347AT4_E_PHY_ID:
290 case M88E1112_E_PHY_ID:
291 case M88E1111_I_PHY_ID:
292 phy->type = e1000_phy_m88;
293 phy->ops.get_phy_info = igb_get_phy_info_m88;
294
295 if (phy->id == I347AT4_E_PHY_ID ||
296 phy->id == M88E1112_E_PHY_ID)
297 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
298 else
299 phy->ops.get_cable_length = igb_get_cable_length_m88;
300
301 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
302 break;
303 case IGP03E1000_E_PHY_ID:
304 phy->type = e1000_phy_igp_3;
305 phy->ops.get_phy_info = igb_get_phy_info_igp;
306 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
307 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
308 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
309 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
310 break;
311 case I82580_I_PHY_ID:
312 case I350_I_PHY_ID:
313 phy->type = e1000_phy_82580;
314 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_82580;
315 phy->ops.get_cable_length = igb_get_cable_length_82580;
316 phy->ops.get_phy_info = igb_get_phy_info_82580;
317 break;
318 default:
319 return -E1000_ERR_PHY;
320 }
321
322 return 0;
323}
324
325
326
327
328
329
330
331
332static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
333{
334 u16 mask = E1000_SWFW_PHY0_SM;
335
336 if (hw->bus.func == E1000_FUNC_1)
337 mask = E1000_SWFW_PHY1_SM;
338 else if (hw->bus.func == E1000_FUNC_2)
339 mask = E1000_SWFW_PHY2_SM;
340 else if (hw->bus.func == E1000_FUNC_3)
341 mask = E1000_SWFW_PHY3_SM;
342
343 return igb_acquire_swfw_sync_82575(hw, mask);
344}
345
346
347
348
349
350
351
352
353static void igb_release_phy_82575(struct e1000_hw *hw)
354{
355 u16 mask = E1000_SWFW_PHY0_SM;
356
357 if (hw->bus.func == E1000_FUNC_1)
358 mask = E1000_SWFW_PHY1_SM;
359 else if (hw->bus.func == E1000_FUNC_2)
360 mask = E1000_SWFW_PHY2_SM;
361 else if (hw->bus.func == E1000_FUNC_3)
362 mask = E1000_SWFW_PHY3_SM;
363
364 igb_release_swfw_sync_82575(hw, mask);
365}
366
367
368
369
370
371
372
373
374
375
376static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
377 u16 *data)
378{
379 s32 ret_val = -E1000_ERR_PARAM;
380
381 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
382 hw_dbg("PHY Address %u is out of range\n", offset);
383 goto out;
384 }
385
386 ret_val = hw->phy.ops.acquire(hw);
387 if (ret_val)
388 goto out;
389
390 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
391
392 hw->phy.ops.release(hw);
393
394out:
395 return ret_val;
396}
397
398
399
400
401
402
403
404
405
406
407static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
408 u16 data)
409{
410 s32 ret_val = -E1000_ERR_PARAM;
411
412
413 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
414 hw_dbg("PHY Address %d is out of range\n", offset);
415 goto out;
416 }
417
418 ret_val = hw->phy.ops.acquire(hw);
419 if (ret_val)
420 goto out;
421
422 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
423
424 hw->phy.ops.release(hw);
425
426out:
427 return ret_val;
428}
429
430
431
432
433
434
435
436
437static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
438{
439 struct e1000_phy_info *phy = &hw->phy;
440 s32 ret_val = 0;
441 u16 phy_id;
442 u32 ctrl_ext;
443 u32 mdic;
444
445
446
447
448
449
450
451
452 if (!(igb_sgmii_active_82575(hw))) {
453 phy->addr = 1;
454 ret_val = igb_get_phy_id(hw);
455 goto out;
456 }
457
458 if (igb_sgmii_uses_mdio_82575(hw)) {
459 switch (hw->mac.type) {
460 case e1000_82575:
461 case e1000_82576:
462 mdic = rd32(E1000_MDIC);
463 mdic &= E1000_MDIC_PHY_MASK;
464 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
465 break;
466 case e1000_82580:
467 case e1000_i350:
468 mdic = rd32(E1000_MDICNFG);
469 mdic &= E1000_MDICNFG_PHY_MASK;
470 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
471 break;
472 default:
473 ret_val = -E1000_ERR_PHY;
474 goto out;
475 break;
476 }
477 ret_val = igb_get_phy_id(hw);
478 goto out;
479 }
480
481
482 ctrl_ext = rd32(E1000_CTRL_EXT);
483 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
484 wrfl();
485 msleep(300);
486
487
488
489
490
491 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
492 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
493 if (ret_val == 0) {
494 hw_dbg("Vendor ID 0x%08X read at address %u\n",
495 phy_id, phy->addr);
496
497
498
499
500 if (phy_id == M88_VENDOR)
501 break;
502 } else {
503 hw_dbg("PHY address %u was unreadable\n", phy->addr);
504 }
505 }
506
507
508 if (phy->addr == 8) {
509 phy->addr = 0;
510 ret_val = -E1000_ERR_PHY;
511 goto out;
512 } else {
513 ret_val = igb_get_phy_id(hw);
514 }
515
516
517 wr32(E1000_CTRL_EXT, ctrl_ext);
518
519out:
520 return ret_val;
521}
522
523
524
525
526
527
528
529static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
530{
531 s32 ret_val;
532
533
534
535
536
537
538 hw_dbg("Soft resetting SGMII attached PHY...\n");
539
540
541
542
543
544 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
545 if (ret_val)
546 goto out;
547
548 ret_val = igb_phy_sw_reset(hw);
549
550out:
551 return ret_val;
552}
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
568{
569 struct e1000_phy_info *phy = &hw->phy;
570 s32 ret_val;
571 u16 data;
572
573 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
574 if (ret_val)
575 goto out;
576
577 if (active) {
578 data |= IGP02E1000_PM_D0_LPLU;
579 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
580 data);
581 if (ret_val)
582 goto out;
583
584
585 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
586 &data);
587 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
588 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
589 data);
590 if (ret_val)
591 goto out;
592 } else {
593 data &= ~IGP02E1000_PM_D0_LPLU;
594 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
595 data);
596
597
598
599
600
601
602 if (phy->smart_speed == e1000_smart_speed_on) {
603 ret_val = phy->ops.read_reg(hw,
604 IGP01E1000_PHY_PORT_CONFIG, &data);
605 if (ret_val)
606 goto out;
607
608 data |= IGP01E1000_PSCFR_SMART_SPEED;
609 ret_val = phy->ops.write_reg(hw,
610 IGP01E1000_PHY_PORT_CONFIG, data);
611 if (ret_val)
612 goto out;
613 } else if (phy->smart_speed == e1000_smart_speed_off) {
614 ret_val = phy->ops.read_reg(hw,
615 IGP01E1000_PHY_PORT_CONFIG, &data);
616 if (ret_val)
617 goto out;
618
619 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
620 ret_val = phy->ops.write_reg(hw,
621 IGP01E1000_PHY_PORT_CONFIG, data);
622 if (ret_val)
623 goto out;
624 }
625 }
626
627out:
628 return ret_val;
629}
630
631
632
633
634
635
636
637
638
639
640static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
641{
642 s32 ret_val;
643
644 ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
645 if (ret_val)
646 goto out;
647
648 ret_val = igb_acquire_nvm(hw);
649
650 if (ret_val)
651 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
652
653out:
654 return ret_val;
655}
656
657
658
659
660
661
662
663
664static void igb_release_nvm_82575(struct e1000_hw *hw)
665{
666 igb_release_nvm(hw);
667 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
668}
669
670
671
672
673
674
675
676
677
678static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
679{
680 u32 swfw_sync;
681 u32 swmask = mask;
682 u32 fwmask = mask << 16;
683 s32 ret_val = 0;
684 s32 i = 0, timeout = 200;
685
686 while (i < timeout) {
687 if (igb_get_hw_semaphore(hw)) {
688 ret_val = -E1000_ERR_SWFW_SYNC;
689 goto out;
690 }
691
692 swfw_sync = rd32(E1000_SW_FW_SYNC);
693 if (!(swfw_sync & (fwmask | swmask)))
694 break;
695
696
697
698
699
700 igb_put_hw_semaphore(hw);
701 mdelay(5);
702 i++;
703 }
704
705 if (i == timeout) {
706 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
707 ret_val = -E1000_ERR_SWFW_SYNC;
708 goto out;
709 }
710
711 swfw_sync |= swmask;
712 wr32(E1000_SW_FW_SYNC, swfw_sync);
713
714 igb_put_hw_semaphore(hw);
715
716out:
717 return ret_val;
718}
719
720
721
722
723
724
725
726
727
728static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
729{
730 u32 swfw_sync;
731
732 while (igb_get_hw_semaphore(hw) != 0);
733
734
735 swfw_sync = rd32(E1000_SW_FW_SYNC);
736 swfw_sync &= ~mask;
737 wr32(E1000_SW_FW_SYNC, swfw_sync);
738
739 igb_put_hw_semaphore(hw);
740}
741
742
743
744
745
746
747
748
749
750
751
752static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
753{
754 s32 timeout = PHY_CFG_TIMEOUT;
755 s32 ret_val = 0;
756 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
757
758 if (hw->bus.func == 1)
759 mask = E1000_NVM_CFG_DONE_PORT_1;
760 else if (hw->bus.func == E1000_FUNC_2)
761 mask = E1000_NVM_CFG_DONE_PORT_2;
762 else if (hw->bus.func == E1000_FUNC_3)
763 mask = E1000_NVM_CFG_DONE_PORT_3;
764
765 while (timeout) {
766 if (rd32(E1000_EEMNGCTL) & mask)
767 break;
768 msleep(1);
769 timeout--;
770 }
771 if (!timeout)
772 hw_dbg("MNG configuration cycle has not completed.\n");
773
774
775 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
776 (hw->phy.type == e1000_phy_igp_3))
777 igb_phy_init_script_igp3(hw);
778
779 return ret_val;
780}
781
782
783
784
785
786
787
788
789static s32 igb_check_for_link_82575(struct e1000_hw *hw)
790{
791 s32 ret_val;
792 u16 speed, duplex;
793
794 if (hw->phy.media_type != e1000_media_type_copper) {
795 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
796 &duplex);
797
798
799
800
801
802 hw->mac.get_link_status = !hw->mac.serdes_has_link;
803 } else {
804 ret_val = igb_check_for_copper_link(hw);
805 }
806
807 return ret_val;
808}
809
810
811
812
813
814void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
815{
816 u32 reg;
817
818
819 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
820 !igb_sgmii_active_82575(hw))
821 return;
822
823
824 reg = rd32(E1000_PCS_CFG0);
825 reg |= E1000_PCS_CFG_PCS_EN;
826 wr32(E1000_PCS_CFG0, reg);
827
828
829 reg = rd32(E1000_CTRL_EXT);
830 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
831 wr32(E1000_CTRL_EXT, reg);
832
833
834 wrfl();
835 msleep(1);
836}
837
838
839
840
841
842
843
844
845
846
847static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
848 u16 *duplex)
849{
850 struct e1000_mac_info *mac = &hw->mac;
851 u32 pcs;
852
853
854 mac->serdes_has_link = false;
855 *speed = 0;
856 *duplex = 0;
857
858
859
860
861
862
863 pcs = rd32(E1000_PCS_LSTAT);
864
865
866
867
868
869
870 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
871 mac->serdes_has_link = true;
872
873
874 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
875 *speed = SPEED_1000;
876 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
877 *speed = SPEED_100;
878 } else {
879 *speed = SPEED_10;
880 }
881
882
883 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
884 *duplex = FULL_DUPLEX;
885 } else {
886 *duplex = HALF_DUPLEX;
887 }
888 }
889
890 return 0;
891}
892
893
894
895
896
897
898
899
900void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
901{
902 u32 reg;
903
904 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
905 igb_sgmii_active_82575(hw))
906 return;
907
908 if (!igb_enable_mng_pass_thru(hw)) {
909
910 reg = rd32(E1000_PCS_CFG0);
911 reg &= ~E1000_PCS_CFG_PCS_EN;
912 wr32(E1000_PCS_CFG0, reg);
913
914
915 reg = rd32(E1000_CTRL_EXT);
916 reg |= E1000_CTRL_EXT_SDP3_DATA;
917 wr32(E1000_CTRL_EXT, reg);
918
919
920 wrfl();
921 msleep(1);
922 }
923}
924
925
926
927
928
929
930
931
932static s32 igb_reset_hw_82575(struct e1000_hw *hw)
933{
934 u32 ctrl, icr;
935 s32 ret_val;
936
937
938
939
940
941 ret_val = igb_disable_pcie_master(hw);
942 if (ret_val)
943 hw_dbg("PCI-E Master disable polling has failed.\n");
944
945
946 ret_val = igb_set_pcie_completion_timeout(hw);
947 if (ret_val) {
948 hw_dbg("PCI-E Set completion timeout has failed.\n");
949 }
950
951 hw_dbg("Masking off all interrupts\n");
952 wr32(E1000_IMC, 0xffffffff);
953
954 wr32(E1000_RCTL, 0);
955 wr32(E1000_TCTL, E1000_TCTL_PSP);
956 wrfl();
957
958 msleep(10);
959
960 ctrl = rd32(E1000_CTRL);
961
962 hw_dbg("Issuing a global reset to MAC\n");
963 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
964
965 ret_val = igb_get_auto_rd_done(hw);
966 if (ret_val) {
967
968
969
970
971
972 hw_dbg("Auto Read Done did not complete\n");
973 }
974
975
976 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
977 igb_reset_init_script_82575(hw);
978
979
980 wr32(E1000_IMC, 0xffffffff);
981 icr = rd32(E1000_ICR);
982
983
984 ret_val = igb_check_alt_mac_addr(hw);
985
986 return ret_val;
987}
988
989
990
991
992
993
994
995static s32 igb_init_hw_82575(struct e1000_hw *hw)
996{
997 struct e1000_mac_info *mac = &hw->mac;
998 s32 ret_val;
999 u16 i, rar_count = mac->rar_entry_count;
1000
1001
1002 ret_val = igb_id_led_init(hw);
1003 if (ret_val) {
1004 hw_dbg("Error initializing identification LED\n");
1005
1006 }
1007
1008
1009 hw_dbg("Initializing the IEEE VLAN\n");
1010 igb_clear_vfta(hw);
1011
1012
1013 igb_init_rx_addrs(hw, rar_count);
1014
1015
1016 hw_dbg("Zeroing the MTA\n");
1017 for (i = 0; i < mac->mta_reg_count; i++)
1018 array_wr32(E1000_MTA, i, 0);
1019
1020
1021 hw_dbg("Zeroing the UTA\n");
1022 for (i = 0; i < mac->uta_reg_count; i++)
1023 array_wr32(E1000_UTA, i, 0);
1024
1025
1026 ret_val = igb_setup_link(hw);
1027
1028
1029
1030
1031
1032
1033
1034 igb_clear_hw_cntrs_82575(hw);
1035
1036 return ret_val;
1037}
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1048{
1049 u32 ctrl;
1050 s32 ret_val;
1051
1052 ctrl = rd32(E1000_CTRL);
1053 ctrl |= E1000_CTRL_SLU;
1054 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1055 wr32(E1000_CTRL, ctrl);
1056
1057 ret_val = igb_setup_serdes_link_82575(hw);
1058 if (ret_val)
1059 goto out;
1060
1061 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1062
1063 msleep(300);
1064
1065 ret_val = hw->phy.ops.reset(hw);
1066 if (ret_val) {
1067 hw_dbg("Error resetting the PHY.\n");
1068 goto out;
1069 }
1070 }
1071 switch (hw->phy.type) {
1072 case e1000_phy_m88:
1073 if (hw->phy.id == I347AT4_E_PHY_ID ||
1074 hw->phy.id == M88E1112_E_PHY_ID)
1075 ret_val = igb_copper_link_setup_m88_gen2(hw);
1076 else
1077 ret_val = igb_copper_link_setup_m88(hw);
1078 break;
1079 case e1000_phy_igp_3:
1080 ret_val = igb_copper_link_setup_igp(hw);
1081 break;
1082 case e1000_phy_82580:
1083 ret_val = igb_copper_link_setup_82580(hw);
1084 break;
1085 default:
1086 ret_val = -E1000_ERR_PHY;
1087 break;
1088 }
1089
1090 if (ret_val)
1091 goto out;
1092
1093 ret_val = igb_setup_copper_link(hw);
1094out:
1095 return ret_val;
1096}
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1108{
1109 u32 ctrl_ext, ctrl_reg, reg;
1110 bool pcs_autoneg;
1111
1112 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1113 !igb_sgmii_active_82575(hw))
1114 return 0;
1115
1116
1117
1118
1119
1120
1121
1122 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1123
1124
1125 ctrl_ext = rd32(E1000_CTRL_EXT);
1126 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1127 wr32(E1000_CTRL_EXT, ctrl_ext);
1128
1129 ctrl_reg = rd32(E1000_CTRL);
1130 ctrl_reg |= E1000_CTRL_SLU;
1131
1132 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1133
1134 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1135
1136
1137 reg = rd32(E1000_CONNSW);
1138 reg |= E1000_CONNSW_ENRGSRC;
1139 wr32(E1000_CONNSW, reg);
1140 }
1141
1142 reg = rd32(E1000_PCS_LCTL);
1143
1144
1145 pcs_autoneg = hw->mac.autoneg;
1146
1147 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1148 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1149
1150 pcs_autoneg = true;
1151
1152 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1153 break;
1154 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1155
1156 pcs_autoneg = false;
1157 default:
1158
1159
1160
1161
1162
1163 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1164 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1165
1166
1167 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1168 break;
1169 }
1170
1171 wr32(E1000_CTRL, ctrl_reg);
1172
1173
1174
1175
1176
1177
1178
1179 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1180 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1181
1182
1183
1184
1185
1186 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1187
1188 if (pcs_autoneg) {
1189
1190 reg |= E1000_PCS_LCTL_AN_ENABLE |
1191 E1000_PCS_LCTL_AN_RESTART;
1192 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1193 } else {
1194
1195 reg |= E1000_PCS_LCTL_FSD;
1196
1197 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1198 }
1199
1200 wr32(E1000_PCS_LCTL, reg);
1201
1202 if (!igb_sgmii_active_82575(hw))
1203 igb_force_mac_fc(hw);
1204
1205 return 0;
1206}
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1217{
1218 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1219 return dev_spec->sgmii_active;
1220}
1221
1222
1223
1224
1225
1226
1227
1228
1229static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1230{
1231 if (hw->mac.type == e1000_82575) {
1232 hw_dbg("Running reset init script for 82575\n");
1233
1234 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1235 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1236 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1237 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1238
1239
1240 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1241 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1242
1243
1244 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1245 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1246 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1247 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1248
1249
1250 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1251 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1252 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1253 }
1254
1255 return 0;
1256}
1257
1258
1259
1260
1261
1262static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1263{
1264 s32 ret_val = 0;
1265
1266
1267
1268
1269
1270
1271 ret_val = igb_check_alt_mac_addr(hw);
1272 if (ret_val)
1273 goto out;
1274
1275 ret_val = igb_read_mac_addr(hw);
1276
1277out:
1278 return ret_val;
1279}
1280
1281
1282
1283
1284
1285
1286
1287
1288void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1289{
1290
1291 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1292 igb_power_down_phy_copper(hw);
1293}
1294
1295
1296
1297
1298
1299
1300
1301static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1302{
1303 igb_clear_hw_cntrs_base(hw);
1304
1305 rd32(E1000_PRC64);
1306 rd32(E1000_PRC127);
1307 rd32(E1000_PRC255);
1308 rd32(E1000_PRC511);
1309 rd32(E1000_PRC1023);
1310 rd32(E1000_PRC1522);
1311 rd32(E1000_PTC64);
1312 rd32(E1000_PTC127);
1313 rd32(E1000_PTC255);
1314 rd32(E1000_PTC511);
1315 rd32(E1000_PTC1023);
1316 rd32(E1000_PTC1522);
1317
1318 rd32(E1000_ALGNERRC);
1319 rd32(E1000_RXERRC);
1320 rd32(E1000_TNCRS);
1321 rd32(E1000_CEXTERR);
1322 rd32(E1000_TSCTC);
1323 rd32(E1000_TSCTFC);
1324
1325 rd32(E1000_MGTPRC);
1326 rd32(E1000_MGTPDC);
1327 rd32(E1000_MGTPTC);
1328
1329 rd32(E1000_IAC);
1330 rd32(E1000_ICRXOC);
1331
1332 rd32(E1000_ICRXPTC);
1333 rd32(E1000_ICRXATC);
1334 rd32(E1000_ICTXPTC);
1335 rd32(E1000_ICTXATC);
1336 rd32(E1000_ICTXQEC);
1337 rd32(E1000_ICTXQMTC);
1338 rd32(E1000_ICRXDMTC);
1339
1340 rd32(E1000_CBTMPC);
1341 rd32(E1000_HTDPMC);
1342 rd32(E1000_CBRMPC);
1343 rd32(E1000_RPTHC);
1344 rd32(E1000_HGPTC);
1345 rd32(E1000_HTCBDPC);
1346 rd32(E1000_HGORCL);
1347 rd32(E1000_HGORCH);
1348 rd32(E1000_HGOTCL);
1349 rd32(E1000_HGOTCH);
1350 rd32(E1000_LENERRS);
1351
1352
1353 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1354 igb_sgmii_active_82575(hw))
1355 rd32(E1000_SCVPC);
1356}
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1368{
1369 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1370 int i, ms_wait;
1371
1372 if (hw->mac.type != e1000_82575 ||
1373 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1374 return;
1375
1376
1377 for (i = 0; i < 4; i++) {
1378 rxdctl[i] = rd32(E1000_RXDCTL(i));
1379 wr32(E1000_RXDCTL(i),
1380 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1381 }
1382
1383 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1384 msleep(1);
1385 rx_enabled = 0;
1386 for (i = 0; i < 4; i++)
1387 rx_enabled |= rd32(E1000_RXDCTL(i));
1388 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1389 break;
1390 }
1391
1392 if (ms_wait == 10)
1393 hw_dbg("Queue disable timed out after 10ms\n");
1394
1395
1396
1397
1398
1399 rfctl = rd32(E1000_RFCTL);
1400 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1401
1402 rlpml = rd32(E1000_RLPML);
1403 wr32(E1000_RLPML, 0);
1404
1405 rctl = rd32(E1000_RCTL);
1406 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1407 temp_rctl |= E1000_RCTL_LPE;
1408
1409 wr32(E1000_RCTL, temp_rctl);
1410 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1411 wrfl();
1412 msleep(2);
1413
1414
1415
1416
1417 for (i = 0; i < 4; i++)
1418 wr32(E1000_RXDCTL(i), rxdctl[i]);
1419 wr32(E1000_RCTL, rctl);
1420 wrfl();
1421
1422 wr32(E1000_RLPML, rlpml);
1423 wr32(E1000_RFCTL, rfctl);
1424
1425
1426 rd32(E1000_ROC);
1427 rd32(E1000_RNBC);
1428 rd32(E1000_MPC);
1429}
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1442{
1443 u32 gcr = rd32(E1000_GCR);
1444 s32 ret_val = 0;
1445 u16 pcie_devctl2;
1446
1447
1448 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1449 goto out;
1450
1451
1452
1453
1454
1455 if (!(gcr & E1000_GCR_CAP_VER2)) {
1456 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1457 goto out;
1458 }
1459
1460
1461
1462
1463
1464
1465 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1466 &pcie_devctl2);
1467 if (ret_val)
1468 goto out;
1469
1470 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1471
1472 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1473 &pcie_devctl2);
1474out:
1475
1476 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1477
1478 wr32(E1000_GCR, gcr);
1479 return ret_val;
1480}
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
1491{
1492 u32 dtxswc;
1493
1494 switch (hw->mac.type) {
1495 case e1000_82576:
1496 case e1000_i350:
1497 dtxswc = rd32(E1000_DTXSWC);
1498 if (enable) {
1499 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
1500 E1000_DTXSWC_VLAN_SPOOF_MASK);
1501
1502
1503 dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
1504 } else {
1505 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
1506 E1000_DTXSWC_VLAN_SPOOF_MASK);
1507 }
1508 wr32(E1000_DTXSWC, dtxswc);
1509 break;
1510 default:
1511 break;
1512 }
1513}
1514
1515
1516
1517
1518
1519
1520
1521
1522void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1523{
1524 u32 dtxswc = rd32(E1000_DTXSWC);
1525
1526 if (enable)
1527 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1528 else
1529 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1530
1531 wr32(E1000_DTXSWC, dtxswc);
1532}
1533
1534
1535
1536
1537
1538
1539
1540
1541void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1542{
1543 u32 vt_ctl = rd32(E1000_VT_CTL);
1544
1545 if (enable)
1546 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
1547 else
1548 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
1549
1550 wr32(E1000_VT_CTL, vt_ctl);
1551}
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
1563{
1564 s32 ret_val;
1565
1566
1567 ret_val = hw->phy.ops.acquire(hw);
1568 if (ret_val)
1569 goto out;
1570
1571 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
1572
1573 hw->phy.ops.release(hw);
1574
1575out:
1576 return ret_val;
1577}
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
1588{
1589 s32 ret_val;
1590
1591
1592 ret_val = hw->phy.ops.acquire(hw);
1593 if (ret_val)
1594 goto out;
1595
1596 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
1597
1598 hw->phy.ops.release(hw);
1599
1600out:
1601 return ret_val;
1602}
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
1613{
1614 s32 ret_val = 0;
1615 u32 mdicnfg;
1616 u16 nvm_data = 0;
1617
1618 if (hw->mac.type != e1000_82580)
1619 goto out;
1620 if (!igb_sgmii_active_82575(hw))
1621 goto out;
1622
1623 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
1624 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
1625 &nvm_data);
1626 if (ret_val) {
1627 hw_dbg("NVM Read Error\n");
1628 goto out;
1629 }
1630
1631 mdicnfg = rd32(E1000_MDICNFG);
1632 if (nvm_data & NVM_WORD24_EXT_MDIO)
1633 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
1634 if (nvm_data & NVM_WORD24_COM_MDIO)
1635 mdicnfg |= E1000_MDICNFG_COM_MDIO;
1636 wr32(E1000_MDICNFG, mdicnfg);
1637out:
1638 return ret_val;
1639}
1640
1641
1642
1643
1644
1645
1646
1647
1648static s32 igb_reset_hw_82580(struct e1000_hw *hw)
1649{
1650 s32 ret_val = 0;
1651
1652 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
1653 u32 ctrl, icr;
1654 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
1655
1656
1657 hw->dev_spec._82575.global_device_reset = false;
1658
1659
1660 ctrl = rd32(E1000_CTRL);
1661
1662
1663
1664
1665
1666 ret_val = igb_disable_pcie_master(hw);
1667 if (ret_val)
1668 hw_dbg("PCI-E Master disable polling has failed.\n");
1669
1670 hw_dbg("Masking off all interrupts\n");
1671 wr32(E1000_IMC, 0xffffffff);
1672 wr32(E1000_RCTL, 0);
1673 wr32(E1000_TCTL, E1000_TCTL_PSP);
1674 wrfl();
1675
1676 msleep(10);
1677
1678
1679 if (global_device_reset &&
1680 igb_acquire_swfw_sync_82575(hw, swmbsw_mask))
1681 global_device_reset = false;
1682
1683 if (global_device_reset &&
1684 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
1685 ctrl |= E1000_CTRL_DEV_RST;
1686 else
1687 ctrl |= E1000_CTRL_RST;
1688
1689 wr32(E1000_CTRL, ctrl);
1690
1691
1692 if (global_device_reset)
1693 msleep(5);
1694
1695 ret_val = igb_get_auto_rd_done(hw);
1696 if (ret_val) {
1697
1698
1699
1700
1701
1702 hw_dbg("Auto Read Done did not complete\n");
1703 }
1704
1705
1706 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1707 igb_reset_init_script_82575(hw);
1708
1709
1710 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
1711
1712
1713 wr32(E1000_IMC, 0xffffffff);
1714 icr = rd32(E1000_ICR);
1715
1716 ret_val = igb_reset_mdicnfg_82580(hw);
1717 if (ret_val)
1718 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
1719
1720
1721 ret_val = igb_check_alt_mac_addr(hw);
1722
1723
1724 if (global_device_reset)
1725 igb_release_swfw_sync_82575(hw, swmbsw_mask);
1726
1727 return ret_val;
1728}
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740u16 igb_rxpbs_adjust_82580(u32 data)
1741{
1742 u16 ret_val = 0;
1743
1744 if (data < E1000_82580_RXPBS_TABLE_SIZE)
1745 ret_val = e1000_82580_rxpbs_table[data];
1746
1747 return ret_val;
1748}
1749
1750static struct e1000_mac_operations e1000_mac_ops_82575 = {
1751 .init_hw = igb_init_hw_82575,
1752 .check_for_link = igb_check_for_link_82575,
1753 .rar_set = igb_rar_set,
1754 .read_mac_addr = igb_read_mac_addr_82575,
1755 .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
1756};
1757
1758static struct e1000_phy_operations e1000_phy_ops_82575 = {
1759 .acquire = igb_acquire_phy_82575,
1760 .get_cfg_done = igb_get_cfg_done_82575,
1761 .release = igb_release_phy_82575,
1762};
1763
1764static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
1765 .acquire = igb_acquire_nvm_82575,
1766 .read = igb_read_nvm_eerd,
1767 .release = igb_release_nvm_82575,
1768 .write = igb_write_nvm_spi,
1769};
1770
1771const struct e1000_info e1000_82575_info = {
1772 .get_invariants = igb_get_invariants_82575,
1773 .mac_ops = &e1000_mac_ops_82575,
1774 .phy_ops = &e1000_phy_ops_82575,
1775 .nvm_ops = &e1000_nvm_ops_82575,
1776};
1777
1778