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28#ifndef _E1000_HW_H_
29#define _E1000_HW_H_
30
31#include <linux/types.h>
32#include <linux/delay.h>
33#include <linux/io.h>
34#include <linux/netdevice.h>
35
36#include "e1000_regs.h"
37#include "e1000_defines.h"
38
39struct e1000_hw;
40
41#define E1000_DEV_ID_82576 0x10C9
42#define E1000_DEV_ID_82576_FIBER 0x10E6
43#define E1000_DEV_ID_82576_SERDES 0x10E7
44#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
45#define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
46#define E1000_DEV_ID_82576_NS 0x150A
47#define E1000_DEV_ID_82576_NS_SERDES 0x1518
48#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
49#define E1000_DEV_ID_82575EB_COPPER 0x10A7
50#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
51#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
52#define E1000_DEV_ID_82580_COPPER 0x150E
53#define E1000_DEV_ID_82580_FIBER 0x150F
54#define E1000_DEV_ID_82580_SERDES 0x1510
55#define E1000_DEV_ID_82580_SGMII 0x1511
56#define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
57#define E1000_DEV_ID_DH89XXCC_SGMII 0x0438
58#define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
59#define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
60#define E1000_DEV_ID_DH89XXCC_SFP 0x0440
61#define E1000_DEV_ID_I350_COPPER 0x1521
62#define E1000_DEV_ID_I350_FIBER 0x1522
63#define E1000_DEV_ID_I350_SERDES 0x1523
64#define E1000_DEV_ID_I350_SGMII 0x1524
65
66#define E1000_REVISION_2 2
67#define E1000_REVISION_4 4
68
69#define E1000_FUNC_0 0
70#define E1000_FUNC_1 1
71#define E1000_FUNC_2 2
72#define E1000_FUNC_3 3
73
74#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
75#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
76#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
77#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
78
79enum e1000_mac_type {
80 e1000_undefined = 0,
81 e1000_82575,
82 e1000_82576,
83 e1000_82580,
84 e1000_i350,
85 e1000_num_macs
86};
87
88enum e1000_media_type {
89 e1000_media_type_unknown = 0,
90 e1000_media_type_copper = 1,
91 e1000_media_type_internal_serdes = 2,
92 e1000_num_media_types
93};
94
95enum e1000_nvm_type {
96 e1000_nvm_unknown = 0,
97 e1000_nvm_none,
98 e1000_nvm_eeprom_spi,
99 e1000_nvm_flash_hw,
100 e1000_nvm_flash_sw
101};
102
103enum e1000_nvm_override {
104 e1000_nvm_override_none = 0,
105 e1000_nvm_override_spi_small,
106 e1000_nvm_override_spi_large,
107};
108
109enum e1000_phy_type {
110 e1000_phy_unknown = 0,
111 e1000_phy_none,
112 e1000_phy_m88,
113 e1000_phy_igp,
114 e1000_phy_igp_2,
115 e1000_phy_gg82563,
116 e1000_phy_igp_3,
117 e1000_phy_ife,
118 e1000_phy_82580,
119};
120
121enum e1000_bus_type {
122 e1000_bus_type_unknown = 0,
123 e1000_bus_type_pci,
124 e1000_bus_type_pcix,
125 e1000_bus_type_pci_express,
126 e1000_bus_type_reserved
127};
128
129enum e1000_bus_speed {
130 e1000_bus_speed_unknown = 0,
131 e1000_bus_speed_33,
132 e1000_bus_speed_66,
133 e1000_bus_speed_100,
134 e1000_bus_speed_120,
135 e1000_bus_speed_133,
136 e1000_bus_speed_2500,
137 e1000_bus_speed_5000,
138 e1000_bus_speed_reserved
139};
140
141enum e1000_bus_width {
142 e1000_bus_width_unknown = 0,
143 e1000_bus_width_pcie_x1,
144 e1000_bus_width_pcie_x2,
145 e1000_bus_width_pcie_x4 = 4,
146 e1000_bus_width_pcie_x8 = 8,
147 e1000_bus_width_32,
148 e1000_bus_width_64,
149 e1000_bus_width_reserved
150};
151
152enum e1000_1000t_rx_status {
153 e1000_1000t_rx_status_not_ok = 0,
154 e1000_1000t_rx_status_ok,
155 e1000_1000t_rx_status_undefined = 0xFF
156};
157
158enum e1000_rev_polarity {
159 e1000_rev_polarity_normal = 0,
160 e1000_rev_polarity_reversed,
161 e1000_rev_polarity_undefined = 0xFF
162};
163
164enum e1000_fc_mode {
165 e1000_fc_none = 0,
166 e1000_fc_rx_pause,
167 e1000_fc_tx_pause,
168 e1000_fc_full,
169 e1000_fc_default = 0xFF
170};
171
172
173struct e1000_hw_stats {
174 u64 crcerrs;
175 u64 algnerrc;
176 u64 symerrs;
177 u64 rxerrc;
178 u64 mpc;
179 u64 scc;
180 u64 ecol;
181 u64 mcc;
182 u64 latecol;
183 u64 colc;
184 u64 dc;
185 u64 tncrs;
186 u64 sec;
187 u64 cexterr;
188 u64 rlec;
189 u64 xonrxc;
190 u64 xontxc;
191 u64 xoffrxc;
192 u64 xofftxc;
193 u64 fcruc;
194 u64 prc64;
195 u64 prc127;
196 u64 prc255;
197 u64 prc511;
198 u64 prc1023;
199 u64 prc1522;
200 u64 gprc;
201 u64 bprc;
202 u64 mprc;
203 u64 gptc;
204 u64 gorc;
205 u64 gotc;
206 u64 rnbc;
207 u64 ruc;
208 u64 rfc;
209 u64 roc;
210 u64 rjc;
211 u64 mgprc;
212 u64 mgpdc;
213 u64 mgptc;
214 u64 tor;
215 u64 tot;
216 u64 tpr;
217 u64 tpt;
218 u64 ptc64;
219 u64 ptc127;
220 u64 ptc255;
221 u64 ptc511;
222 u64 ptc1023;
223 u64 ptc1522;
224 u64 mptc;
225 u64 bptc;
226 u64 tsctc;
227 u64 tsctfc;
228 u64 iac;
229 u64 icrxptc;
230 u64 icrxatc;
231 u64 ictxptc;
232 u64 ictxatc;
233 u64 ictxqec;
234 u64 ictxqmtc;
235 u64 icrxdmtc;
236 u64 icrxoc;
237 u64 cbtmpc;
238 u64 htdpmc;
239 u64 cbrdpc;
240 u64 cbrmpc;
241 u64 rpthc;
242 u64 hgptc;
243 u64 htcbdpc;
244 u64 hgorc;
245 u64 hgotc;
246 u64 lenerrs;
247 u64 scvpc;
248 u64 hrmpc;
249 u64 doosync;
250};
251
252struct e1000_phy_stats {
253 u32 idle_errors;
254 u32 receive_errors;
255};
256
257struct e1000_host_mng_dhcp_cookie {
258 u32 signature;
259 u8 status;
260 u8 reserved0;
261 u16 vlan_id;
262 u32 reserved1;
263 u16 reserved2;
264 u8 reserved3;
265 u8 checksum;
266};
267
268
269struct e1000_host_command_header {
270 u8 command_id;
271 u8 command_length;
272 u8 command_options;
273 u8 checksum;
274};
275
276#define E1000_HI_MAX_DATA_LENGTH 252
277struct e1000_host_command_info {
278 struct e1000_host_command_header command_header;
279 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
280};
281
282
283struct e1000_host_mng_command_header {
284 u8 command_id;
285 u8 checksum;
286 u16 reserved1;
287 u16 reserved2;
288 u16 command_length;
289};
290
291#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
292struct e1000_host_mng_command_info {
293 struct e1000_host_mng_command_header command_header;
294 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
295};
296
297#include "e1000_mac.h"
298#include "e1000_phy.h"
299#include "e1000_nvm.h"
300#include "e1000_mbx.h"
301
302struct e1000_mac_operations {
303 s32 (*check_for_link)(struct e1000_hw *);
304 s32 (*reset_hw)(struct e1000_hw *);
305 s32 (*init_hw)(struct e1000_hw *);
306 bool (*check_mng_mode)(struct e1000_hw *);
307 s32 (*setup_physical_interface)(struct e1000_hw *);
308 void (*rar_set)(struct e1000_hw *, u8 *, u32);
309 s32 (*read_mac_addr)(struct e1000_hw *);
310 s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);
311};
312
313struct e1000_phy_operations {
314 s32 (*acquire)(struct e1000_hw *);
315 s32 (*check_polarity)(struct e1000_hw *);
316 s32 (*check_reset_block)(struct e1000_hw *);
317 s32 (*force_speed_duplex)(struct e1000_hw *);
318 s32 (*get_cfg_done)(struct e1000_hw *hw);
319 s32 (*get_cable_length)(struct e1000_hw *);
320 s32 (*get_phy_info)(struct e1000_hw *);
321 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
322 void (*release)(struct e1000_hw *);
323 s32 (*reset)(struct e1000_hw *);
324 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
325 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
326 s32 (*write_reg)(struct e1000_hw *, u32, u16);
327};
328
329struct e1000_nvm_operations {
330 s32 (*acquire)(struct e1000_hw *);
331 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
332 void (*release)(struct e1000_hw *);
333 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
334};
335
336struct e1000_info {
337 s32 (*get_invariants)(struct e1000_hw *);
338 struct e1000_mac_operations *mac_ops;
339 struct e1000_phy_operations *phy_ops;
340 struct e1000_nvm_operations *nvm_ops;
341};
342
343extern const struct e1000_info e1000_82575_info;
344
345struct e1000_mac_info {
346 struct e1000_mac_operations ops;
347
348 u8 addr[6];
349 u8 perm_addr[6];
350
351 enum e1000_mac_type type;
352
353 u32 ledctl_default;
354 u32 ledctl_mode1;
355 u32 ledctl_mode2;
356 u32 mc_filter_type;
357 u32 txcw;
358
359 u16 mta_reg_count;
360 u16 uta_reg_count;
361
362
363 #define MAX_MTA_REG 128
364 u32 mta_shadow[MAX_MTA_REG];
365 u16 rar_entry_count;
366
367 u8 forced_speed_duplex;
368
369 bool adaptive_ifs;
370 bool arc_subsystem_valid;
371 bool asf_firmware_present;
372 bool autoneg;
373 bool autoneg_failed;
374 bool disable_hw_init_bits;
375 bool get_link_status;
376 bool ifs_params_forced;
377 bool in_ifs_mode;
378 bool report_tx_early;
379 bool serdes_has_link;
380 bool tx_pkt_filtering;
381};
382
383struct e1000_phy_info {
384 struct e1000_phy_operations ops;
385
386 enum e1000_phy_type type;
387
388 enum e1000_1000t_rx_status local_rx;
389 enum e1000_1000t_rx_status remote_rx;
390 enum e1000_ms_type ms_type;
391 enum e1000_ms_type original_ms_type;
392 enum e1000_rev_polarity cable_polarity;
393 enum e1000_smart_speed smart_speed;
394
395 u32 addr;
396 u32 id;
397 u32 reset_delay_us;
398 u32 revision;
399
400 enum e1000_media_type media_type;
401
402 u16 autoneg_advertised;
403 u16 autoneg_mask;
404 u16 cable_length;
405 u16 max_cable_length;
406 u16 min_cable_length;
407
408 u8 mdix;
409
410 bool disable_polarity_correction;
411 bool is_mdix;
412 bool polarity_correction;
413 bool reset_disable;
414 bool speed_downgraded;
415 bool autoneg_wait_to_complete;
416};
417
418struct e1000_nvm_info {
419 struct e1000_nvm_operations ops;
420
421 enum e1000_nvm_type type;
422 enum e1000_nvm_override override;
423
424 u32 flash_bank_size;
425 u32 flash_base_addr;
426
427 u16 word_size;
428 u16 delay_usec;
429 u16 address_bits;
430 u16 opcode_bits;
431 u16 page_size;
432};
433
434struct e1000_bus_info {
435 enum e1000_bus_type type;
436 enum e1000_bus_speed speed;
437 enum e1000_bus_width width;
438
439 u32 snoop;
440
441 u16 func;
442 u16 pci_cmd_word;
443};
444
445struct e1000_fc_info {
446 u32 high_water;
447 u32 low_water;
448 u16 pause_time;
449 bool send_xon;
450 bool strict_ieee;
451 enum e1000_fc_mode current_mode;
452 enum e1000_fc_mode requested_mode;
453};
454
455struct e1000_mbx_operations {
456 s32 (*init_params)(struct e1000_hw *hw);
457 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
458 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
459 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
460 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
461 s32 (*check_for_msg)(struct e1000_hw *, u16);
462 s32 (*check_for_ack)(struct e1000_hw *, u16);
463 s32 (*check_for_rst)(struct e1000_hw *, u16);
464};
465
466struct e1000_mbx_stats {
467 u32 msgs_tx;
468 u32 msgs_rx;
469
470 u32 acks;
471 u32 reqs;
472 u32 rsts;
473};
474
475struct e1000_mbx_info {
476 struct e1000_mbx_operations ops;
477 struct e1000_mbx_stats stats;
478 u32 timeout;
479 u32 usec_delay;
480 u16 size;
481};
482
483struct e1000_dev_spec_82575 {
484 bool sgmii_active;
485 bool global_device_reset;
486};
487
488struct e1000_hw {
489 void *back;
490
491 u8 __iomem *hw_addr;
492 u8 __iomem *flash_address;
493 unsigned long io_base;
494
495 struct e1000_mac_info mac;
496 struct e1000_fc_info fc;
497 struct e1000_phy_info phy;
498 struct e1000_nvm_info nvm;
499 struct e1000_bus_info bus;
500 struct e1000_mbx_info mbx;
501 struct e1000_host_mng_dhcp_cookie mng_cookie;
502
503 union {
504 struct e1000_dev_spec_82575 _82575;
505 } dev_spec;
506
507 u16 device_id;
508 u16 subsystem_vendor_id;
509 u16 subsystem_device_id;
510 u16 vendor_id;
511
512 u8 revision_id;
513};
514
515extern struct net_device *igb_get_hw_dev(struct e1000_hw *hw);
516#define hw_dbg(format, arg...) \
517 netdev_dbg(igb_get_hw_dev(hw), format, ##arg)
518
519
520s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
521s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
522#endif
523