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28#include <linux/if_ether.h>
29#include <linux/delay.h>
30
31#include "e1000_mac.h"
32#include "e1000_nvm.h"
33
34
35
36
37
38
39
40
41static void igb_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
42{
43 *eecd = *eecd | E1000_EECD_SK;
44 wr32(E1000_EECD, *eecd);
45 wrfl();
46 udelay(hw->nvm.delay_usec);
47}
48
49
50
51
52
53
54
55
56static void igb_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
57{
58 *eecd = *eecd & ~E1000_EECD_SK;
59 wr32(E1000_EECD, *eecd);
60 wrfl();
61 udelay(hw->nvm.delay_usec);
62}
63
64
65
66
67
68
69
70
71
72
73
74static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
75{
76 struct e1000_nvm_info *nvm = &hw->nvm;
77 u32 eecd = rd32(E1000_EECD);
78 u32 mask;
79
80 mask = 0x01 << (count - 1);
81 if (nvm->type == e1000_nvm_eeprom_spi)
82 eecd |= E1000_EECD_DO;
83
84 do {
85 eecd &= ~E1000_EECD_DI;
86
87 if (data & mask)
88 eecd |= E1000_EECD_DI;
89
90 wr32(E1000_EECD, eecd);
91 wrfl();
92
93 udelay(nvm->delay_usec);
94
95 igb_raise_eec_clk(hw, &eecd);
96 igb_lower_eec_clk(hw, &eecd);
97
98 mask >>= 1;
99 } while (mask);
100
101 eecd &= ~E1000_EECD_DI;
102 wr32(E1000_EECD, eecd);
103}
104
105
106
107
108
109
110
111
112
113
114
115
116static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
117{
118 u32 eecd;
119 u32 i;
120 u16 data;
121
122 eecd = rd32(E1000_EECD);
123
124 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
125 data = 0;
126
127 for (i = 0; i < count; i++) {
128 data <<= 1;
129 igb_raise_eec_clk(hw, &eecd);
130
131 eecd = rd32(E1000_EECD);
132
133 eecd &= ~E1000_EECD_DI;
134 if (eecd & E1000_EECD_DO)
135 data |= 1;
136
137 igb_lower_eec_clk(hw, &eecd);
138 }
139
140 return data;
141}
142
143
144
145
146
147
148
149
150
151static s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
152{
153 u32 attempts = 100000;
154 u32 i, reg = 0;
155 s32 ret_val = -E1000_ERR_NVM;
156
157 for (i = 0; i < attempts; i++) {
158 if (ee_reg == E1000_NVM_POLL_READ)
159 reg = rd32(E1000_EERD);
160 else
161 reg = rd32(E1000_EEWR);
162
163 if (reg & E1000_NVM_RW_REG_DONE) {
164 ret_val = 0;
165 break;
166 }
167
168 udelay(5);
169 }
170
171 return ret_val;
172}
173
174
175
176
177
178
179
180
181
182s32 igb_acquire_nvm(struct e1000_hw *hw)
183{
184 u32 eecd = rd32(E1000_EECD);
185 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
186 s32 ret_val = 0;
187
188
189 wr32(E1000_EECD, eecd | E1000_EECD_REQ);
190 eecd = rd32(E1000_EECD);
191
192 while (timeout) {
193 if (eecd & E1000_EECD_GNT)
194 break;
195 udelay(5);
196 eecd = rd32(E1000_EECD);
197 timeout--;
198 }
199
200 if (!timeout) {
201 eecd &= ~E1000_EECD_REQ;
202 wr32(E1000_EECD, eecd);
203 hw_dbg("Could not acquire NVM grant\n");
204 ret_val = -E1000_ERR_NVM;
205 }
206
207 return ret_val;
208}
209
210
211
212
213
214
215
216static void igb_standby_nvm(struct e1000_hw *hw)
217{
218 struct e1000_nvm_info *nvm = &hw->nvm;
219 u32 eecd = rd32(E1000_EECD);
220
221 if (nvm->type == e1000_nvm_eeprom_spi) {
222
223 eecd |= E1000_EECD_CS;
224 wr32(E1000_EECD, eecd);
225 wrfl();
226 udelay(nvm->delay_usec);
227 eecd &= ~E1000_EECD_CS;
228 wr32(E1000_EECD, eecd);
229 wrfl();
230 udelay(nvm->delay_usec);
231 }
232}
233
234
235
236
237
238
239
240static void e1000_stop_nvm(struct e1000_hw *hw)
241{
242 u32 eecd;
243
244 eecd = rd32(E1000_EECD);
245 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
246
247 eecd |= E1000_EECD_CS;
248 igb_lower_eec_clk(hw, &eecd);
249 }
250}
251
252
253
254
255
256
257
258void igb_release_nvm(struct e1000_hw *hw)
259{
260 u32 eecd;
261
262 e1000_stop_nvm(hw);
263
264 eecd = rd32(E1000_EECD);
265 eecd &= ~E1000_EECD_REQ;
266 wr32(E1000_EECD, eecd);
267}
268
269
270
271
272
273
274
275static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw)
276{
277 struct e1000_nvm_info *nvm = &hw->nvm;
278 u32 eecd = rd32(E1000_EECD);
279 s32 ret_val = 0;
280 u16 timeout = 0;
281 u8 spi_stat_reg;
282
283
284 if (nvm->type == e1000_nvm_eeprom_spi) {
285
286 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
287 wr32(E1000_EECD, eecd);
288 udelay(1);
289 timeout = NVM_MAX_RETRY_SPI;
290
291
292
293
294
295
296
297 while (timeout) {
298 igb_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
299 hw->nvm.opcode_bits);
300 spi_stat_reg = (u8)igb_shift_in_eec_bits(hw, 8);
301 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
302 break;
303
304 udelay(5);
305 igb_standby_nvm(hw);
306 timeout--;
307 }
308
309 if (!timeout) {
310 hw_dbg("SPI NVM Status error\n");
311 ret_val = -E1000_ERR_NVM;
312 goto out;
313 }
314 }
315
316out:
317 return ret_val;
318}
319
320
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324
325
326
327
328
329s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
330{
331 struct e1000_nvm_info *nvm = &hw->nvm;
332 u32 i, eerd = 0;
333 s32 ret_val = 0;
334
335
336
337
338
339 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
340 (words == 0)) {
341 hw_dbg("nvm parameter(s) out of bounds\n");
342 ret_val = -E1000_ERR_NVM;
343 goto out;
344 }
345
346 for (i = 0; i < words; i++) {
347 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
348 E1000_NVM_RW_REG_START;
349
350 wr32(E1000_EERD, eerd);
351 ret_val = igb_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
352 if (ret_val)
353 break;
354
355 data[i] = (rd32(E1000_EERD) >>
356 E1000_NVM_RW_REG_DATA);
357 }
358
359out:
360 return ret_val;
361}
362
363
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367
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369
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372
373
374
375s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
376{
377 struct e1000_nvm_info *nvm = &hw->nvm;
378 s32 ret_val;
379 u16 widx = 0;
380
381
382
383
384
385 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
386 (words == 0)) {
387 hw_dbg("nvm parameter(s) out of bounds\n");
388 ret_val = -E1000_ERR_NVM;
389 goto out;
390 }
391
392 ret_val = hw->nvm.ops.acquire(hw);
393 if (ret_val)
394 goto out;
395
396 msleep(10);
397
398 while (widx < words) {
399 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
400
401 ret_val = igb_ready_nvm_eeprom(hw);
402 if (ret_val)
403 goto release;
404
405 igb_standby_nvm(hw);
406
407
408 igb_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
409 nvm->opcode_bits);
410
411 igb_standby_nvm(hw);
412
413
414
415
416
417 if ((nvm->address_bits == 8) && (offset >= 128))
418 write_opcode |= NVM_A8_OPCODE_SPI;
419
420
421 igb_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
422 igb_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
423 nvm->address_bits);
424
425
426 while (widx < words) {
427 u16 word_out = data[widx];
428 word_out = (word_out >> 8) | (word_out << 8);
429 igb_shift_out_eec_bits(hw, word_out, 16);
430 widx++;
431
432 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
433 igb_standby_nvm(hw);
434 break;
435 }
436 }
437 }
438
439 msleep(10);
440release:
441 hw->nvm.ops.release(hw);
442
443out:
444 return ret_val;
445}
446
447
448
449
450
451
452
453
454
455
456s32 igb_read_part_string(struct e1000_hw *hw, u8 *part_num, u32 part_num_size)
457{
458 s32 ret_val;
459 u16 nvm_data;
460 u16 pointer;
461 u16 offset;
462 u16 length;
463
464 if (part_num == NULL) {
465 hw_dbg("PBA string buffer was null\n");
466 ret_val = E1000_ERR_INVALID_ARGUMENT;
467 goto out;
468 }
469
470 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
471 if (ret_val) {
472 hw_dbg("NVM Read Error\n");
473 goto out;
474 }
475
476 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pointer);
477 if (ret_val) {
478 hw_dbg("NVM Read Error\n");
479 goto out;
480 }
481
482
483
484
485
486
487 if (nvm_data != NVM_PBA_PTR_GUARD) {
488 hw_dbg("NVM PBA number is not stored as string\n");
489
490
491 if (part_num_size < 11) {
492 hw_dbg("PBA string buffer too small\n");
493 return E1000_ERR_NO_SPACE;
494 }
495
496
497 part_num[0] = (nvm_data >> 12) & 0xF;
498 part_num[1] = (nvm_data >> 8) & 0xF;
499 part_num[2] = (nvm_data >> 4) & 0xF;
500 part_num[3] = nvm_data & 0xF;
501 part_num[4] = (pointer >> 12) & 0xF;
502 part_num[5] = (pointer >> 8) & 0xF;
503 part_num[6] = '-';
504 part_num[7] = 0;
505 part_num[8] = (pointer >> 4) & 0xF;
506 part_num[9] = pointer & 0xF;
507
508
509 part_num[10] = '\0';
510
511
512 for (offset = 0; offset < 10; offset++) {
513 if (part_num[offset] < 0xA)
514 part_num[offset] += '0';
515 else if (part_num[offset] < 0x10)
516 part_num[offset] += 'A' - 0xA;
517 }
518
519 goto out;
520 }
521
522 ret_val = hw->nvm.ops.read(hw, pointer, 1, &length);
523 if (ret_val) {
524 hw_dbg("NVM Read Error\n");
525 goto out;
526 }
527
528 if (length == 0xFFFF || length == 0) {
529 hw_dbg("NVM PBA number section invalid length\n");
530 ret_val = E1000_ERR_NVM_PBA_SECTION;
531 goto out;
532 }
533
534 if (part_num_size < (((u32)length * 2) - 1)) {
535 hw_dbg("PBA string buffer too small\n");
536 ret_val = E1000_ERR_NO_SPACE;
537 goto out;
538 }
539
540
541 pointer++;
542 length--;
543
544 for (offset = 0; offset < length; offset++) {
545 ret_val = hw->nvm.ops.read(hw, pointer + offset, 1, &nvm_data);
546 if (ret_val) {
547 hw_dbg("NVM Read Error\n");
548 goto out;
549 }
550 part_num[offset * 2] = (u8)(nvm_data >> 8);
551 part_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
552 }
553 part_num[offset * 2] = '\0';
554
555out:
556 return ret_val;
557}
558
559
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562
563
564
565
566
567s32 igb_read_mac_addr(struct e1000_hw *hw)
568{
569 u32 rar_high;
570 u32 rar_low;
571 u16 i;
572
573 rar_high = rd32(E1000_RAH(0));
574 rar_low = rd32(E1000_RAL(0));
575
576 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
577 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
578
579 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
580 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
581
582 for (i = 0; i < ETH_ALEN; i++)
583 hw->mac.addr[i] = hw->mac.perm_addr[i];
584
585 return 0;
586}
587
588
589
590
591
592
593
594
595s32 igb_validate_nvm_checksum(struct e1000_hw *hw)
596{
597 s32 ret_val = 0;
598 u16 checksum = 0;
599 u16 i, nvm_data;
600
601 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
602 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
603 if (ret_val) {
604 hw_dbg("NVM Read Error\n");
605 goto out;
606 }
607 checksum += nvm_data;
608 }
609
610 if (checksum != (u16) NVM_SUM) {
611 hw_dbg("NVM Checksum Invalid\n");
612 ret_val = -E1000_ERR_NVM;
613 goto out;
614 }
615
616out:
617 return ret_val;
618}
619
620
621
622
623
624
625
626
627
628s32 igb_update_nvm_checksum(struct e1000_hw *hw)
629{
630 s32 ret_val;
631 u16 checksum = 0;
632 u16 i, nvm_data;
633
634 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
635 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
636 if (ret_val) {
637 hw_dbg("NVM Read Error while updating checksum.\n");
638 goto out;
639 }
640 checksum += nvm_data;
641 }
642 checksum = (u16) NVM_SUM - checksum;
643 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
644 if (ret_val)
645 hw_dbg("NVM Write Error while updating checksum.\n");
646
647out:
648 return ret_val;
649}
650
651