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29#define DRV_NAME "starfire"
30#define DRV_VERSION "2.1"
31#define DRV_RELDATE "July 6, 2008"
32
33#include <linux/module.h>
34#include <linux/kernel.h>
35#include <linux/pci.h>
36#include <linux/netdevice.h>
37#include <linux/etherdevice.h>
38#include <linux/init.h>
39#include <linux/delay.h>
40#include <linux/crc32.h>
41#include <linux/ethtool.h>
42#include <linux/mii.h>
43#include <linux/if_vlan.h>
44#include <linux/mm.h>
45#include <linux/firmware.h>
46#include <asm/processor.h>
47#include <asm/uaccess.h>
48#include <asm/io.h>
49
50
51
52
53
54#define HAS_BROKEN_FIRMWARE
55
56
57
58
59#ifdef HAS_BROKEN_FIRMWARE
60#define PADDING_MASK 3
61#endif
62
63
64
65
66#define ZEROCOPY
67
68#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
69#define VLAN_SUPPORT
70#endif
71
72
73
74
75
76static int intr_latency;
77static int small_frames;
78
79static int debug = 1;
80static int max_interrupt_work = 20;
81static int mtu;
82
83
84static const int multicast_filter_limit = 512;
85
86static int enable_hw_cksum = 1;
87
88#define PKT_BUF_SZ 1536
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102
103#if defined(__ia64__) || defined(__alpha__) || defined(__sparc__)
104static int rx_copybreak = PKT_BUF_SZ;
105#else
106static int rx_copybreak ;
107#endif
108
109
110#ifdef __sparc__
111#define DMA_BURST_SIZE 64
112#else
113#define DMA_BURST_SIZE 128
114#endif
115
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119
120
121#define MAX_UNITS 8
122static int options[MAX_UNITS] = {0, };
123static int full_duplex[MAX_UNITS] = {0, };
124
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128
129
130#define RX_RING_SIZE 256
131#define TX_RING_SIZE 32
132
133#define DONE_Q_SIZE 1024
134
135#define QUEUE_ALIGN 256
136
137#if RX_RING_SIZE > 256
138#define RX_Q_ENTRIES Rx2048QEntries
139#else
140#define RX_Q_ENTRIES Rx256QEntries
141#endif
142
143
144
145#define TX_TIMEOUT (2 * HZ)
146
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149
150
151#if (defined(__i386__) && defined(CONFIG_HIGHMEM64G)) || defined(__x86_64__) || defined (__ia64__) || defined(__alpha__) || (defined(CONFIG_MIPS) && ((defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) || defined(CONFIG_64BIT))) || (defined(__powerpc64__) || defined(CONFIG_PHYS_64BIT))
152
153#define ADDR_64BITS
154#define netdrv_addr_t __le64
155#define cpu_to_dma(x) cpu_to_le64(x)
156#define dma_to_cpu(x) le64_to_cpu(x)
157#define RX_DESC_Q_ADDR_SIZE RxDescQAddr64bit
158#define TX_DESC_Q_ADDR_SIZE TxDescQAddr64bit
159#define RX_COMPL_Q_ADDR_SIZE RxComplQAddr64bit
160#define TX_COMPL_Q_ADDR_SIZE TxComplQAddr64bit
161#define RX_DESC_ADDR_SIZE RxDescAddr64bit
162#else
163#define netdrv_addr_t __le32
164#define cpu_to_dma(x) cpu_to_le32(x)
165#define dma_to_cpu(x) le32_to_cpu(x)
166#define RX_DESC_Q_ADDR_SIZE RxDescQAddr32bit
167#define TX_DESC_Q_ADDR_SIZE TxDescQAddr32bit
168#define RX_COMPL_Q_ADDR_SIZE RxComplQAddr32bit
169#define TX_COMPL_Q_ADDR_SIZE TxComplQAddr32bit
170#define RX_DESC_ADDR_SIZE RxDescAddr32bit
171#endif
172
173#define skb_first_frag_len(skb) skb_headlen(skb)
174#define skb_num_frags(skb) (skb_shinfo(skb)->nr_frags + 1)
175
176
177#define FIRMWARE_RX "adaptec/starfire_rx.bin"
178#define FIRMWARE_TX "adaptec/starfire_tx.bin"
179
180
181static const char version[] __devinitconst =
182KERN_INFO "starfire.c:v1.03 7/26/2000 Written by Donald Becker <becker@scyld.com>\n"
183" (unofficial 2.2/2.4 kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n";
184
185MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
186MODULE_DESCRIPTION("Adaptec Starfire Ethernet driver");
187MODULE_LICENSE("GPL");
188MODULE_VERSION(DRV_VERSION);
189MODULE_FIRMWARE(FIRMWARE_RX);
190MODULE_FIRMWARE(FIRMWARE_TX);
191
192module_param(max_interrupt_work, int, 0);
193module_param(mtu, int, 0);
194module_param(debug, int, 0);
195module_param(rx_copybreak, int, 0);
196module_param(intr_latency, int, 0);
197module_param(small_frames, int, 0);
198module_param_array(options, int, NULL, 0);
199module_param_array(full_duplex, int, NULL, 0);
200module_param(enable_hw_cksum, int, 0);
201MODULE_PARM_DESC(max_interrupt_work, "Maximum events handled per interrupt");
202MODULE_PARM_DESC(mtu, "MTU (all boards)");
203MODULE_PARM_DESC(debug, "Debug level (0-6)");
204MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
205MODULE_PARM_DESC(intr_latency, "Maximum interrupt latency, in microseconds");
206MODULE_PARM_DESC(small_frames, "Maximum size of receive frames that bypass interrupt latency (0,64,128,256,512)");
207MODULE_PARM_DESC(options, "Deprecated: Bits 0-3: media type, bit 17: full duplex");
208MODULE_PARM_DESC(full_duplex, "Deprecated: Forced full-duplex setting (0/1)");
209MODULE_PARM_DESC(enable_hw_cksum, "Enable/disable hardware cksum support (0/1)");
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298enum chip_capability_flags {CanHaveMII=1, };
299
300enum chipset {
301 CH_6915 = 0,
302};
303
304static DEFINE_PCI_DEVICE_TABLE(starfire_pci_tbl) = {
305 { PCI_VDEVICE(ADAPTEC, 0x6915), CH_6915 },
306 { 0, }
307};
308MODULE_DEVICE_TABLE(pci, starfire_pci_tbl);
309
310
311static const struct chip_info {
312 const char *name;
313 int drv_flags;
314} netdrv_tbl[] __devinitdata = {
315 { "Adaptec Starfire 6915", CanHaveMII },
316};
317
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324
325
326
327enum register_offsets {
328 PCIDeviceConfig=0x50040, GenCtrl=0x50070, IntrTimerCtrl=0x50074,
329 IntrClear=0x50080, IntrStatus=0x50084, IntrEnable=0x50088,
330 MIICtrl=0x52000, TxStationAddr=0x50120, EEPROMCtrl=0x51000,
331 GPIOCtrl=0x5008C, TxDescCtrl=0x50090,
332 TxRingPtr=0x50098, HiPriTxRingPtr=0x50094,
333 TxRingHiAddr=0x5009C,
334 TxProducerIdx=0x500A0, TxConsumerIdx=0x500A4,
335 TxThreshold=0x500B0,
336 CompletionHiAddr=0x500B4, TxCompletionAddr=0x500B8,
337 RxCompletionAddr=0x500BC, RxCompletionQ2Addr=0x500C0,
338 CompletionQConsumerIdx=0x500C4, RxDMACtrl=0x500D0,
339 RxDescQCtrl=0x500D4, RxDescQHiAddr=0x500DC, RxDescQAddr=0x500E0,
340 RxDescQIdx=0x500E8, RxDMAStatus=0x500F0, RxFilterMode=0x500F4,
341 TxMode=0x55000, VlanType=0x55064,
342 PerfFilterTable=0x56000, HashTable=0x56100,
343 TxGfpMem=0x58000, RxGfpMem=0x5a000,
344};
345
346
347
348
349
350
351enum intr_status_bits {
352 IntrLinkChange=0xf0000000, IntrStatsMax=0x08000000,
353 IntrAbnormalSummary=0x02000000, IntrGeneralTimer=0x01000000,
354 IntrSoftware=0x800000, IntrRxComplQ1Low=0x400000,
355 IntrTxComplQLow=0x200000, IntrPCI=0x100000,
356 IntrDMAErr=0x080000, IntrTxDataLow=0x040000,
357 IntrRxComplQ2Low=0x020000, IntrRxDescQ1Low=0x010000,
358 IntrNormalSummary=0x8000, IntrTxDone=0x4000,
359 IntrTxDMADone=0x2000, IntrTxEmpty=0x1000,
360 IntrEarlyRxQ2=0x0800, IntrEarlyRxQ1=0x0400,
361 IntrRxQ2Done=0x0200, IntrRxQ1Done=0x0100,
362 IntrRxGFPDead=0x80, IntrRxDescQ2Low=0x40,
363 IntrNoTxCsum=0x20, IntrTxBadID=0x10,
364 IntrHiPriTxBadID=0x08, IntrRxGfp=0x04,
365 IntrTxGfp=0x02, IntrPCIPad=0x01,
366
367 IntrRxDone=IntrRxQ2Done | IntrRxQ1Done,
368 IntrRxEmpty=IntrRxDescQ1Low | IntrRxDescQ2Low,
369 IntrNormalMask=0xff00, IntrAbnormalMask=0x3ff00fe,
370};
371
372
373enum rx_mode_bits {
374 AcceptBroadcast=0x04, AcceptAllMulticast=0x02, AcceptAll=0x01,
375 AcceptMulticast=0x10, PerfectFilter=0x40, HashFilter=0x30,
376 PerfectFilterVlan=0x80, MinVLANPrio=0xE000, VlanMode=0x0200,
377 WakeupOnGFP=0x0800,
378};
379
380
381enum tx_mode_bits {
382 MiiSoftReset=0x8000, MIILoopback=0x4000,
383 TxFlowEnable=0x0800, RxFlowEnable=0x0400,
384 PadEnable=0x04, FullDuplex=0x02, HugeFrame=0x01,
385};
386
387
388enum tx_ctrl_bits {
389 TxDescSpaceUnlim=0x00, TxDescSpace32=0x10, TxDescSpace64=0x20,
390 TxDescSpace128=0x30, TxDescSpace256=0x40,
391 TxDescType0=0x00, TxDescType1=0x01, TxDescType2=0x02,
392 TxDescType3=0x03, TxDescType4=0x04,
393 TxNoDMACompletion=0x08,
394 TxDescQAddr64bit=0x80, TxDescQAddr32bit=0,
395 TxHiPriFIFOThreshShift=24, TxPadLenShift=16,
396 TxDMABurstSizeShift=8,
397};
398
399
400enum rx_ctrl_bits {
401 RxBufferLenShift=16, RxMinDescrThreshShift=0,
402 RxPrefetchMode=0x8000, RxVariableQ=0x2000,
403 Rx2048QEntries=0x4000, Rx256QEntries=0,
404 RxDescAddr64bit=0x1000, RxDescAddr32bit=0,
405 RxDescQAddr64bit=0x0100, RxDescQAddr32bit=0,
406 RxDescSpace4=0x000, RxDescSpace8=0x100,
407 RxDescSpace16=0x200, RxDescSpace32=0x300,
408 RxDescSpace64=0x400, RxDescSpace128=0x500,
409 RxConsumerWrEn=0x80,
410};
411
412
413enum rx_dmactrl_bits {
414 RxReportBadFrames=0x80000000, RxDMAShortFrames=0x40000000,
415 RxDMABadFrames=0x20000000, RxDMACrcErrorFrames=0x10000000,
416 RxDMAControlFrame=0x08000000, RxDMAPauseFrame=0x04000000,
417 RxChecksumIgnore=0, RxChecksumRejectTCPUDP=0x02000000,
418 RxChecksumRejectTCPOnly=0x01000000,
419 RxCompletionQ2Enable=0x800000,
420 RxDMAQ2Disable=0, RxDMAQ2FPOnly=0x100000,
421 RxDMAQ2SmallPkt=0x200000, RxDMAQ2HighPrio=0x300000,
422 RxDMAQ2NonIP=0x400000,
423 RxUseBackupQueue=0x080000, RxDMACRC=0x040000,
424 RxEarlyIntThreshShift=12, RxHighPrioThreshShift=8,
425 RxBurstSizeShift=0,
426};
427
428
429enum rx_compl_bits {
430 RxComplQAddr64bit=0x80, RxComplQAddr32bit=0,
431 RxComplProducerWrEn=0x40,
432 RxComplType0=0x00, RxComplType1=0x10,
433 RxComplType2=0x20, RxComplType3=0x30,
434 RxComplThreshShift=0,
435};
436
437
438enum tx_compl_bits {
439 TxComplQAddr64bit=0x80, TxComplQAddr32bit=0,
440 TxComplProducerWrEn=0x40,
441 TxComplIntrStatus=0x20,
442 CommonQueueMode=0x10,
443 TxComplThreshShift=0,
444};
445
446
447enum gen_ctrl_bits {
448 RxEnable=0x05, TxEnable=0x0a,
449 RxGFPEnable=0x10, TxGFPEnable=0x20,
450};
451
452
453enum intr_ctrl_bits {
454 Timer10X=0x800, EnableIntrMasking=0x60, SmallFrameBypass=0x100,
455 SmallFrame64=0, SmallFrame128=0x200, SmallFrame256=0x400, SmallFrame512=0x600,
456 IntrLatencyMask=0x1f,
457};
458
459
460struct starfire_rx_desc {
461 netdrv_addr_t rxaddr;
462};
463enum rx_desc_bits {
464 RxDescValid=1, RxDescEndRing=2,
465};
466
467
468struct short_rx_done_desc {
469 __le32 status;
470};
471struct basic_rx_done_desc {
472 __le32 status;
473 __le16 vlanid;
474 __le16 status2;
475};
476struct csum_rx_done_desc {
477 __le32 status;
478 __le16 csum;
479 __le16 status2;
480};
481struct full_rx_done_desc {
482 __le32 status;
483 __le16 status3;
484 __le16 status2;
485 __le16 vlanid;
486 __le16 csum;
487 __le32 timestamp;
488};
489
490#ifdef VLAN_SUPPORT
491typedef struct full_rx_done_desc rx_done_desc;
492#define RxComplType RxComplType3
493#else
494typedef struct csum_rx_done_desc rx_done_desc;
495#define RxComplType RxComplType2
496#endif
497
498enum rx_done_bits {
499 RxOK=0x20000000, RxFIFOErr=0x10000000, RxBufQ2=0x08000000,
500};
501
502
503struct starfire_tx_desc_1 {
504 __le32 status;
505 __le32 addr;
506};
507
508
509struct starfire_tx_desc_2 {
510 __le32 status;
511 __le32 reserved;
512 __le64 addr;
513};
514
515#ifdef ADDR_64BITS
516typedef struct starfire_tx_desc_2 starfire_tx_desc;
517#define TX_DESC_TYPE TxDescType2
518#else
519typedef struct starfire_tx_desc_1 starfire_tx_desc;
520#define TX_DESC_TYPE TxDescType1
521#endif
522#define TX_DESC_SPACING TxDescSpaceUnlim
523
524enum tx_desc_bits {
525 TxDescID=0xB0000000,
526 TxCRCEn=0x01000000, TxDescIntr=0x08000000,
527 TxRingWrap=0x04000000, TxCalTCP=0x02000000,
528};
529struct tx_done_desc {
530 __le32 status;
531#if 0
532 __le32 intrstatus;
533#endif
534};
535
536struct rx_ring_info {
537 struct sk_buff *skb;
538 dma_addr_t mapping;
539};
540struct tx_ring_info {
541 struct sk_buff *skb;
542 dma_addr_t mapping;
543 unsigned int used_slots;
544};
545
546#define PHY_CNT 2
547struct netdev_private {
548
549 struct starfire_rx_desc *rx_ring;
550 starfire_tx_desc *tx_ring;
551 dma_addr_t rx_ring_dma;
552 dma_addr_t tx_ring_dma;
553
554 struct rx_ring_info rx_info[RX_RING_SIZE];
555 struct tx_ring_info tx_info[TX_RING_SIZE];
556
557 rx_done_desc *rx_done_q;
558 dma_addr_t rx_done_q_dma;
559 unsigned int rx_done;
560 struct tx_done_desc *tx_done_q;
561 dma_addr_t tx_done_q_dma;
562 unsigned int tx_done;
563 struct napi_struct napi;
564 struct net_device *dev;
565 struct pci_dev *pci_dev;
566#ifdef VLAN_SUPPORT
567 struct vlan_group *vlgrp;
568#endif
569 void *queue_mem;
570 dma_addr_t queue_mem_dma;
571 size_t queue_mem_size;
572
573
574 spinlock_t lock;
575 unsigned int cur_rx, dirty_rx;
576 unsigned int cur_tx, dirty_tx, reap_tx;
577 unsigned int rx_buf_sz;
578
579 int speed100;
580 u32 tx_mode;
581 u32 intr_timer_ctrl;
582 u8 tx_threshold;
583
584 struct mii_if_info mii_if;
585 int phy_cnt;
586 unsigned char phys[PHY_CNT];
587 void __iomem *base;
588};
589
590
591static int mdio_read(struct net_device *dev, int phy_id, int location);
592static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
593static int netdev_open(struct net_device *dev);
594static void check_duplex(struct net_device *dev);
595static void tx_timeout(struct net_device *dev);
596static void init_ring(struct net_device *dev);
597static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
598static irqreturn_t intr_handler(int irq, void *dev_instance);
599static void netdev_error(struct net_device *dev, int intr_status);
600static int __netdev_rx(struct net_device *dev, int *quota);
601static int netdev_poll(struct napi_struct *napi, int budget);
602static void refill_rx_ring(struct net_device *dev);
603static void netdev_error(struct net_device *dev, int intr_status);
604static void set_rx_mode(struct net_device *dev);
605static struct net_device_stats *get_stats(struct net_device *dev);
606static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
607static int netdev_close(struct net_device *dev);
608static void netdev_media_change(struct net_device *dev);
609static const struct ethtool_ops ethtool_ops;
610
611
612#ifdef VLAN_SUPPORT
613static void netdev_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
614{
615 struct netdev_private *np = netdev_priv(dev);
616
617 spin_lock(&np->lock);
618 if (debug > 2)
619 printk("%s: Setting vlgrp to %p\n", dev->name, grp);
620 np->vlgrp = grp;
621 set_rx_mode(dev);
622 spin_unlock(&np->lock);
623}
624
625static void netdev_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
626{
627 struct netdev_private *np = netdev_priv(dev);
628
629 spin_lock(&np->lock);
630 if (debug > 1)
631 printk("%s: Adding vlanid %d to vlan filter\n", dev->name, vid);
632 set_rx_mode(dev);
633 spin_unlock(&np->lock);
634}
635
636static void netdev_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
637{
638 struct netdev_private *np = netdev_priv(dev);
639
640 spin_lock(&np->lock);
641 if (debug > 1)
642 printk("%s: removing vlanid %d from vlan filter\n", dev->name, vid);
643 vlan_group_set_device(np->vlgrp, vid, NULL);
644 set_rx_mode(dev);
645 spin_unlock(&np->lock);
646}
647#endif
648
649
650static const struct net_device_ops netdev_ops = {
651 .ndo_open = netdev_open,
652 .ndo_stop = netdev_close,
653 .ndo_start_xmit = start_tx,
654 .ndo_tx_timeout = tx_timeout,
655 .ndo_get_stats = get_stats,
656 .ndo_set_multicast_list = &set_rx_mode,
657 .ndo_do_ioctl = netdev_ioctl,
658 .ndo_change_mtu = eth_change_mtu,
659 .ndo_set_mac_address = eth_mac_addr,
660 .ndo_validate_addr = eth_validate_addr,
661#ifdef VLAN_SUPPORT
662 .ndo_vlan_rx_register = netdev_vlan_rx_register,
663 .ndo_vlan_rx_add_vid = netdev_vlan_rx_add_vid,
664 .ndo_vlan_rx_kill_vid = netdev_vlan_rx_kill_vid,
665#endif
666};
667
668static int __devinit starfire_init_one(struct pci_dev *pdev,
669 const struct pci_device_id *ent)
670{
671 struct netdev_private *np;
672 int i, irq, option, chip_idx = ent->driver_data;
673 struct net_device *dev;
674 static int card_idx = -1;
675 long ioaddr;
676 void __iomem *base;
677 int drv_flags, io_size;
678 int boguscnt;
679
680
681#ifndef MODULE
682 static int printed_version;
683 if (!printed_version++)
684 printk(version);
685#endif
686
687 card_idx++;
688
689 if (pci_enable_device (pdev))
690 return -EIO;
691
692 ioaddr = pci_resource_start(pdev, 0);
693 io_size = pci_resource_len(pdev, 0);
694 if (!ioaddr || ((pci_resource_flags(pdev, 0) & IORESOURCE_MEM) == 0)) {
695 printk(KERN_ERR DRV_NAME " %d: no PCI MEM resources, aborting\n", card_idx);
696 return -ENODEV;
697 }
698
699 dev = alloc_etherdev(sizeof(*np));
700 if (!dev) {
701 printk(KERN_ERR DRV_NAME " %d: cannot alloc etherdev, aborting\n", card_idx);
702 return -ENOMEM;
703 }
704 SET_NETDEV_DEV(dev, &pdev->dev);
705
706 irq = pdev->irq;
707
708 if (pci_request_regions (pdev, DRV_NAME)) {
709 printk(KERN_ERR DRV_NAME " %d: cannot reserve PCI resources, aborting\n", card_idx);
710 goto err_out_free_netdev;
711 }
712
713 base = ioremap(ioaddr, io_size);
714 if (!base) {
715 printk(KERN_ERR DRV_NAME " %d: cannot remap %#x @ %#lx, aborting\n",
716 card_idx, io_size, ioaddr);
717 goto err_out_free_res;
718 }
719
720 pci_set_master(pdev);
721
722
723 pci_try_set_mwi(pdev);
724
725#ifdef ZEROCOPY
726
727 if (enable_hw_cksum)
728 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
729#endif
730
731#ifdef VLAN_SUPPORT
732 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER;
733#endif
734#ifdef ADDR_64BITS
735 dev->features |= NETIF_F_HIGHDMA;
736#endif
737
738
739 for (i = 0; i < 6; i++)
740 dev->dev_addr[i] = readb(base + EEPROMCtrl + 20 - i);
741
742#if ! defined(final_version)
743 if (debug > 4)
744 for (i = 0; i < 0x20; i++)
745 printk("%2.2x%s",
746 (unsigned int)readb(base + EEPROMCtrl + i),
747 i % 16 != 15 ? " " : "\n");
748#endif
749
750
751 writel(MiiSoftReset, base + TxMode);
752 udelay(1000);
753 writel(0, base + TxMode);
754
755
756 writel(1, base + PCIDeviceConfig);
757 boguscnt = 1000;
758 while (--boguscnt > 0) {
759 udelay(10);
760 if ((readl(base + PCIDeviceConfig) & 1) == 0)
761 break;
762 }
763 if (boguscnt == 0)
764 printk("%s: chipset reset never completed!\n", dev->name);
765
766 udelay(1000);
767
768 dev->base_addr = (unsigned long)base;
769 dev->irq = irq;
770
771 np = netdev_priv(dev);
772 np->dev = dev;
773 np->base = base;
774 spin_lock_init(&np->lock);
775 pci_set_drvdata(pdev, dev);
776
777 np->pci_dev = pdev;
778
779 np->mii_if.dev = dev;
780 np->mii_if.mdio_read = mdio_read;
781 np->mii_if.mdio_write = mdio_write;
782 np->mii_if.phy_id_mask = 0x1f;
783 np->mii_if.reg_num_mask = 0x1f;
784
785 drv_flags = netdrv_tbl[chip_idx].drv_flags;
786
787 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
788 if (dev->mem_start)
789 option = dev->mem_start;
790
791
792 if (option & 0x200)
793 np->mii_if.full_duplex = 1;
794
795 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
796 np->mii_if.full_duplex = 1;
797
798 if (np->mii_if.full_duplex)
799 np->mii_if.force_media = 1;
800 else
801 np->mii_if.force_media = 0;
802 np->speed100 = 1;
803
804
805 np->intr_timer_ctrl = (((intr_latency * 10) / 1024) & IntrLatencyMask) |
806 Timer10X | EnableIntrMasking;
807
808 if (small_frames > 0) {
809 np->intr_timer_ctrl |= SmallFrameBypass;
810 switch (small_frames) {
811 case 1 ... 64:
812 np->intr_timer_ctrl |= SmallFrame64;
813 break;
814 case 65 ... 128:
815 np->intr_timer_ctrl |= SmallFrame128;
816 break;
817 case 129 ... 256:
818 np->intr_timer_ctrl |= SmallFrame256;
819 break;
820 default:
821 np->intr_timer_ctrl |= SmallFrame512;
822 if (small_frames > 512)
823 printk("Adjusting small_frames down to 512\n");
824 break;
825 }
826 }
827
828 dev->netdev_ops = &netdev_ops;
829 dev->watchdog_timeo = TX_TIMEOUT;
830 SET_ETHTOOL_OPS(dev, ðtool_ops);
831
832 netif_napi_add(dev, &np->napi, netdev_poll, max_interrupt_work);
833
834 if (mtu)
835 dev->mtu = mtu;
836
837 if (register_netdev(dev))
838 goto err_out_cleardev;
839
840 printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n",
841 dev->name, netdrv_tbl[chip_idx].name, base,
842 dev->dev_addr, irq);
843
844 if (drv_flags & CanHaveMII) {
845 int phy, phy_idx = 0;
846 int mii_status;
847 for (phy = 0; phy < 32 && phy_idx < PHY_CNT; phy++) {
848 mdio_write(dev, phy, MII_BMCR, BMCR_RESET);
849 mdelay(100);
850 boguscnt = 1000;
851 while (--boguscnt > 0)
852 if ((mdio_read(dev, phy, MII_BMCR) & BMCR_RESET) == 0)
853 break;
854 if (boguscnt == 0) {
855 printk("%s: PHY#%d reset never completed!\n", dev->name, phy);
856 continue;
857 }
858 mii_status = mdio_read(dev, phy, MII_BMSR);
859 if (mii_status != 0) {
860 np->phys[phy_idx++] = phy;
861 np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
862 printk(KERN_INFO "%s: MII PHY found at address %d, status "
863 "%#4.4x advertising %#4.4x.\n",
864 dev->name, phy, mii_status, np->mii_if.advertising);
865
866 break;
867 }
868 }
869 np->phy_cnt = phy_idx;
870 if (np->phy_cnt > 0)
871 np->mii_if.phy_id = np->phys[0];
872 else
873 memset(&np->mii_if, 0, sizeof(np->mii_if));
874 }
875
876 printk(KERN_INFO "%s: scatter-gather and hardware TCP cksumming %s.\n",
877 dev->name, enable_hw_cksum ? "enabled" : "disabled");
878 return 0;
879
880err_out_cleardev:
881 pci_set_drvdata(pdev, NULL);
882 iounmap(base);
883err_out_free_res:
884 pci_release_regions (pdev);
885err_out_free_netdev:
886 free_netdev(dev);
887 return -ENODEV;
888}
889
890
891
892static int mdio_read(struct net_device *dev, int phy_id, int location)
893{
894 struct netdev_private *np = netdev_priv(dev);
895 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
896 int result, boguscnt=1000;
897
898 do {
899 result = readl(mdio_addr);
900 } while ((result & 0xC0000000) != 0x80000000 && --boguscnt > 0);
901 if (boguscnt == 0)
902 return 0;
903 if ((result & 0xffff) == 0xffff)
904 return 0;
905 return result & 0xffff;
906}
907
908
909static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
910{
911 struct netdev_private *np = netdev_priv(dev);
912 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
913 writel(value, mdio_addr);
914
915}
916
917
918static int netdev_open(struct net_device *dev)
919{
920 const struct firmware *fw_rx, *fw_tx;
921 const __be32 *fw_rx_data, *fw_tx_data;
922 struct netdev_private *np = netdev_priv(dev);
923 void __iomem *ioaddr = np->base;
924 int i, retval;
925 size_t tx_size, rx_size;
926 size_t tx_done_q_size, rx_done_q_size, tx_ring_size, rx_ring_size;
927
928
929
930 retval = request_irq(dev->irq, intr_handler, IRQF_SHARED, dev->name, dev);
931 if (retval)
932 return retval;
933
934
935 writel(0, ioaddr + GenCtrl);
936 writel(1, ioaddr + PCIDeviceConfig);
937 if (debug > 1)
938 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
939 dev->name, dev->irq);
940
941
942 if (!np->queue_mem) {
943 tx_done_q_size = ((sizeof(struct tx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
944 rx_done_q_size = ((sizeof(rx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
945 tx_ring_size = ((sizeof(starfire_tx_desc) * TX_RING_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
946 rx_ring_size = sizeof(struct starfire_rx_desc) * RX_RING_SIZE;
947 np->queue_mem_size = tx_done_q_size + rx_done_q_size + tx_ring_size + rx_ring_size;
948 np->queue_mem = pci_alloc_consistent(np->pci_dev, np->queue_mem_size, &np->queue_mem_dma);
949 if (np->queue_mem == NULL) {
950 free_irq(dev->irq, dev);
951 return -ENOMEM;
952 }
953
954 np->tx_done_q = np->queue_mem;
955 np->tx_done_q_dma = np->queue_mem_dma;
956 np->rx_done_q = (void *) np->tx_done_q + tx_done_q_size;
957 np->rx_done_q_dma = np->tx_done_q_dma + tx_done_q_size;
958 np->tx_ring = (void *) np->rx_done_q + rx_done_q_size;
959 np->tx_ring_dma = np->rx_done_q_dma + rx_done_q_size;
960 np->rx_ring = (void *) np->tx_ring + tx_ring_size;
961 np->rx_ring_dma = np->tx_ring_dma + tx_ring_size;
962 }
963
964
965 netif_carrier_off(dev);
966 init_ring(dev);
967
968 writel((np->rx_buf_sz << RxBufferLenShift) |
969 (0 << RxMinDescrThreshShift) |
970 RxPrefetchMode | RxVariableQ |
971 RX_Q_ENTRIES |
972 RX_DESC_Q_ADDR_SIZE | RX_DESC_ADDR_SIZE |
973 RxDescSpace4,
974 ioaddr + RxDescQCtrl);
975
976
977 writel(RxChecksumIgnore |
978 (0 << RxEarlyIntThreshShift) |
979 (6 << RxHighPrioThreshShift) |
980 ((DMA_BURST_SIZE / 32) << RxBurstSizeShift),
981 ioaddr + RxDMACtrl);
982
983
984 writel((2 << TxHiPriFIFOThreshShift) |
985 (0 << TxPadLenShift) |
986 ((DMA_BURST_SIZE / 32) << TxDMABurstSizeShift) |
987 TX_DESC_Q_ADDR_SIZE |
988 TX_DESC_SPACING | TX_DESC_TYPE,
989 ioaddr + TxDescCtrl);
990
991 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + RxDescQHiAddr);
992 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + TxRingHiAddr);
993 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + CompletionHiAddr);
994 writel(np->rx_ring_dma, ioaddr + RxDescQAddr);
995 writel(np->tx_ring_dma, ioaddr + TxRingPtr);
996
997 writel(np->tx_done_q_dma, ioaddr + TxCompletionAddr);
998 writel(np->rx_done_q_dma |
999 RxComplType |
1000 (0 << RxComplThreshShift),
1001 ioaddr + RxCompletionAddr);
1002
1003 if (debug > 1)
1004 printk(KERN_DEBUG "%s: Filling in the station address.\n", dev->name);
1005
1006
1007 for (i = 0; i < 6; i++)
1008 writeb(dev->dev_addr[i], ioaddr + TxStationAddr + 5 - i);
1009
1010
1011 writew(0, ioaddr + PerfFilterTable);
1012 writew(0, ioaddr + PerfFilterTable + 4);
1013 writew(0, ioaddr + PerfFilterTable + 8);
1014 for (i = 1; i < 16; i++) {
1015 __be16 *eaddrs = (__be16 *)dev->dev_addr;
1016 void __iomem *setup_frm = ioaddr + PerfFilterTable + i * 16;
1017 writew(be16_to_cpu(eaddrs[2]), setup_frm); setup_frm += 4;
1018 writew(be16_to_cpu(eaddrs[1]), setup_frm); setup_frm += 4;
1019 writew(be16_to_cpu(eaddrs[0]), setup_frm); setup_frm += 8;
1020 }
1021
1022
1023
1024 np->tx_mode = TxFlowEnable|RxFlowEnable|PadEnable;
1025 writel(MiiSoftReset | np->tx_mode, ioaddr + TxMode);
1026 udelay(1000);
1027 writel(np->tx_mode, ioaddr + TxMode);
1028 np->tx_threshold = 4;
1029 writel(np->tx_threshold, ioaddr + TxThreshold);
1030
1031 writel(np->intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1032
1033 napi_enable(&np->napi);
1034
1035 netif_start_queue(dev);
1036
1037 if (debug > 1)
1038 printk(KERN_DEBUG "%s: Setting the Rx and Tx modes.\n", dev->name);
1039 set_rx_mode(dev);
1040
1041 np->mii_if.advertising = mdio_read(dev, np->phys[0], MII_ADVERTISE);
1042 check_duplex(dev);
1043
1044
1045 writel(0x0f00ff00, ioaddr + GPIOCtrl);
1046
1047
1048 writel(IntrRxDone | IntrRxEmpty | IntrDMAErr |
1049 IntrTxDMADone | IntrStatsMax | IntrLinkChange |
1050 IntrRxGFPDead | IntrNoTxCsum | IntrTxBadID,
1051 ioaddr + IntrEnable);
1052
1053 writel(0x00800000 | readl(ioaddr + PCIDeviceConfig),
1054 ioaddr + PCIDeviceConfig);
1055
1056#ifdef VLAN_SUPPORT
1057
1058 writel(ETH_P_8021Q, ioaddr + VlanType);
1059#endif
1060
1061 retval = request_firmware(&fw_rx, FIRMWARE_RX, &np->pci_dev->dev);
1062 if (retval) {
1063 printk(KERN_ERR "starfire: Failed to load firmware \"%s\"\n",
1064 FIRMWARE_RX);
1065 goto out_init;
1066 }
1067 if (fw_rx->size % 4) {
1068 printk(KERN_ERR "starfire: bogus length %zu in \"%s\"\n",
1069 fw_rx->size, FIRMWARE_RX);
1070 retval = -EINVAL;
1071 goto out_rx;
1072 }
1073 retval = request_firmware(&fw_tx, FIRMWARE_TX, &np->pci_dev->dev);
1074 if (retval) {
1075 printk(KERN_ERR "starfire: Failed to load firmware \"%s\"\n",
1076 FIRMWARE_TX);
1077 goto out_rx;
1078 }
1079 if (fw_tx->size % 4) {
1080 printk(KERN_ERR "starfire: bogus length %zu in \"%s\"\n",
1081 fw_tx->size, FIRMWARE_TX);
1082 retval = -EINVAL;
1083 goto out_tx;
1084 }
1085 fw_rx_data = (const __be32 *)&fw_rx->data[0];
1086 fw_tx_data = (const __be32 *)&fw_tx->data[0];
1087 rx_size = fw_rx->size / 4;
1088 tx_size = fw_tx->size / 4;
1089
1090
1091 for (i = 0; i < rx_size; i++)
1092 writel(be32_to_cpup(&fw_rx_data[i]), ioaddr + RxGfpMem + i * 4);
1093 for (i = 0; i < tx_size; i++)
1094 writel(be32_to_cpup(&fw_tx_data[i]), ioaddr + TxGfpMem + i * 4);
1095 if (enable_hw_cksum)
1096
1097 writel(TxEnable|TxGFPEnable|RxEnable|RxGFPEnable, ioaddr + GenCtrl);
1098 else
1099
1100 writel(TxEnable|RxEnable, ioaddr + GenCtrl);
1101
1102 if (debug > 1)
1103 printk(KERN_DEBUG "%s: Done netdev_open().\n",
1104 dev->name);
1105
1106out_tx:
1107 release_firmware(fw_tx);
1108out_rx:
1109 release_firmware(fw_rx);
1110out_init:
1111 if (retval)
1112 netdev_close(dev);
1113 return retval;
1114}
1115
1116
1117static void check_duplex(struct net_device *dev)
1118{
1119 struct netdev_private *np = netdev_priv(dev);
1120 u16 reg0;
1121 int silly_count = 1000;
1122
1123 mdio_write(dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising);
1124 mdio_write(dev, np->phys[0], MII_BMCR, BMCR_RESET);
1125 udelay(500);
1126 while (--silly_count && mdio_read(dev, np->phys[0], MII_BMCR) & BMCR_RESET)
1127 ;
1128 if (!silly_count) {
1129 printk("%s: MII reset failed!\n", dev->name);
1130 return;
1131 }
1132
1133 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1134
1135 if (!np->mii_if.force_media) {
1136 reg0 |= BMCR_ANENABLE | BMCR_ANRESTART;
1137 } else {
1138 reg0 &= ~(BMCR_ANENABLE | BMCR_ANRESTART);
1139 if (np->speed100)
1140 reg0 |= BMCR_SPEED100;
1141 if (np->mii_if.full_duplex)
1142 reg0 |= BMCR_FULLDPLX;
1143 printk(KERN_DEBUG "%s: Link forced to %sMbit %s-duplex\n",
1144 dev->name,
1145 np->speed100 ? "100" : "10",
1146 np->mii_if.full_duplex ? "full" : "half");
1147 }
1148 mdio_write(dev, np->phys[0], MII_BMCR, reg0);
1149}
1150
1151
1152static void tx_timeout(struct net_device *dev)
1153{
1154 struct netdev_private *np = netdev_priv(dev);
1155 void __iomem *ioaddr = np->base;
1156 int old_debug;
1157
1158 printk(KERN_WARNING "%s: Transmit timed out, status %#8.8x, "
1159 "resetting...\n", dev->name, (int) readl(ioaddr + IntrStatus));
1160
1161
1162
1163
1164
1165
1166
1167 old_debug = debug;
1168 debug = 2;
1169 netdev_close(dev);
1170 netdev_open(dev);
1171 debug = old_debug;
1172
1173
1174
1175 dev->trans_start = jiffies;
1176 dev->stats.tx_errors++;
1177 netif_wake_queue(dev);
1178}
1179
1180
1181
1182static void init_ring(struct net_device *dev)
1183{
1184 struct netdev_private *np = netdev_priv(dev);
1185 int i;
1186
1187 np->cur_rx = np->cur_tx = np->reap_tx = 0;
1188 np->dirty_rx = np->dirty_tx = np->rx_done = np->tx_done = 0;
1189
1190 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1191
1192
1193 for (i = 0; i < RX_RING_SIZE; i++) {
1194 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
1195 np->rx_info[i].skb = skb;
1196 if (skb == NULL)
1197 break;
1198 np->rx_info[i].mapping = pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1199 skb->dev = dev;
1200
1201 np->rx_ring[i].rxaddr = cpu_to_dma(np->rx_info[i].mapping | RxDescValid);
1202 }
1203 writew(i - 1, np->base + RxDescQIdx);
1204 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1205
1206
1207 for ( ; i < RX_RING_SIZE; i++) {
1208 np->rx_ring[i].rxaddr = 0;
1209 np->rx_info[i].skb = NULL;
1210 np->rx_info[i].mapping = 0;
1211 }
1212
1213 np->rx_ring[RX_RING_SIZE - 1].rxaddr |= cpu_to_dma(RxDescEndRing);
1214
1215
1216 for (i = 0; i < DONE_Q_SIZE; i++) {
1217 np->rx_done_q[i].status = 0;
1218 np->tx_done_q[i].status = 0;
1219 }
1220
1221 for (i = 0; i < TX_RING_SIZE; i++)
1222 memset(&np->tx_info[i], 0, sizeof(np->tx_info[i]));
1223}
1224
1225
1226static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
1227{
1228 struct netdev_private *np = netdev_priv(dev);
1229 unsigned int entry;
1230 u32 status;
1231 int i;
1232
1233
1234
1235
1236
1237 if ((np->cur_tx - np->dirty_tx) + skb_num_frags(skb) * 2 > TX_RING_SIZE) {
1238 netif_stop_queue(dev);
1239 return NETDEV_TX_BUSY;
1240 }
1241
1242#if defined(ZEROCOPY) && defined(HAS_BROKEN_FIRMWARE)
1243 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1244 if (skb_padto(skb, (skb->len + PADDING_MASK) & ~PADDING_MASK))
1245 return NETDEV_TX_OK;
1246 }
1247#endif
1248
1249 entry = np->cur_tx % TX_RING_SIZE;
1250 for (i = 0; i < skb_num_frags(skb); i++) {
1251 int wrap_ring = 0;
1252 status = TxDescID;
1253
1254 if (i == 0) {
1255 np->tx_info[entry].skb = skb;
1256 status |= TxCRCEn;
1257 if (entry >= TX_RING_SIZE - skb_num_frags(skb)) {
1258 status |= TxRingWrap;
1259 wrap_ring = 1;
1260 }
1261 if (np->reap_tx) {
1262 status |= TxDescIntr;
1263 np->reap_tx = 0;
1264 }
1265 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1266 status |= TxCalTCP;
1267 dev->stats.tx_compressed++;
1268 }
1269 status |= skb_first_frag_len(skb) | (skb_num_frags(skb) << 16);
1270
1271 np->tx_info[entry].mapping =
1272 pci_map_single(np->pci_dev, skb->data, skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1273 } else {
1274 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[i - 1];
1275 status |= this_frag->size;
1276 np->tx_info[entry].mapping =
1277 pci_map_single(np->pci_dev, page_address(this_frag->page) + this_frag->page_offset, this_frag->size, PCI_DMA_TODEVICE);
1278 }
1279
1280 np->tx_ring[entry].addr = cpu_to_dma(np->tx_info[entry].mapping);
1281 np->tx_ring[entry].status = cpu_to_le32(status);
1282 if (debug > 3)
1283 printk(KERN_DEBUG "%s: Tx #%d/#%d slot %d status %#8.8x.\n",
1284 dev->name, np->cur_tx, np->dirty_tx,
1285 entry, status);
1286 if (wrap_ring) {
1287 np->tx_info[entry].used_slots = TX_RING_SIZE - entry;
1288 np->cur_tx += np->tx_info[entry].used_slots;
1289 entry = 0;
1290 } else {
1291 np->tx_info[entry].used_slots = 1;
1292 np->cur_tx += np->tx_info[entry].used_slots;
1293 entry++;
1294 }
1295
1296 if (np->cur_tx % (TX_RING_SIZE / 2) == 0)
1297 np->reap_tx = 1;
1298 }
1299
1300
1301
1302
1303 wmb();
1304
1305
1306 writel(entry * (sizeof(starfire_tx_desc) / 8), np->base + TxProducerIdx);
1307
1308
1309 if ((np->cur_tx - np->dirty_tx) + 4 > TX_RING_SIZE)
1310 netif_stop_queue(dev);
1311
1312 return NETDEV_TX_OK;
1313}
1314
1315
1316
1317
1318static irqreturn_t intr_handler(int irq, void *dev_instance)
1319{
1320 struct net_device *dev = dev_instance;
1321 struct netdev_private *np = netdev_priv(dev);
1322 void __iomem *ioaddr = np->base;
1323 int boguscnt = max_interrupt_work;
1324 int consumer;
1325 int tx_status;
1326 int handled = 0;
1327
1328 do {
1329 u32 intr_status = readl(ioaddr + IntrClear);
1330
1331 if (debug > 4)
1332 printk(KERN_DEBUG "%s: Interrupt status %#8.8x.\n",
1333 dev->name, intr_status);
1334
1335 if (intr_status == 0 || intr_status == (u32) -1)
1336 break;
1337
1338 handled = 1;
1339
1340 if (intr_status & (IntrRxDone | IntrRxEmpty)) {
1341 u32 enable;
1342
1343 if (likely(napi_schedule_prep(&np->napi))) {
1344 __napi_schedule(&np->napi);
1345 enable = readl(ioaddr + IntrEnable);
1346 enable &= ~(IntrRxDone | IntrRxEmpty);
1347 writel(enable, ioaddr + IntrEnable);
1348
1349 readl(ioaddr + IntrEnable);
1350 } else {
1351
1352 enable = readl(ioaddr + IntrEnable);
1353 if (enable & (IntrRxDone | IntrRxEmpty)) {
1354 printk(KERN_INFO
1355 "%s: interrupt while in poll!\n",
1356 dev->name);
1357 enable &= ~(IntrRxDone | IntrRxEmpty);
1358 writel(enable, ioaddr + IntrEnable);
1359 }
1360 }
1361 }
1362
1363
1364
1365
1366 consumer = readl(ioaddr + TxConsumerIdx);
1367 if (debug > 3)
1368 printk(KERN_DEBUG "%s: Tx Consumer index is %d.\n",
1369 dev->name, consumer);
1370
1371 while ((tx_status = le32_to_cpu(np->tx_done_q[np->tx_done].status)) != 0) {
1372 if (debug > 3)
1373 printk(KERN_DEBUG "%s: Tx completion #%d entry %d is %#8.8x.\n",
1374 dev->name, np->dirty_tx, np->tx_done, tx_status);
1375 if ((tx_status & 0xe0000000) == 0xa0000000) {
1376 dev->stats.tx_packets++;
1377 } else if ((tx_status & 0xe0000000) == 0x80000000) {
1378 u16 entry = (tx_status & 0x7fff) / sizeof(starfire_tx_desc);
1379 struct sk_buff *skb = np->tx_info[entry].skb;
1380 np->tx_info[entry].skb = NULL;
1381 pci_unmap_single(np->pci_dev,
1382 np->tx_info[entry].mapping,
1383 skb_first_frag_len(skb),
1384 PCI_DMA_TODEVICE);
1385 np->tx_info[entry].mapping = 0;
1386 np->dirty_tx += np->tx_info[entry].used_slots;
1387 entry = (entry + np->tx_info[entry].used_slots) % TX_RING_SIZE;
1388 {
1389 int i;
1390 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1391 pci_unmap_single(np->pci_dev,
1392 np->tx_info[entry].mapping,
1393 skb_shinfo(skb)->frags[i].size,
1394 PCI_DMA_TODEVICE);
1395 np->dirty_tx++;
1396 entry++;
1397 }
1398 }
1399
1400 dev_kfree_skb_irq(skb);
1401 }
1402 np->tx_done_q[np->tx_done].status = 0;
1403 np->tx_done = (np->tx_done + 1) % DONE_Q_SIZE;
1404 }
1405 writew(np->tx_done, ioaddr + CompletionQConsumerIdx + 2);
1406
1407 if (netif_queue_stopped(dev) &&
1408 (np->cur_tx - np->dirty_tx + 4 < TX_RING_SIZE)) {
1409
1410 netif_wake_queue(dev);
1411 }
1412
1413
1414 if (intr_status & IntrStatsMax)
1415 get_stats(dev);
1416
1417
1418 if (intr_status & IntrLinkChange)
1419 netdev_media_change(dev);
1420
1421
1422 if (intr_status & IntrAbnormalSummary)
1423 netdev_error(dev, intr_status);
1424
1425 if (--boguscnt < 0) {
1426 if (debug > 1)
1427 printk(KERN_WARNING "%s: Too much work at interrupt, "
1428 "status=%#8.8x.\n",
1429 dev->name, intr_status);
1430 break;
1431 }
1432 } while (1);
1433
1434 if (debug > 4)
1435 printk(KERN_DEBUG "%s: exiting interrupt, status=%#8.8x.\n",
1436 dev->name, (int) readl(ioaddr + IntrStatus));
1437 return IRQ_RETVAL(handled);
1438}
1439
1440
1441
1442
1443
1444
1445static int __netdev_rx(struct net_device *dev, int *quota)
1446{
1447 struct netdev_private *np = netdev_priv(dev);
1448 u32 desc_status;
1449 int retcode = 0;
1450
1451
1452 while ((desc_status = le32_to_cpu(np->rx_done_q[np->rx_done].status)) != 0) {
1453 struct sk_buff *skb;
1454 u16 pkt_len;
1455 int entry;
1456 rx_done_desc *desc = &np->rx_done_q[np->rx_done];
1457
1458 if (debug > 4)
1459 printk(KERN_DEBUG " netdev_rx() status of %d was %#8.8x.\n", np->rx_done, desc_status);
1460 if (!(desc_status & RxOK)) {
1461
1462 if (debug > 2)
1463 printk(KERN_DEBUG " netdev_rx() Rx error was %#8.8x.\n", desc_status);
1464 dev->stats.rx_errors++;
1465 if (desc_status & RxFIFOErr)
1466 dev->stats.rx_fifo_errors++;
1467 goto next_rx;
1468 }
1469
1470 if (*quota <= 0) {
1471 retcode = 1;
1472 goto out;
1473 }
1474 (*quota)--;
1475
1476 pkt_len = desc_status;
1477 entry = (desc_status >> 16) & 0x7ff;
1478
1479 if (debug > 4)
1480 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d, quota %d.\n", pkt_len, *quota);
1481
1482
1483 if (pkt_len < rx_copybreak &&
1484 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1485 skb_reserve(skb, 2);
1486 pci_dma_sync_single_for_cpu(np->pci_dev,
1487 np->rx_info[entry].mapping,
1488 pkt_len, PCI_DMA_FROMDEVICE);
1489 skb_copy_to_linear_data(skb, np->rx_info[entry].skb->data, pkt_len);
1490 pci_dma_sync_single_for_device(np->pci_dev,
1491 np->rx_info[entry].mapping,
1492 pkt_len, PCI_DMA_FROMDEVICE);
1493 skb_put(skb, pkt_len);
1494 } else {
1495 pci_unmap_single(np->pci_dev, np->rx_info[entry].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1496 skb = np->rx_info[entry].skb;
1497 skb_put(skb, pkt_len);
1498 np->rx_info[entry].skb = NULL;
1499 np->rx_info[entry].mapping = 0;
1500 }
1501#ifndef final_version
1502
1503 if (debug > 5) {
1504 printk(KERN_DEBUG " Rx data %pM %pM %2.2x%2.2x.\n",
1505 skb->data, skb->data + 6,
1506 skb->data[12], skb->data[13]);
1507 }
1508#endif
1509
1510 skb->protocol = eth_type_trans(skb, dev);
1511#ifdef VLAN_SUPPORT
1512 if (debug > 4)
1513 printk(KERN_DEBUG " netdev_rx() status2 of %d was %#4.4x.\n", np->rx_done, le16_to_cpu(desc->status2));
1514#endif
1515 if (le16_to_cpu(desc->status2) & 0x0100) {
1516 skb->ip_summed = CHECKSUM_UNNECESSARY;
1517 dev->stats.rx_compressed++;
1518 }
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528 else if (le16_to_cpu(desc->status2) & 0x0040) {
1529 skb->ip_summed = CHECKSUM_COMPLETE;
1530 skb->csum = le16_to_cpu(desc->csum);
1531 printk(KERN_DEBUG "%s: checksum_hw, status2 = %#x\n", dev->name, le16_to_cpu(desc->status2));
1532 }
1533#ifdef VLAN_SUPPORT
1534 if (np->vlgrp && le16_to_cpu(desc->status2) & 0x0200) {
1535 u16 vlid = le16_to_cpu(desc->vlanid);
1536
1537 if (debug > 4) {
1538 printk(KERN_DEBUG " netdev_rx() vlanid = %d\n",
1539 vlid);
1540 }
1541
1542
1543
1544
1545 vlan_hwaccel_rx(skb, np->vlgrp, vlid);
1546 } else
1547#endif
1548 netif_receive_skb(skb);
1549 dev->stats.rx_packets++;
1550
1551 next_rx:
1552 np->cur_rx++;
1553 desc->status = 0;
1554 np->rx_done = (np->rx_done + 1) % DONE_Q_SIZE;
1555 }
1556
1557 if (*quota == 0) {
1558 retcode = 1;
1559 goto out;
1560 }
1561 writew(np->rx_done, np->base + CompletionQConsumerIdx);
1562
1563 out:
1564 refill_rx_ring(dev);
1565 if (debug > 5)
1566 printk(KERN_DEBUG " exiting netdev_rx(): %d, status of %d was %#8.8x.\n",
1567 retcode, np->rx_done, desc_status);
1568 return retcode;
1569}
1570
1571static int netdev_poll(struct napi_struct *napi, int budget)
1572{
1573 struct netdev_private *np = container_of(napi, struct netdev_private, napi);
1574 struct net_device *dev = np->dev;
1575 u32 intr_status;
1576 void __iomem *ioaddr = np->base;
1577 int quota = budget;
1578
1579 do {
1580 writel(IntrRxDone | IntrRxEmpty, ioaddr + IntrClear);
1581
1582 if (__netdev_rx(dev, "a))
1583 goto out;
1584
1585 intr_status = readl(ioaddr + IntrStatus);
1586 } while (intr_status & (IntrRxDone | IntrRxEmpty));
1587
1588 napi_complete(napi);
1589 intr_status = readl(ioaddr + IntrEnable);
1590 intr_status |= IntrRxDone | IntrRxEmpty;
1591 writel(intr_status, ioaddr + IntrEnable);
1592
1593 out:
1594 if (debug > 5)
1595 printk(KERN_DEBUG " exiting netdev_poll(): %d.\n",
1596 budget - quota);
1597
1598
1599 return budget - quota;
1600}
1601
1602static void refill_rx_ring(struct net_device *dev)
1603{
1604 struct netdev_private *np = netdev_priv(dev);
1605 struct sk_buff *skb;
1606 int entry = -1;
1607
1608
1609 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1610 entry = np->dirty_rx % RX_RING_SIZE;
1611 if (np->rx_info[entry].skb == NULL) {
1612 skb = dev_alloc_skb(np->rx_buf_sz);
1613 np->rx_info[entry].skb = skb;
1614 if (skb == NULL)
1615 break;
1616 np->rx_info[entry].mapping =
1617 pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1618 skb->dev = dev;
1619 np->rx_ring[entry].rxaddr =
1620 cpu_to_dma(np->rx_info[entry].mapping | RxDescValid);
1621 }
1622 if (entry == RX_RING_SIZE - 1)
1623 np->rx_ring[entry].rxaddr |= cpu_to_dma(RxDescEndRing);
1624 }
1625 if (entry >= 0)
1626 writew(entry, np->base + RxDescQIdx);
1627}
1628
1629
1630static void netdev_media_change(struct net_device *dev)
1631{
1632 struct netdev_private *np = netdev_priv(dev);
1633 void __iomem *ioaddr = np->base;
1634 u16 reg0, reg1, reg4, reg5;
1635 u32 new_tx_mode;
1636 u32 new_intr_timer_ctrl;
1637
1638
1639 mdio_read(dev, np->phys[0], MII_BMCR);
1640 mdio_read(dev, np->phys[0], MII_BMSR);
1641
1642 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1643 reg1 = mdio_read(dev, np->phys[0], MII_BMSR);
1644
1645 if (reg1 & BMSR_LSTATUS) {
1646
1647 if (reg0 & BMCR_ANENABLE) {
1648
1649 reg4 = mdio_read(dev, np->phys[0], MII_ADVERTISE);
1650 reg5 = mdio_read(dev, np->phys[0], MII_LPA);
1651 if (reg4 & ADVERTISE_100FULL && reg5 & LPA_100FULL) {
1652 np->speed100 = 1;
1653 np->mii_if.full_duplex = 1;
1654 } else if (reg4 & ADVERTISE_100HALF && reg5 & LPA_100HALF) {
1655 np->speed100 = 1;
1656 np->mii_if.full_duplex = 0;
1657 } else if (reg4 & ADVERTISE_10FULL && reg5 & LPA_10FULL) {
1658 np->speed100 = 0;
1659 np->mii_if.full_duplex = 1;
1660 } else {
1661 np->speed100 = 0;
1662 np->mii_if.full_duplex = 0;
1663 }
1664 } else {
1665
1666 if (reg0 & BMCR_SPEED100)
1667 np->speed100 = 1;
1668 else
1669 np->speed100 = 0;
1670 if (reg0 & BMCR_FULLDPLX)
1671 np->mii_if.full_duplex = 1;
1672 else
1673 np->mii_if.full_duplex = 0;
1674 }
1675 netif_carrier_on(dev);
1676 printk(KERN_DEBUG "%s: Link is up, running at %sMbit %s-duplex\n",
1677 dev->name,
1678 np->speed100 ? "100" : "10",
1679 np->mii_if.full_duplex ? "full" : "half");
1680
1681 new_tx_mode = np->tx_mode & ~FullDuplex;
1682 if (np->mii_if.full_duplex)
1683 new_tx_mode |= FullDuplex;
1684 if (np->tx_mode != new_tx_mode) {
1685 np->tx_mode = new_tx_mode;
1686 writel(np->tx_mode | MiiSoftReset, ioaddr + TxMode);
1687 udelay(1000);
1688 writel(np->tx_mode, ioaddr + TxMode);
1689 }
1690
1691 new_intr_timer_ctrl = np->intr_timer_ctrl & ~Timer10X;
1692 if (np->speed100)
1693 new_intr_timer_ctrl |= Timer10X;
1694 if (np->intr_timer_ctrl != new_intr_timer_ctrl) {
1695 np->intr_timer_ctrl = new_intr_timer_ctrl;
1696 writel(new_intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1697 }
1698 } else {
1699 netif_carrier_off(dev);
1700 printk(KERN_DEBUG "%s: Link is down\n", dev->name);
1701 }
1702}
1703
1704
1705static void netdev_error(struct net_device *dev, int intr_status)
1706{
1707 struct netdev_private *np = netdev_priv(dev);
1708
1709
1710 if (intr_status & IntrTxDataLow) {
1711 if (np->tx_threshold <= PKT_BUF_SZ / 16) {
1712 writel(++np->tx_threshold, np->base + TxThreshold);
1713 printk(KERN_NOTICE "%s: PCI bus congestion, increasing Tx FIFO threshold to %d bytes\n",
1714 dev->name, np->tx_threshold * 16);
1715 } else
1716 printk(KERN_WARNING "%s: PCI Tx underflow -- adapter is probably malfunctioning\n", dev->name);
1717 }
1718 if (intr_status & IntrRxGFPDead) {
1719 dev->stats.rx_fifo_errors++;
1720 dev->stats.rx_errors++;
1721 }
1722 if (intr_status & (IntrNoTxCsum | IntrDMAErr)) {
1723 dev->stats.tx_fifo_errors++;
1724 dev->stats.tx_errors++;
1725 }
1726 if ((intr_status & ~(IntrNormalMask | IntrAbnormalSummary | IntrLinkChange | IntrStatsMax | IntrTxDataLow | IntrRxGFPDead | IntrNoTxCsum | IntrPCIPad)) && debug)
1727 printk(KERN_ERR "%s: Something Wicked happened! %#8.8x.\n",
1728 dev->name, intr_status);
1729}
1730
1731
1732static struct net_device_stats *get_stats(struct net_device *dev)
1733{
1734 struct netdev_private *np = netdev_priv(dev);
1735 void __iomem *ioaddr = np->base;
1736
1737
1738 dev->stats.tx_bytes = readl(ioaddr + 0x57010);
1739 dev->stats.rx_bytes = readl(ioaddr + 0x57044);
1740 dev->stats.tx_packets = readl(ioaddr + 0x57000);
1741 dev->stats.tx_aborted_errors =
1742 readl(ioaddr + 0x57024) + readl(ioaddr + 0x57028);
1743 dev->stats.tx_window_errors = readl(ioaddr + 0x57018);
1744 dev->stats.collisions =
1745 readl(ioaddr + 0x57004) + readl(ioaddr + 0x57008);
1746
1747
1748 dev->stats.rx_dropped += readw(ioaddr + RxDMAStatus);
1749 writew(0, ioaddr + RxDMAStatus);
1750 dev->stats.rx_crc_errors = readl(ioaddr + 0x5703C);
1751 dev->stats.rx_frame_errors = readl(ioaddr + 0x57040);
1752 dev->stats.rx_length_errors = readl(ioaddr + 0x57058);
1753 dev->stats.rx_missed_errors = readl(ioaddr + 0x5707C);
1754
1755 return &dev->stats;
1756}
1757
1758
1759static void set_rx_mode(struct net_device *dev)
1760{
1761 struct netdev_private *np = netdev_priv(dev);
1762 void __iomem *ioaddr = np->base;
1763 u32 rx_mode = MinVLANPrio;
1764 struct netdev_hw_addr *ha;
1765 int i;
1766#ifdef VLAN_SUPPORT
1767
1768 rx_mode |= VlanMode;
1769 if (np->vlgrp) {
1770 int vlan_count = 0;
1771 void __iomem *filter_addr = ioaddr + HashTable + 8;
1772 for (i = 0; i < VLAN_VID_MASK; i++) {
1773 if (vlan_group_get_device(np->vlgrp, i)) {
1774 if (vlan_count >= 32)
1775 break;
1776 writew(i, filter_addr);
1777 filter_addr += 16;
1778 vlan_count++;
1779 }
1780 }
1781 if (i == VLAN_VID_MASK) {
1782 rx_mode |= PerfectFilterVlan;
1783 while (vlan_count < 32) {
1784 writew(0, filter_addr);
1785 filter_addr += 16;
1786 vlan_count++;
1787 }
1788 }
1789 }
1790#endif
1791
1792 if (dev->flags & IFF_PROMISC) {
1793 rx_mode |= AcceptAll;
1794 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
1795 (dev->flags & IFF_ALLMULTI)) {
1796
1797 rx_mode |= AcceptBroadcast|AcceptAllMulticast|PerfectFilter;
1798 } else if (netdev_mc_count(dev) <= 14) {
1799
1800 void __iomem *filter_addr = ioaddr + PerfFilterTable + 2 * 16;
1801 __be16 *eaddrs;
1802 netdev_for_each_mc_addr(ha, dev) {
1803 eaddrs = (__be16 *) ha->addr;
1804 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 4;
1805 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1806 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 8;
1807 }
1808 eaddrs = (__be16 *)dev->dev_addr;
1809 i = netdev_mc_count(dev) + 2;
1810 while (i++ < 16) {
1811 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
1812 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1813 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
1814 }
1815 rx_mode |= AcceptBroadcast|PerfectFilter;
1816 } else {
1817
1818 void __iomem *filter_addr;
1819 __be16 *eaddrs;
1820 __le16 mc_filter[32] __attribute__ ((aligned(sizeof(long))));
1821
1822 memset(mc_filter, 0, sizeof(mc_filter));
1823 netdev_for_each_mc_addr(ha, dev) {
1824
1825
1826 int bit_nr = ether_crc_le(ETH_ALEN, ha->addr) >> 23;
1827 __le32 *fptr = (__le32 *) &mc_filter[(bit_nr >> 4) & ~1];
1828
1829 *fptr |= cpu_to_le32(1 << (bit_nr & 31));
1830 }
1831
1832 filter_addr = ioaddr + PerfFilterTable + 2 * 16;
1833 eaddrs = (__be16 *)dev->dev_addr;
1834 for (i = 2; i < 16; i++) {
1835 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
1836 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1837 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
1838 }
1839 for (filter_addr = ioaddr + HashTable, i = 0; i < 32; filter_addr+= 16, i++)
1840 writew(mc_filter[i], filter_addr);
1841 rx_mode |= AcceptBroadcast|PerfectFilter|HashFilter;
1842 }
1843 writel(rx_mode, ioaddr + RxFilterMode);
1844}
1845
1846static int check_if_running(struct net_device *dev)
1847{
1848 if (!netif_running(dev))
1849 return -EINVAL;
1850 return 0;
1851}
1852
1853static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1854{
1855 struct netdev_private *np = netdev_priv(dev);
1856 strcpy(info->driver, DRV_NAME);
1857 strcpy(info->version, DRV_VERSION);
1858 strcpy(info->bus_info, pci_name(np->pci_dev));
1859}
1860
1861static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1862{
1863 struct netdev_private *np = netdev_priv(dev);
1864 spin_lock_irq(&np->lock);
1865 mii_ethtool_gset(&np->mii_if, ecmd);
1866 spin_unlock_irq(&np->lock);
1867 return 0;
1868}
1869
1870static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1871{
1872 struct netdev_private *np = netdev_priv(dev);
1873 int res;
1874 spin_lock_irq(&np->lock);
1875 res = mii_ethtool_sset(&np->mii_if, ecmd);
1876 spin_unlock_irq(&np->lock);
1877 check_duplex(dev);
1878 return res;
1879}
1880
1881static int nway_reset(struct net_device *dev)
1882{
1883 struct netdev_private *np = netdev_priv(dev);
1884 return mii_nway_restart(&np->mii_if);
1885}
1886
1887static u32 get_link(struct net_device *dev)
1888{
1889 struct netdev_private *np = netdev_priv(dev);
1890 return mii_link_ok(&np->mii_if);
1891}
1892
1893static u32 get_msglevel(struct net_device *dev)
1894{
1895 return debug;
1896}
1897
1898static void set_msglevel(struct net_device *dev, u32 val)
1899{
1900 debug = val;
1901}
1902
1903static const struct ethtool_ops ethtool_ops = {
1904 .begin = check_if_running,
1905 .get_drvinfo = get_drvinfo,
1906 .get_settings = get_settings,
1907 .set_settings = set_settings,
1908 .nway_reset = nway_reset,
1909 .get_link = get_link,
1910 .get_msglevel = get_msglevel,
1911 .set_msglevel = set_msglevel,
1912};
1913
1914static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1915{
1916 struct netdev_private *np = netdev_priv(dev);
1917 struct mii_ioctl_data *data = if_mii(rq);
1918 int rc;
1919
1920 if (!netif_running(dev))
1921 return -EINVAL;
1922
1923 spin_lock_irq(&np->lock);
1924 rc = generic_mii_ioctl(&np->mii_if, data, cmd, NULL);
1925 spin_unlock_irq(&np->lock);
1926
1927 if ((cmd == SIOCSMIIREG) && (data->phy_id == np->phys[0]))
1928 check_duplex(dev);
1929
1930 return rc;
1931}
1932
1933static int netdev_close(struct net_device *dev)
1934{
1935 struct netdev_private *np = netdev_priv(dev);
1936 void __iomem *ioaddr = np->base;
1937 int i;
1938
1939 netif_stop_queue(dev);
1940
1941 napi_disable(&np->napi);
1942
1943 if (debug > 1) {
1944 printk(KERN_DEBUG "%s: Shutting down ethercard, Intr status %#8.8x.\n",
1945 dev->name, (int) readl(ioaddr + IntrStatus));
1946 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1947 dev->name, np->cur_tx, np->dirty_tx,
1948 np->cur_rx, np->dirty_rx);
1949 }
1950
1951
1952 writel(0, ioaddr + IntrEnable);
1953
1954
1955 writel(0, ioaddr + GenCtrl);
1956 readl(ioaddr + GenCtrl);
1957
1958 if (debug > 5) {
1959 printk(KERN_DEBUG" Tx ring at %#llx:\n",
1960 (long long) np->tx_ring_dma);
1961 for (i = 0; i < 8 ; i++)
1962 printk(KERN_DEBUG " #%d desc. %#8.8x %#llx -> %#8.8x.\n",
1963 i, le32_to_cpu(np->tx_ring[i].status),
1964 (long long) dma_to_cpu(np->tx_ring[i].addr),
1965 le32_to_cpu(np->tx_done_q[i].status));
1966 printk(KERN_DEBUG " Rx ring at %#llx -> %p:\n",
1967 (long long) np->rx_ring_dma, np->rx_done_q);
1968 if (np->rx_done_q)
1969 for (i = 0; i < 8 ; i++) {
1970 printk(KERN_DEBUG " #%d desc. %#llx -> %#8.8x\n",
1971 i, (long long) dma_to_cpu(np->rx_ring[i].rxaddr), le32_to_cpu(np->rx_done_q[i].status));
1972 }
1973 }
1974
1975 free_irq(dev->irq, dev);
1976
1977
1978 for (i = 0; i < RX_RING_SIZE; i++) {
1979 np->rx_ring[i].rxaddr = cpu_to_dma(0xBADF00D0);
1980 if (np->rx_info[i].skb != NULL) {
1981 pci_unmap_single(np->pci_dev, np->rx_info[i].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1982 dev_kfree_skb(np->rx_info[i].skb);
1983 }
1984 np->rx_info[i].skb = NULL;
1985 np->rx_info[i].mapping = 0;
1986 }
1987 for (i = 0; i < TX_RING_SIZE; i++) {
1988 struct sk_buff *skb = np->tx_info[i].skb;
1989 if (skb == NULL)
1990 continue;
1991 pci_unmap_single(np->pci_dev,
1992 np->tx_info[i].mapping,
1993 skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1994 np->tx_info[i].mapping = 0;
1995 dev_kfree_skb(skb);
1996 np->tx_info[i].skb = NULL;
1997 }
1998
1999 return 0;
2000}
2001
2002#ifdef CONFIG_PM
2003static int starfire_suspend(struct pci_dev *pdev, pm_message_t state)
2004{
2005 struct net_device *dev = pci_get_drvdata(pdev);
2006
2007 if (netif_running(dev)) {
2008 netif_device_detach(dev);
2009 netdev_close(dev);
2010 }
2011
2012 pci_save_state(pdev);
2013 pci_set_power_state(pdev, pci_choose_state(pdev,state));
2014
2015 return 0;
2016}
2017
2018static int starfire_resume(struct pci_dev *pdev)
2019{
2020 struct net_device *dev = pci_get_drvdata(pdev);
2021
2022 pci_set_power_state(pdev, PCI_D0);
2023 pci_restore_state(pdev);
2024
2025 if (netif_running(dev)) {
2026 netdev_open(dev);
2027 netif_device_attach(dev);
2028 }
2029
2030 return 0;
2031}
2032#endif
2033
2034
2035static void __devexit starfire_remove_one (struct pci_dev *pdev)
2036{
2037 struct net_device *dev = pci_get_drvdata(pdev);
2038 struct netdev_private *np = netdev_priv(dev);
2039
2040 BUG_ON(!dev);
2041
2042 unregister_netdev(dev);
2043
2044 if (np->queue_mem)
2045 pci_free_consistent(pdev, np->queue_mem_size, np->queue_mem, np->queue_mem_dma);
2046
2047
2048
2049 pci_set_power_state(pdev, PCI_D3hot);
2050 pci_disable_device(pdev);
2051
2052 iounmap(np->base);
2053 pci_release_regions(pdev);
2054
2055 pci_set_drvdata(pdev, NULL);
2056 free_netdev(dev);
2057}
2058
2059
2060static struct pci_driver starfire_driver = {
2061 .name = DRV_NAME,
2062 .probe = starfire_init_one,
2063 .remove = __devexit_p(starfire_remove_one),
2064#ifdef CONFIG_PM
2065 .suspend = starfire_suspend,
2066 .resume = starfire_resume,
2067#endif
2068 .id_table = starfire_pci_tbl,
2069};
2070
2071
2072static int __init starfire_init (void)
2073{
2074
2075#ifdef MODULE
2076 printk(version);
2077
2078 printk(KERN_INFO DRV_NAME ": polling (NAPI) enabled\n");
2079#endif
2080
2081 BUILD_BUG_ON(sizeof(dma_addr_t) != sizeof(netdrv_addr_t));
2082
2083 return pci_register_driver(&starfire_driver);
2084}
2085
2086
2087static void __exit starfire_cleanup (void)
2088{
2089 pci_unregister_driver (&starfire_driver);
2090}
2091
2092
2093module_init(starfire_init);
2094module_exit(starfire_cleanup);
2095
2096
2097
2098
2099
2100
2101
2102
2103